Speedster22i DDR3 User Guide (UG031)

Speedster22i DDR3 User Guide (UG031) Speedster FPGAs Speedster FPGAs www.achronix.com 1 Speedster22i DDR3 User Guide (UG031) Copyrights, Trademarks and Disclaimers Copyright © 2018 Achronix Semiconductor Corporation. All rights reserved. Achronix, Speedcore, Speedster, and ACE are trademarks of Achronix Semiconductor Corporation in the U.S. and/or other countries All other trademarks are the property of their respective owners. All specifications subject to change without notice. NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable. However, Achronix Semiconductor Corporation does not give any representations or warranties as to the completeness or accuracy of such information and shall have no liability for the use of the information contained herein. Achronix Semiconductor Corporation reserves the right to make changes to this document and the information contained herein at any time and without notice. All Achronix trademarks, registered trademarks, disclaimers and patents are listed at http://www.achronix.com/legal. Achronix Semiconductor Corporation 2903 Bunker Hill Lane Santa Clara, CA 95054 USA Website: www.achronix.com E-mail : [email protected] 2 www.achronix.com Speedster FPGAs Speedster22i DDR3 User Guide (UG031) Table of Contents Chapter - 1: Introduction . 7 Features . 7 Functional Overview . 8 Chapter - 2: DDR3 Macro Interfaces . 10 Internal (Core-side) Interface . 10 External (Memory) Interface . 13 DDR3 Macro Block Diagram . 15 Chapter - 3: DDR3 Core Parameters . 16 Chapter - 4: Read and Write Operations . 21 Read Interface Details . 21 Read Protocol 2× Clock Mode . 21 Back-to-Back Read Protocol 2× Clock Mode . 23 Write Interface Details . 25 Write Protocol 2× Clock Mode . 25 Back-to-Back Write Protocol 2× Clock Mode . 29 Chapter - 5: Address Mapping . 32 Chapter - 6: Board Design and Layout . 34 Routing Guidelines and Trace Matching . 34 Board-Level Simulation . 34 DDR3 Routing Guidelines . 34 High-Level Rules . 35 Guidelines . 37 Stack-up . 45 Chapter - 7: PHY Architecture . 51 Overview . 51 Clock and Reset Architectures . 51 Overview . 51 Clocks . 51 Resets . 53 Example Use Cases . 54 Speedster FPGAs www.achronix.com 3 Speedster22i DDR3 User Guide (UG031) DLL and Write/Read Leveling . 62 DLL Specs and Operation . 62 Soft Write/Read Leveling . 63 Read-Leveling Values . 64 Write-Leveling Values . 64 Chapter - 8: Memory Interface Latency . 65 Chapter - 9: SPD Parameters and Configuration . 66 Manual Setting with Parameter Calculator . 66 Step 1. Collect Data . 66 Step 2. Enter Data into the Spreadsheet . 66 Step 3. Transfer the Calculated Values to the Macro . 68 Step 4. Regenerate the Bitstream for the Revised Design . 68 Automated I2C Read and Update . 68 Chapter - 10: ACE Macro Generation and Integration . 69 Overview . 69 DDR3 IP Diagrams . 69 Sections . 73 DDR3 Configuration Editor Overview Page . 73 DDR3 Configuration Editor Memory Timing Page . 77 DDR3 Configuration Editor DLL Timing Page . 80 DDR3 Configuration Editor DQS Preamble Page . 82 DDR3 Controller Placement Constraints . ..

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