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DDR and DDR2 SDRAM Controller Compiler User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive Software Version: 9.0 San Jose, CA 95134 Document Date: March 2009 www.altera.com Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap- plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. UG-DDRSDRAM-10.0 Contents Chapter 1. About This Compiler Release Information . 1–1 Device Family Support . 1–1 Features . 1–2 General Description . 1–2 Performance and Resource Utilization . 1–4 Installation and Licensing . 1–5 OpenCore Plus Evaluation . 1–6 Chapter 2. Getting Started Design Flow . 2–1 SOPC Builder Design Flow . 2–1 DDR & DDR2 SDRAM Controller Walkthrough . -
Basic Components of a Computer System
Patricio Bulic´ Basic Components Of a Computer System A Textbook October 14, 2020 Springer Contents 1 Main memory ................................................. 1 1.1 Introduction . .1 1.2 Basics of Digital Circuits: A Quick Review . .3 1.2.1 MOS transistor as a switch . .3 1.2.2 CMOS inverter . .4 1.2.3 Bistable element . .5 1.3 SRAM cell . .6 1.4 DRAM cell . .7 1.4.1 Basic operation of DRAM . .8 1.4.2 Basic operation of sense amplifiers . 10 1.5 DRAM Arrays and DRAM Banks . 11 1.6 DRAM Chips . 13 1.7 Basic DRAM operations and timings . 15 1.7.1 Reading data from DRAM memory . 16 1.7.2 Writing data to DRAM memory . 17 1.7.3 Refreshing the DRAM memory . 18 1.8 Improving the performance of a DRAM chip . 20 1.8.1 Fast Page Mode DRAM . 21 1.8.2 Extended Data Output DRAM . 22 1.9 Synchronous DRAM . 24 1.9.1 Functional description . 25 1.9.2 Basic operations and timings. 28 1.10 Double Data Rate SDRAM . 36 1.10.1 Functional description . 37 1.10.2 DDR SDRAM timing diagrams . 40 1.10.3 Address Mapping . 43 1.10.4 Memory timings: a summary . 44 1.10.5 DDR Versions . 45 1.11 DIMM Modules . 46 1.11.1 Micron DDR4 DIMM module . 49 1.12 Memory channels . 49 v vi Contents 1.12.1 Case study: Intel i7-860 memory . 52 1.12.2 Case study: i9-9900K memory . 53 1.13 Bibliographical notes . 54 References ........................................................ -
Timing Circuit Design in High Performance DRAM
Chapter 11 Timing Circuit Design in High Performance DRAM Feng (Dan) Lin Abstract The need for high performance dynamic random access memory (DRAM) becomes a pressing concern with processor speeds racing into the multi-gigahertz range. For a high performance computing system, such as high-end graphics cards or game consoles, memory bandwidth is one of the key limitations. One way to address this ever increasing bandwidth requirement is by increasing the data transfer rate. As the I/O speed jumps up, precise timing control becomes critical and challenge with variations and limitations in nano-scaled DRAM processes. In this chapter, we will explore two most important timing circuits used in high performance DRAM: clock distribution network (CDN) and clock synchronization circuits (CSC). Keywords Memory interface • DRAM • Memory bandwidth • Clock distribu- tion network (CDN) • Clock synchronization circuit (CSC) • Source-synchronous • Analog phase generator (APG) • De-skewing • Duty-cycle correction (DCC) Delay-locked loop (DLL) • 3D integration 11.1 Introduction 11.1.1 Memory Interface A typical memory system, shown in Fig. 11.1, generally includes a memory control- ler, DRAM devices and memory channels between them. As part of the DRAM device, memory interface serves as a gateway between the external world and internal periphery logics (i.e. array interface and command and address logic). The state-of-art memory interface may include data transceivers, SERDES (serializer/deserializer), F. Lin (*) Senior Member of Technical Staff, Micron Technology, Inc. e-mail: [email protected] K. Iniewski (ed.), CMOS Processors and Memories, 337 Analog Circuits and Signal Processing, DOI 10.1007/978-90-481-9216-8_11, © Springer Science+Business Media B.V. -
Table of Contents Table of Contents
Table of Contents Table of Contents UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 Form 10-K (Mark One) ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2010 or TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number: 000-22339 RAMBUS INC. (Exact name of registrant as specified in its charter) Delaware 94 -3112828 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification Number) 1050 Enterprise Way, Suite 700 94089 Sunnyvale, California (Zip Code) (Address of principal executive offices) Registrant’s telephone number, including area code: (408) 462-8000 Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Name of Each Exchange on Which Registered Common Stock, $.001 Par Value The NASDAQ Stock Market LLC (The NASDAQ Global Select Market) Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes No Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes No Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. -
DDR) SDRAM Controller (Pipelined Version) User’S Guide
ispLever TM CORECORE Double Data Rate (DDR) SDRAM Controller (Pipelined Version) User’s Guide June 2004 ipug12_03 Double Data Rate (DDR) SDRAM Controller Lattice Semiconductor (Pipelined Version) User’s Guide Introduction DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle (on both edges of the clock signal), implementing burst mode data transfer. The DDR SDRAM Controller is a parameterized core. This allows the user to modify the data widths, burst transfer rates, and CAS latency settings of the design. In addition, the DDR core supports intelligent bank management. By maintaining a database of “all banks activated” and the “rows activated” in each bank, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write com- mands issued to the DDR SDRAM. Since the DDR SDRAM Controller takes care of activating/pre-charging the banks, the user can simply issue sim- ple read/write commands without regard to the bank/charge status. Features •Performance of Greater than 100MHz (200 DDR) • Interfaces to JEDEC Standard DDR SDRAMs • Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits • Supports up to 8 External Memory Banks • Programmable Burst Lengths of 2, 4, or 8 • Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0 • Byte-level Writing Supported • Increased Throughput Using Command Pipelining and Bank Management • Supports Power-down and Self Refresh Modes •Automatic Initialization •Automatic Refresh During Normal and Power-down Modes • Timing and Settings Parameters Implemented as Programmable Registers • Bus Interfaces to PCI Target, PowerPC and AMBA (AHB) Buses Available • Complete Synchronous Implementation 2 Double Data Rate (DDR) SDRAM Controller Lattice Semiconductor (Pipelined Version) User’s Guide Figure 1. -
UNITED STATES SECURITIES and EXCHANGE COMMISSION Form
Use these links to rapidly review the document TABLE OF CONTENTS PART IV Table of Contents UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 Form 10-K (Mark One) ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2011 or TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number: 000-22339 RAMBUS INC. (Exact name of registrant as specified in its charter) Delaware 94-3112828 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification Number) 1050 Enterprise Way, Suite 700 Sunnyvale, California 94089 (Address of principal executive offices) (Zip Code) Registrant's telephone number, including area code: (408) 462-8000 Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Name of Each Exchange on Which Registered Common Stock, $.001 Par Value The NASDAQ Stock Market LLC (The NASDAQ Global Select Market) Securities registered pursuant to Section 12(g) of the Act: None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes No Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes No Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. -
RAMBUS INC. (Exact Name of Registrant As Specified in Its Charter) ______
UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 ________________ Form 10-K ________________ (Mark One) ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended December 31, 2011 or TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number: 000-22339 ________________ RAMBUS INC. (Exact name of registrant as specified in its charter) ________________ Delaware 94-3112828 (State or other jurisdiction of (I.R.S. Employer incorporation or organization) Identification Number) 1050 Enterprise Way, Suite 700 94089 Sunnyvale, California (Zip Code) (Address of principal executive offices) Registrant’s telephone number, including area code: (408) 462-8000 ________________ Securities registered pursuant to Section 12(b) of the Act: Title of Each Class Name of Each Exchange on Which Registered Common Stock, $.001 Par Value The NASDAQ Stock Market LLC (The NASDAQ Global Select Market) Securities registered pursuant to Section 12(g) of the Act: None ________________ Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes No Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes No Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. -
DDR SDRAM Controller
DDR SDRAM Controller October 2002 IP Data Sheet Features ■ Bus Interfaces to PCI Target, PowerPC and ■ AMBA (AHB) Buses Available Performance of Greater than 200MHz in ■ Complete Synchronous Implementation DDR Mode ■ Interfaces to JEDEC Standard DDR General Description SDRAMs ■ Supports DDR SDRAM Data Widths of 16, DDR (Double Data Rate) SDRAM was introduced as a 32 and 64 Bits replacement for SDRAM memory running at bus ■ Supports up to 8 External Memory Banks speeds over 75MHz. DDR SDRAM is similar in function ■ Programmable Burst Lengths of 2, 4, or 8 to the regular SDRAM but doubles the bandwidth of the ■ Programmable CAS Latency of 1.5, 2.0, 2.5 memory by transferring data twice per cycle on both or 3.0 edges of the clock signal, implementing burst mode ■ Byte-level Writing Supported data transfer. ■ Increased Performance Using Command The DDR SDRAM Controller is a parameterized core Pipelining and Bank Management giving user the flexibility for modifying the data widths, ■ Supports Power-down and Self Refresh burst transfer rates, and CAS latency settings of the Modes design. In addition, the DDR core supports intelligent ■ Automatic Initialization bank management, which is done by maintaining a ■ Automatic Refresh During Nomal and database of “all banks activated” and the “rows acti- Power-down Modes vated” in each bank. With this information, the DDR ■ Timing and Settings Parameters SDRAM Controller decides if an active or pre-charge Implemented as Programmable Registers command is needed. This effectively reduces the latency of -
All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-To-Digital Conversion Angeli, Nico (2020)
All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion Angeli, Nico (2020) DOI (TUprints): https://doi.org/10.25534/tuprints-00012975 Lizenz: CC-BY-NC-ND 4.0 International - Creative Commons, Namensnennung, nicht kom- merziell, keine Bearbeitung Publikationstyp: Dissertation Fachbereich: 18 Fachbereich Elektrotechnik und Informationstechnik Quelle des Originals: https://tuprints.ulb.tu-darmstadt.de/12975 All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion Digitale Taktsignal Kalibrierung für schnelle quellsynchrone I/O Links basierend auf Phasen-zu-digital Wandlung Zur Erlangung des akademischen Grades Doktor-Ingenieur (Dr.-Ing.) genehmigte Dissertation von M.Sc. Nico Angeli aus Würzburg Tag der Einreichung: 13. März 2020, Tag der Prüfung: 01. Juli 2020 Darmstadt — D 17 1. Gutachten: Prof. Dr.-Ing. Klaus Hofmann 2. Gutachten: Prof. Dr.-Ing. Chihao Xu Fachgebiet Integrierte Elektronische Systeme All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion Digitale Taktsignal Kalibrierung für schnelle quellsynchrone I/O Links basierend auf Phasen-zu-digital Wandlung Genehmigte Dissertation von M.Sc. Nico Angeli aus Würzburg 1. Gutachten: Prof. Dr.-Ing. Klaus Hofmann 2. Gutachten: Prof. Dr.-Ing. Chihao Xu Tag der Einreichung: 13. März 2020 Tag der Prüfung: 01. Juli 2020 Darmstadt — D 17 Bitte zitieren Sie dieses Dokument als: URN: urn:nbn:de:tuda-tuprints-129758 URL: http://tuprints.ulb.tu-darmstadt.de/12975 Dieses Dokument wird bereitgestellt von tuprints, E-Publishing-Service der TU Darmstadt http://tuprints.ulb.tu-darmstadt.de [email protected] Die Veröffentlichung steht unter folgender Creative Commons Lizenz: Namensnennung – Keine kommerzielle Nutzung – Keine Bearbeitung 4.0 International https://creativecommons.org/licenses/by-nc-nd/4.0/deed.de Erklärungen zur Dissertation § 8 Abs. -
Session 27 Overview DRAM and Eram
ISSCC 2007 / SESSION 27 / DRAM AND eRAM / OVERVIEW Session 27 Overview DRAM and eRAM Chair: Martin Brox, Qimonda, Neubiberg, Germany Associate Chair: Kazuhiko Kajigaya, Elpida Memory, Sagamihara, Japan Demand growth for electronic systems has been driven by new consumer and computing applica- tions. The most popular examples are the next-generation, high-resolution game-consoles. These systems heavily leverage the performance of today’s memories and processors. Yet, these applica- tions are still unable to create a life-like experience due to the limitations of the on- and off-chip memory bandwidth available to the processing functions. Careful optimization of the memory hier- archy bandwidth is necessary to improve system performance. High-speed embedded-DRAM (eDRAM) has evolved as a serious contender to embedded-SRAM (eSRAM), while external data- rates continue their rapid rise. However, speed improvements cannot stand on their own as system costs must be kept reasonable. To this end, good test and repair solutions reduce cost and facilitate higher levels of integra- tion. The presentations in this session report recent advances that address these challenges. Paper 27.1 by IBM introduces an innovative sense-amplifier for use in an eDRAM macro operating at a random-cycle frequen- cy of 500MHz. This macro, which occupies only 32% of an equivalent eSRAM-macro in the same SOI-technology, enables higher-density cache implementations improving system level performance. Cost, test strategy and system integration are the focus of the next two presentations. Paper 27.2 by Renesas, Shikino and Daioh, explores strategies needed for known-good-die (KGD) applications with the example of an eSRAM-macro. -
Computer Technology an Introduction
APEX TUTORS Page | 1 Computer Technology An Introduction Installation, Configuration, Connection, Troubleshooting A guide to configuring, installing, connecting and troubleshooting computer systems Page | 2 Table of Contents Table of Contents ........................................................................................................... 2 Preface............................................................................................................................ 4 Introduction .................................................................................................................... 5 CHAPTER 1 CPU.......................................................................................................... 7 CPU Packages ................................................................................................................ 7 CHAPTER 2 RAM ...................................................................................................... 19 RAM Variations ........................................................................................................... 22 CHAPTER 3 Hard Drive Technologies ....................................................................... 25 RAID ............................................................................................................................ 32 Implementing RAID .................................................................................................... 34 Solid State Disks ......................................................................................................... -
External Memory Interface Handbook Volume 2: Design Guidelines
External Memory Interface Handbook Volume 2: Design Guidelines Last updated for Altera Complete Design Suite: 15.0 Subscribe EMI_DG 101 Innovation Drive 2015.05.04 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Selecting Your Memory Contents Selecting Your Memory.......................................................................................1-1 DDR SDRAM Features............................................................................................................................... 1-2 DDR2 SDRAM Features............................................................................................................................. 1-3 DDR3 SDRAM Features............................................................................................................................. 1-3 QDR, QDR II, and QDR II+ SRAM Features..........................................................................................1-4 RLDRAM II and RLDRAM 3 Features.....................................................................................................1-4 LPDDR2 Features........................................................................................................................................ 1-6 Memory Selection........................................................................................................................................ 1-6 Example of High-Speed Memory in Embedded Processor....................................................................1-9 Example of High-Speed Memory in Telecom......................................................................................