sensors

Article LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs

Tingyou Lin 1,*, Yingchieh Ho 2,* and Chauchin Su 3

1 Institute of Communications Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan 2 Department of Electrical Engineering, National Dong-Hwa University, Hualien 97401, Taiwan 3 Department of Electrical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan; [email protected] * Correspondence: [email protected] (T.L.); [email protected] (Y.H.); Tel.: +886-3-571-2121 (ext. 54429) (T.L.)

Received: 16 April 2017; Accepted: 10 June 2017; Published: 15 June 2017

Abstract: This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width- (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 µm HV BCD processes, and total area is 900 × 914 µm2. The maximal temperature variation among the eight banks can reduce to 2.8 ◦C by the proposed thermal balancing system from 9.5 ◦C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.

Keywords: monolithic power ICs; temperature sensor; oscillator; thermal balancing; power metal-oxide-semiconductor (MOS); calibration

1. Introduction Monolithic power integrated circuits (ICs) are popular in small and medium power applications such as power modules for LED and portable devices [1–3]. High-voltage (HV) switching metal-oxide-semiconductor field-effect transistor () and low-voltage (LV) control circuits are integrated in a single chip for not only reducing the circuit footprint but also decreasing the ICs package cost. Both the static power dissipation and the power efficiency can be improved accordingly. However, thermal management and reliability are significant challenges [4–7]. Most monolithic power ICs use lateral double-diffused MOSFETs (LDMOSs) as the switching devices. They are inferior to discrete , such as vertical double-diffused MOSFETs (DMOSs) or integrated gate bipolar (IGBT) in that they have larger turn-on resistances Ron [8]. A larger Ron implies greater 2 power dissipation, Pd = IL Ron. However, the temperature distribution is affected by many kinds of factors. As the number of transistors is more than 10,000 in a discrete power MOSFET IC, the transistor’s lifetime will decrease as the channel temperature exceeds 75 ◦C. Therefore, the on-chip channel temperature sensing is necessary to optimize the operations of power MOSFET. A high-voltage power MOSFET that is constructed as a parallel MOSFET bank of multiple smaller transistors is called a large array device. The transistors are arranged in a sophisticated manner so that load current is uniformly distributed to them in parallel. Many layout styles, including multi-fingers,

Sensors 2017, 17, 1397; doi:10.3390/s17061397 www.mdpi.com/journal/sensors Sensors 2017, 17, 1397 2 of 14 Sensors 2017, 17, 1397 2 of 14 manner so that load current is uniformly distributed to them in parallel. Many layout styles, including multi-fingers, waffle, overlapping circular gate, wave, and diamond styles have been waffle,developed. overlapping However, circular the uniform gate, wave, distribution and diamond of the load styles current have is been still difficult developed. to guarantee However, [9]. the uniformFigure distribution1 shows an ofinfrared the load thermal current photograph is still difficult of a to 45 guarantee V N-type [ 9power]. Figure MOS1 shows with ana infraredpower thermaldissipation photograph of 1 W. of The a 45 temperature V N-type power at the MOSsubstrate with ring a power is 53.3–55.2 dissipation °C, and of 1 that W. Theat the temperature top metal at theabove substrate the ringtransistor is 53.3–55.2 channel◦C, is and42.4–46.1 that at °C. the However, top metal aboveboth the the temperatures transistor channel are not is 42.4–46.1the exact◦ C. However,temperature both in the the temperatures transistor channel. are not Back-end the exact layers temperature could cause in thethe transistorinfrared thermal channel. method Back-end of layerstemperature could cause measuring the infrared to yield thermal erroneous method results of temperature owing to die measuring surface condition to yield erroneous and radiative results owingtransfer to die [10]. surface As a conditionrule of thumb, and radiative every 10 transfer°C increases [10]. Asin the a rule channel of thumb, temperature every 10 decreases◦C increases the in thelifetime channel of temperature semiconductor decreases device in the a half lifetime [11]. of in a half [11].

FigureFigure 1. 1.Infrated Infrated thermalthermal photo of of a a power power MOSFET. MOSFET.

ThermalThermal resistance resistance model model is is a populara popular method method to to derive derive channel channel temperature temperature from from the the case case or or the ambientthe ambient temperatures, temperatures, but it but is an it is average an average value. valu Thee. The finite finite element element (FE) (FE) thermal thermal model model simulates simulates the the thermal characterization of high-power modules by using RC network for thermal impedance thermal characterization of high-power modules by using RC network for thermal impedance [12]. It is [12]. It is effective to design heat dissipations in the presets, if the equivalent RC network is effective to design heat dissipations in the presets, if the equivalent RC network is completely tracked. completely tracked. Some on-chip temperature sensors have been proposed to measure exact Some on-chip temperature sensors have been proposed to measure exact temperature from solid-state temperature from solid-state devices. These sensors are inherently sensitive to temperature. devices. These sensors are inherently sensitive to temperature. Diodes have been used in their analog have been used in their analog counterparts because the yield voltage is a positive temperature counterparts because the yield voltage is a positive temperature coefficient due to reverse saturation coefficient due to reverse saturation current IS [13]. However, the diodes and analog to digital currentconverterIS [13 (ADC)]. However, are not thesuitable diodes for andthe high-resol analog toution digital power converter IC applications (ADC) are owing not suitableto their large for the high-resolutionlayout size, nonlinearity power IC characteristics, applications owing and large to their temperature large layout variations size, in nonlinearity measurements. characteristics, In [14], a anddiode large is temperatureused and an ADC variations is applied in measurements. to perform the Inreadout. [14], a Moreover, is used the system and an requires ADC is appliedthe area to ◦ performoverhead the and readout. has to Moreover, work at over the 100 system °C. In requires some cases, the areabandgap-based overhead and voltage has toreference work at circuits over 100 are C. Inused some as cases, their bandgap-based voltages are proportional voltage reference to absolute circuits temperature are used as their(PTAT) voltages [15]. areA differential proportional totemperature absolute temperature sensor is used (PTAT) to [determinate15]. A differential the efficiency temperature of sensor frequency is used (RF) to determinatelinear power the efficiencyamplifiers of Radio[16]. In frequencyaddition, a (RF) voltage-to-frequency linear power amplifiers converter [16 is]. used In addition, to increase a voltage-to-frequency the resolution and convertersimplifies is usedthe calibration to increase method. the resolution Apart from and simplifiesabove, even the in calibration most digital method. ICs, ring Apart oscillators from above, as eventemperature in most digital sensors ICs, arering used oscillators due to delay as temperaturelines, which depend sensors on are device used duetemperature to delay [17–23]. lines, which As dependtemperature on device sensors temperature need to be [17 embedded–23]. As temperature near the channel sensors of needpower to MOS, be embedded the ring oscillators near the channel and of powerbandgap-based MOS, the sensors ring oscillators are not suit andable bandgap-based for MOS bank sensors because are of not latch-up suitable rule for violation MOS bank and because the of latch-uplayout area rule in violation consideration. and the Temperature layout area inbalancing consideration. technologies Temperature are common balancing in the technologies multi-core are commonprocessor in thefor multi-corecontrolling the performances for controlling of each the core performances and further of eachreducing core andand furtherbalancing reducing the andtemperatures. balancing the In temperatures.[24], the strategy In of [24 the], the equali strategyzing temperature of the equalizing in integrated temperature circuits in has integrated been reported to the optimum choice of the stabilized chip temperature. However, the technique is seldom circuits has been reported to the optimum choice of the stabilized chip temperature. However, the used in power applications. technique is seldom used in power applications. In this paper, a method of thermal balance with on-chip temperature monitoring is proposed for In this paper, a method of thermal balance with on-chip temperature monitoring is proposed monolithic power ICs. The method identifies the hottest of MOSFET bank and reduces its power and for monolithic power ICs. The method identifies the hottest of MOSFET bank and reduces its thermal dissipation. The temperature-sensing device is an on-chip poly- strip. A temperature- power and thermal dissipation. The temperature-sensing device is an on-chip poly-silicon strip. A temperature-to-frequency converter (TFC) is developed to quantize an on-chip temperature as a digital code. For considering the chip area and balancing the control bits, the power MOSFET Sensors 2017, 17, 1397 3 of 14

Sensors 2017, 17, 1397 3 of 14 to-frequency converter (TFC) is developed to quantize an on-chip temperature as a digital code. For considering the chip area and balancing the control bits, the power MOSFET architecture can be dividedarchitecture into can eight be dividedbanks to into monitor eight banksthe channe to monitorl temperature the channel in temperaturethe bank level. in the An bank average level. temperatureAn average temperature monitor is proposed monitor is because proposed the because temper theature temperature will be saturated will be saturatedto a DC value to a DCafter value the chipafter working the chip workingfor a while. for aBased while. on Based the output on the of output the temperature of the temperature sensor, the sensor, hottest the hottestdevice can device be identified.can be identified. The equivalent The equivalent duty cycle duty can cycle thus can be thus adjusted. be adjusted. The rest of the paperpaper isis organizedorganized asas follows.follows. Section Section 22 developsdevelops anan on-chipon-chip temperaturetemperature monitoring technique. Section Section 33 introducesintroduces thethe pulse-width-modulationpulse-width-modulation (PWM)(PWM) methodologymethodology forfor temperature balancing.balancing. Section Section4 details 4 details the corresponding the corresponding circuit implementation circuit implementation and measurements and measurementsmade on a 0.25 madeµm 1P3M on a test0.25 chip. μm 1P3M Finally, test Section chip. 5Finally, draws Section conclusions. 5 draws conclusions.

2. Materials Materials and Methods Proposed On-Chip Temperature MonitoringMonitoring Figure2 2presents presents the the system system block block diagram diagram of the proposedof the proposed on-chip thermal on-chip balancing thermal architecture, balancing architecture,which is composed which is of composed two parts. of The two right parts. part The includes right part a includes temperature a temperature sensor with sensor eight with MOSFET eight MOSFETbanks in a banks parallel, in ana parallel, 8-1 Mux, an and 8-1 an Mux, RC oscillator and an RC (OSC). oscillator Each MOSFET (OSC). Each bank MOSFET has an individual bank has gate an individualcontrol signal gate and control a temperature signal and sensing a temperature poly resistor. sensing The poly 8-1 resistor. Mux is usedThe 8-1 to selectMux is one used resistor to select for onesensing resistor the localfor sensing temperatures the local and temperatures is connected and to the is OSC.connected The left to partthe OSC. includes The theleft thermal part includes balancing the thermalcontroller, balancing which is controller, used to perform which thermalis used to balancing, perform whichthermal is balancing, verified by which a field is programmable verified by a field gate programmablearray (FPGA) and gate the array principle (FPGA) is introducedand the principle in Section is introduced3. in Section 3.

Figure 2. ProposedProposed thermal balancing architecture.

The sensing device in our temperature sensor is a poly-silicon strip, which can be placed next to The sensing device in our temperature sensor is a poly-silicon strip, which can be placed next to the drain/source of the MOSFET bank under consideration. Figure 3 presents the eight parallel banks. the drain/source of the MOSFET bank under consideration. Figure3 presents the eight parallel banks. A poly-silicon strip (thick gray line) is embedded in the middle of each MOSFET bank. Each bank has A poly-silicon strip (thick gray line) is embedded in the middle of each MOSFET bank. Each bank has a total width of 5000 μm (50 μm × 50 fingers × 2 blocks), and the layout of poly and oxide diffusion a total width of 5000 µm (50 µm × 50 fingers × 2 blocks), and the layout of poly and oxide diffusion (OD) layers as shown in Figure 4. The embedded sensors use to measure each of the MOSFET banks (OD) layers as shown in Figure4. The embedded sensors use to measure each of the MOSFET banks and notify the temperature variation within neighboring cells. and notify the temperature variation within neighboring cells. The change in resistance of the integrated resistor with temperature is

 2 R(T) = RO × 1 + TC1 × ∆T + TC2·∆T (1) where RO is the resistance at room temperature, TC1 and TC2 are the first and second-order temperature coefficients, and ∆T is the change in temperature. TSMC design guideline indicates that ∆R/RO equal to −9% in a poly resistor for any change in temperature (∆T) varies from 25 to 150 ◦C, whereas TC2 has a small effect on resistance because TC1 >> TC2 (larger than two orders). The simulated temperature coefficient is ∆R/R −9% TC1 = 0 = = −0.072%/◦C. (2) S ∆T 150 − 25

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Sensors 2017, 17, 1397 4 of 14

FigureFigure 3.3. EquivalentEquivalent circuit circuit of eight of MOSFET eight MOSFET banks with banks poly-silicon with strips poly-silicon as temperature strips sensing as temperature devices.

sensingFigure devices.3. Equivalent circuit of eight MOSFET banks with poly-silicon strips as temperature sensing devices.

Figure 4. Layout of each MOSFET bank with a temperature sensor.

Figure 4. Layout of each MOSFET bank with a temperature sensor. The change Figurein resistance 4. Layout of the of integrated each MOSFET resistor bank with with temperature a temperature is sensor. The change in resistance of the integrated= × 1+1×∆+2∙∆ resistor with temperature is (1)

Figurewhere 5R showsO is the the resistance detail circuitry at room oftemperature, the proposed TC1 TFC, and whichTC2 are is athe stable first multi-vibratorand second-order where = × 1+1×∆+2∙∆ (1) RT istemperature a poly resistor coefficients, of the and poly-silicon ΔT is the change temperature in temperature. sensor andTSMC a design guideline (C) is indicates added tothat adjust where RO is the resistance at room temperature, TC1 and TC2 are the first and second-order the frequencyΔR/RO equal of to the −9% OSC. in a The poly OSC resistor includes for any two change rail-to-rail in temperature comparators (ΔT) varies and anfrom set-reset 25 to 150 (SR) °C, latch. temperature coefficients, and ΔT is the change in temperature. TSMC design guideline indicates that The oscillationwhereas TC2 period has a is small as follows. effect on resistance because TC1 >> TC2 (larger than two orders). The simulatedΔR/RO equal temperature to −9% in coefficienta poly resistor is for any change in temperature (ΔT) varies from 25 to 150 °C, whereas TC2 has a small effect on resistance because TC1 >> TC2 (larger! than two orders). The ∆/ % V 1 = = Vdd=− −0.072%/Vlow . high (2) simulated temperatureτ =coefficientτ + τ =is R ×∆C × ln + ln . (3) 1 2 T V − V V ∆/ % dd high low Figure 5 shows the detail circuitry1 = of the =proposed= TFC, −0.072%/ which is. a stable multi-vibrator where ∆ (2) RT is a poly resistorV of the poly-siliconV temperatureV sensor and a capacitor (C) is added× R to× adjustC thef For example,Figure 5 showsdd = the 2.5 detail V, low circuitry= 0.15 V,of andthe proposedhigh = 2.35 TFC, V which and set, is a so stableτ = 5.5 multi-vibratorT and where= 1/τ. The designfrequency parameters of the OSC. are The set OSC as follows. includes The two poly-silicon rail-to-rail comparators strip is 2 µ andm wide an set-reset and 480 (SR)µm latch. long The with an oscillationRT is a poly period resistor is asof thefollows. poly-silicon temperature sensor and a capacitor (C) is added to adjust the equivalentfrequency resistance of the OSC. of 41 The kΩ OSCand includesC is 8 pF. two According rail-to-rail to comparators Equation (3), and the an set-reset oscillation (SR) period latch. The is 1.8 µs, and theoscillation oscillation period frequency is as follows. is= 554 kHz.+ = ×× + . (3) Based on Equation (1), the frequency or the period can be obtained to determine RT if C is For example, Vdd = 2.5 V,= Vlow = 0.15+ V,= and ×× Vhigh = 2.35 V and set,+ so τ = 5.5. × RT × C and f = 1/τ. The(3) known. The measuring time determines the accuracy of temperatures, which can be derived as design parameters are set as follows. The poly-silicon strip is 2 μm wide and 480 μm long with an follows. Suppose that τ and τmax are the minimal and maximal periods, according to Equation (1), equivalentFor example, resistance Vddmin =of 2.5 41 V, k ΩVlow and = 0.15 C isV, 8and pF. V Accordinghigh = 2.35 V toand Equation set, so τ (3),= 5.5 the × R oscillationT × C and f =period 1/τ. The is at maximal and minimal operating temperatures, T and T . N is the resolution and the number of 1.8design μs, andparameters the oscillation are set frequency as follows. is The554 kHz.poly-silicon max strip minis 2 μm wide and 480 μm long with an temperatureequivalent levels resistance between of 41T kΩand andT C is. 8 The pF. measuringAccording to time Equationτ must (3), the satisfy oscillation period is Based on Equation (1), maxthe frequencymin or the period can be obtainedmeas to determine RT if C is known. The1.8 μ measurings, and the oscillation time determines frequency the is accuracy 554 kHz. of temperatures, which can be derived as follows. τmeas τmeas Based on Equation (1), the frequency or the period can be obtained to determine RT if C is known. Suppose that τmin and τmax are the minimal −and maximal≥ N .periods, according to Equation (1), at (4) The measuring time determines the accuracyτmin ofτ maxtemperatures, which can be derived as follows.

Suppose that τmin and τmax are the minimal and maximal periods, according to Equation (1), at τmax·τmin τmeas ≥ × N. (5) τmax − τmin Sensors 2017, 17, 1397 5 of 14

maximal and minimal operating temperatures, Tmax and Tmin. N is the resolution and the number of temperature levels between Tmax and Tmin. The measuring time τmeas must satisfy Sensors 2017, 17, 1397 5 of 14 − ≥. (4)

∙ If τmeas = (1 ± x)·τo, then τo is the period in≥ which the average×. of oscillation period is determined,(5) and x is the maximal deviation from the average, If τmeas = (1 ± x) ·τo, then τo is the period in which the average of oscillation period is determined, and x is the maximal deviation from the average, τo τmeas ≥ × N. (6) 2x ≥ ×. (6) For example, if τo is 1 µs and x is 5%, then τmin = 0.95 µs and τmax = 1.05 µs. For a given resolution, For example, if τo is 1 μs and x is 5%, then τmin = 0.95 μs and τmax = 1.05 μs. For a given resolution, say N is equal to 1000, and for a fixed value of τ = 10 ms, the maximal count of τ /τ is 10,526, say N is equal to 1000, and for a fixed value ofmeas τmeas = 10 ms, the maximal count of τmeasmeas/τmin ismin 10,526, and theand minimal the minimal count count of τ measof τmeas/τ/maxτmax isis 9524.9524. In In this this case, case, a a14 14 bit bit counter counter is required is required to count to count maximal maximal and minimaland minimal value value of measured of measured frequency. frequency.

R Icharge T0-7 OSC - Vhigh + S Q _ C R Q - Vlow Idischarge +

FigureFigure 5. 5.Proposed Proposed TFC circuit.

Unfortunately, C, RT, and x are difficult to predict precisely. Process variation is another critical Unfortunately, C, R , and x are difficult to predict precisely. Process variation is another critical challenge in temperatureT sensing. As shown in Figure 5, all of the temperature sensing challenge in temperature sensing. As shown in Figure5, all of the temperature sensing resistors ( R ) (RT0–7) share the same capacitor, comparators, SR latch, and inverter in the TFC circuit. Ideally, the T0–7 shareoscillation the same capacitor,frequency comparators,is determined SR only latch, by andRT. Suppose inverter inthat the MOSFET TFC circuit. banks Ideally, Mi and the M oscillationj have frequencytemperature is determined Ti and Tj, only respectively. by RT. SupposeWith a negative that MOSFET temperature banks coefficient,Mi and onceMj have the oscillation temperature Ti andfrequencyTj, respectively. fi is higher Withthan fj, a then negative Ti is higher temperature than Tj. Since coefficient, the oscillation once frequency the oscillation depends frequency on the fi is highersensing than resistorfj, then RT Tandi is capacitor higher than C, a targetTj. Since of the the frequency oscillation range frequency can be designed depends with on the the size sensing of the poly-silicon strip and the capacitor. The sensing resistor is designed related large as compared to resistor RT and capacitor C, a target of the frequency range can be designed with the size of the poly-siliconthe parasitic strip resistance and the capacitor. of interconnections The sensing and resistorTFC switches. is designed As a result, related we assumed large as comparedthat RT >> R toP. the In addition, the temperature sensitivity of the sensing resistor is larger than the parasitic resistance parasitic resistance of interconnections and TFC switches. As a result, we assumed that RT >> RP. of the capacitor. The frequency change is mainly related to the sensing resistor. Thus, the variation of In addition, the temperature sensitivity of the sensing resistor is larger than the parasitic resistance of parasitic resistances and capacitor can be ignored in the TFC circuit. However, process variation and the capacitor.circuit mismatch The frequency affect the changeresults from is mainly metal routin relatedg paths, to the switching sensing devices, resistor. and Thus, sensing the resistors, variation of parasiticeven resistances at a fixed and temperature. capacitor canConsequently, be ignored a in mechanism the TFC circuit. to calibrate However, process process variation variation and and circuitmismatches mismatch is affect developed. the results from metal routing paths, switching devices, and sensing resistors, even at a fixed temperature. Consequently, a mechanism to calibrate process variation and mismatches is developed.3. Calibrations and Thermal Balancing Methodology Since the poly resistor determines the frequency of the TFC, as a function of temperature, the 3. Calibrationspower MOS and operation Thermal with Balancing self-heating Methodology can balances the channel temperature in each bank by Sincepulse-width-modulation the poly resistor determines(PWM) methodology. the frequency Fi is the of thetotal TFC, number as a of function frequencies of temperature, recorded by the powerfrequency MOS operation count module with (FREQCount) self-heating and can calibrate balances module the channel (CALIB) temperatureis a calibration in module each bankthat by overcomes accuracy problems related to process variation and circuit mismatch. MAXSearch finds pulse-width-modulation (PWM) methodology. F is the total number of frequencies recorded by the MOSFET bank with the highest temperature, iwhereas PWMMod reduces the number of PWM frequencypulse countof the hottest module bank (FREQCount) to lower down and its temperat calibrateure. module Figure 6 (CALIB)shows the is flowchart a calibration of the proposed module that overcomes accuracy problems related to process variation and circuit mismatch. MAXSearch finds the MOSFET bank with the highest temperature, whereas PWMMod reduces the number of PWM pulse of the hottest bank to lower down its temperature. Figure6 shows the flowchart of the proposed thermal balancing method. The above loop will keep iterating whenever power and PWM signal are provided. Sensors 2017, 17, 1397 6 of 14 Sensors 2017, 17, 1397 6 of 14

Sensorsthermal2017 balancing, 17, 1397 method. The above loop will keep iterating whenever power and PWM signal6 of are 14 thermalprovided. balancing method. The above loop will keep iterating whenever power and PWM signal are provided.

Figure 6. Flowchart of proposed thermal balancing mechanism. Figure 6. Flowchart of proposed thermal balancing mechanism. The circuitcircuit mismatch mismatch is suppressedis suppressed by theby TFCthe TFC circuit circuit with anwith oscillator an oscillator and eight and sensing eight resistors,sensing The circuit mismatch is suppressed by the TFC circuit with an oscillator and eight sensing andresistors, a subtractor and a subtractor of the calibration of the methodcalibration is expected method to iscancel expected the processto cancel mismatch. the process In the mismatch. calibration In resistors,the calibration and a module, subtractor ΔF ofi is the the calibration number of method changed is frequencies, expected to recordedcancel the and process compared mismatch. with FIni, module, ∆Fi is the number of changed frequencies, recorded and compared with Fi, whereas ∆Fi is thewhereas calibration ΔFi is definedmodule, asΔ FΔi Fisi =the Fi number− CFi. CF ofi is changed the number frequencies, of frequenciesth recorded of the and ith compared MOSFET withbank Fati, defined as ∆Fi = Fi − CFi. CFi is the number of frequencies of the i MOSFET bank at the calibration whereas ΔFi is defined as ΔFi = Fi − CFi. CFi is the number of frequencies of the ith MOSFET bank at timethe calibration when power time devices when arepower not devices functioning. are not Figure func7tioning. displays Figure the block 7 displays diagram the ofblock the calibrationdiagram of the calibration moduletime when in Figure power 2. devices It consists are ofnot two func registertioning. files, Figure CF0–7 7 and displays F0–7. CF the0–7 blockstore thediagram number of module in Figure2. It consists of two register files, CF0–7 and F0–7. CF0–7 store the number of calibration the calibration module in Figure 2. It consists of two register files, CF0–7 and F0–7. CF0–7 store the number frequencies.of calibration At frequencies. the beginning At ofthe CALIB beginning = 1, theof CALIB power MOS= 1, the is turnedpower off,MOS and is theturned sensing off, resistorsand the ofsensing calibration resistors frequencies. are sequentially At the beginningselected. Theof CALIB frequency = 1, theof thepower TFC MOS is recorded is turned in off,CF iand. In the are sequentially selected. The frequency of the TFC is recorded in CFi. In the operation mode and sensingoperation resistors mode and are measuringsequentially (MEAS) selected. mode The of frequency CALIB = 0,of thethe frequencies TFC is recorded are counted, in CF i.and In the measuring (MEAS) mode of CALIB = 0, the frequencies are counted, and the number is recorded operationnumber is moderecorded and as measuring Fi. Finally, (MEAS)CFi is subtracted mode of from CALIB Fi, yielding= 0, the frequenciesΔFi for comparison are counted, of the channeland the as Fi. Finally, CFi is subtracted from Fi, yielding ∆Fi for comparison of the channel temperatures. numbertemperatures. is recorded For example, as Fi. Finally, the total CFi isnumber subtracted of freque fromncies Fi, yielding is stored ΔF ini for a comparisoncounting time of ofthe 1 channelms, the For example, the total number of frequencies is stored in a counting time of 1 ms, the oscillator through temperatures.oscillator through For example,a sensing the resistor, total number RT2◦, working of freque at Tncies ◦= 25 is °C stored and Tin = a 100 counting °C (after time heating). of 1 ms, Thethe a sensing resistor, RT2, working at T = 25 C and T = 100 C (after heating). The results are subtracted, oscillatorresults are through subtracted, a sensing F0,100 °C resistor,– CF0,25 °C ,R yieldingT2, working the temperatureat T = 25 °C leveland T in = transistor 100 °C (after bank heating). 2 (TX2). The F0,100 ◦C – CF0,25 ◦C, yielding the temperature level in transistor bank 2 (TX2). results are subtracted, F0,100 °C – CF0,25 °C, yielding the temperature level in transistor bank 2 (TX2).

Figure 7. Block diagram of the calibration module. Figure 7. Block diagram of the calibration module.

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TheThe hottesthottest bankbank isis defineddefined asas thethe oneone withwith thethe largestlargest ∆ΔFFi.i. AfterAfter thethe hottesthottest devicedevice hashas beenbeen identified,identified, aa PWMPWM modificationmodification schemescheme forfor thatthat bankbank isis employed.employed. AA PWMPWM signalsignal isis aa repetitive pulsepulse streamstream thatthat periodicallyperiodically turnsturns onon devices.devices. To reducereduce thethe temperaturetemperature ofof thethe hottesthottest bank,bank, oneone pulsepulse isis suppressedsuppressed inin everyeveryK pulse, pulse, as as shown shown in Figurein Figure8. In 8. Figure In Figure8, TX2 8, isTX2 assumed is assumed to be theto be hottest the hottest bank. Thebank. gate The control gate control for TX2 for has TX2 an effective has an dutyeffective cycle duty of 3/4 cycle× D ofif 3/4 one × out D ofif one four out pulses of four is suppressed. pulses is Therefore,suppressed. the Therefore, power dissipation the power of dissipation TX2 is 3/4, of reducing TX2 is 3/4, the reducing temperature. the temperature.

Figure 8. Gate control scheme of PWM modificationmodification toto eacheach MOSFETMOSFET banksbanks forfor thermalthermal balancing.balancing.

However, decreasing the effective duty cycle for TX2 will reduce the overall power output. In a However, decreasing the effective duty cycle for TX2 will reduce the overall power output. In a closed loop system, the feedback mechanism is activated to increase the duty cycle to maintain the closed loop system, the feedback mechanism is activated to increase the duty cycle to maintain the overall power output level. Suppose that N numbers of MOSFET banks are in parallel and the original overall power output level. Suppose that N numbers of MOSFET banks are in parallel and the original and the final duty cycle are D0 and D1, respectively. The overall duty cycles of all N devices, or total and the final duty cycle are D and D , respectively. The overall duty cycles of all N devices, or total output current, must be equal0 to each1 other before and after PWM modification. Therefore, output current, must be equal to each other before and after PWM modification. Therefore, × = × + −1 ×. (7) (K − 1) N × D0 = × D1 + (N − 1) × D1. (7) K = × . / (8) N D = × D . (8) The left- and right-hand sides of Equation1 (N (7)− ar1/eK the) accumulated0 duty of all devices. According to Equation (8), the adjusted duty cycle is greater than the original. Consider for example, K = 4, The left- and right-hand sides of Equation (7) are the accumulated duty of all devices. According N = 8, and D0 = 0.25; the adjusted duty cycle D1 = 0.258, increasing by 0.8% after PWM modification. to Equation (8), the adjusted duty cycle is greater than the original. Consider for example, K = 4, Accordingly, TX2 has an effective duty cycle of 0.194 (3/4 × 0.258), which is 78% of the original 0.25. N = 8, and D = 0.25; the adjusted duty cycle D = 0.258, increasing by 0.8% after PWM modification. The remaining0 seven banks share the suppressed1 pulse of TX2, with an increase in the adjusted duty Accordingly, TX2 has an effective duty cycle of 0.194 (3/4 × 0.258), which is 78% of the original 0.25. cycle of 0.8%. The remaining seven banks share the suppressed pulse of TX2, with an increase in the adjusted duty cycle4. Experimental of 0.8%. Results and Discussion 4. ExperimentalTo demonstrate Results the andfeasibility Discussion of the proposed methodology, a test power chip and a test board are used. An on-chip temperature sensor is implemented using TSMC 0.25 μm BCD processes. To demonstrate the feasibility of the proposed methodology, a test power chip and a test board are Figure 9 shows the die photograph of the proposed test chip. The test chip includes eight LDMOS used. An on-chip temperature sensor is implemented using TSMC 0.25 µm BCD processes. Figure9 with individual gate controls and a common source and drain, an 8-1MUX, and an OSC. shows the die photograph of the proposed test chip. The test chip includes eight LDMOS with individual gate controls and a common source and drain, an 8-1MUX, and an OSC. The experiment is composed of the following five steps. First, cad tools, R3D (Silicon Frontline, San Jose, CA, USA) and ANSYS Multiphysics (ANSYS, Canonsburg, PA, USA) are used to simulate the thermal effects of power MOS transistors and the distribution of temperature in MOSFET banks. Second, the post-layout simulation is performed to verify the TFC conversion mechanism. Third, the chip is put into a lab to validate and calibrate the temperature coefficients according to the RC OSC. Fourth, the CALIB and MEAS modes are conducted to count the oscillation frequencies with 0–1.5 W power dissipation. Finally, the PWMMod reduces the effective duty cycle for the hottest device.

Figure 9. Die photograph.

Sensors 2017, 17, 1397 7 of 14

The hottest bank is defined as the one with the largest ΔFi. After the hottest device has been identified, a PWM modification scheme for that bank is employed. A PWM signal is a repetitive pulse stream that periodically turns on devices. To reduce the temperature of the hottest bank, one pulse is suppressed in every pulse, as shown in Figure 8. In Figure 8, TX2 is assumed to be the hottest bank. The gate control for TX2 has an effective duty cycle of 3/4 × D if one out of four pulses is suppressed. Therefore, the power dissipation of TX2 is 3/4, reducing the temperature.

Figure 8. Gate control scheme of PWM modification to each MOSFET banks for thermal balancing.

However, decreasing the effective duty cycle for TX2 will reduce the overall power output. In a closed loop system, the feedback mechanism is activated to increase the duty cycle to maintain the overall power output level. Suppose that N numbers of MOSFET banks are in parallel and the original and the final duty cycle are D0 and D1, respectively. The overall duty cycles of all N devices, or total output current, must be equal to each other before and after PWM modification. Therefore,

× = × + −1 × . (7)

= × . / (8) The left- and right-hand sides of Equation (7) are the accumulated duty of all devices. According to Equation (8), the adjusted duty cycle is greater than the original. Consider for example, K = 4, N = 8, and D0 = 0.25; the adjusted duty cycle D1 = 0.258, increasing by 0.8% after PWM modification. Accordingly, TX2 has an effective duty cycle of 0.194 (3/4 × 0.258), which is 78% of the original 0.25. The remaining seven banks share the suppressed pulse of TX2, with an increase in the adjusted duty cycle of 0.8%.

4. Experimental Results and Discussion Sensors 2017, 17, 1397 8 of 14 To demonstrate the feasibility of the proposed methodology, a test power chip and a test board are used. An on-chip temperature sensor is implemented using TSMC 0.25 μm BCD processes. FigureIt confirms 9 shows that the die proposed photograph algorithm of the reduces proposed the peaktest chip. temperature The test andchip anyincludes kind ofeight variation LDMOS in withtemperature individual for gate eight controls MOSFET and banks. a common source and drain, an 8-1MUX, and an OSC.

Sensors 2017, 17, 1397 8 of 14

The experiment is composed of the following five steps. First, cad tools, R3D (Silicon Frontline, San Jose, California) and ANSYS Multiphysics (ANSYS, Canonsburg, Pennsylvania) are used to simulate the thermal effects of power MOS transistors and the distribution of temperature in MOSFET banks. Second, the post-layout simulation is performed to verify the TFC conversion mechanism. Third, the chip is put into a lab oven to validate and calibrate the temperature coefficients according to the RC OSC. Fourth, the CALIB and MEAS modes are conducted to count the oscillation frequencies with 0–1.5 W power dissipation. Finally, the PWMMod reduces the effective duty cycle for the hottest device. It confirms that the proposed algorithm reduces the peak temperature and any Figure 9. Die photograph. kind of variation in temperature for eight MOSFET banks.

4.1. Power4.1. Power and Thermal and Thermal Simulation Simulation BasedBased on the on power the power MOS MOSlayout layout in Figure in Figure 10a, Figure 10a, Figure 10(b–d) 10 (b–d)show showthe power the power MOS MOSsimulated simulated IR drop,IR drop,power power dissipation, dissipation, and temperature and temperature distribution, distribution, obtained obtained using usingR3D, R3D,based based on a power on a power dissipation of 1.5 W (I = 2.14 A, V = 0.7 V at 25 ◦C). They show power density in W/µm (Figure 10b), dissipation of 1.5 W (ID = 2.14D A, VDS = 0.7DS V at 25 °C). They show power density in W/μm (Figure 10b), IR dropsIR drops of drain of drain voltage voltage distribu distributiontion (Figure (Figure 10c), and10c), source and source voltage voltage distribution distribution in the in top the metal top metal layer layer(Figure (Figure 10d), 10andd), the and overall the overall temperature temperature distribution distribution in silicon in silicon (without (without metal metal consideration) consideration) is is alsoalso shown. shown. These These figures figures indicate indicate that that the the maximal maximal power dissipationdissipation mismatchmismatch isis 6.7%. 6.7%. The The power powerdissipation dissipation is 1.5is 1.5 W uniformlyW uniformly to eight to eight parallel parallel MOSFET MOSFET banks banks without without metal wiring.metal wiring. The distribution The distributionof power of power dissipation, dissipation, obtained obtained by R3D, by isR3D, fed is into fed ANSYS into ANSYS to conduct to conduct a thermal a thermal analysis. analysis. Figure 11 Figureshows 11 shows the results the results of ANSYS of ANSYS simulation simulation related re tolated the to distribution the distribution of power of power dissipation dissipation results. The ◦ results.maximal The maximal temperature temperature difference difference between betwee the banksn the is banks 3.4 C, is where 3.4 °C, TX1 where is the TX1 hottest is the bank hottest and TX4 bank isand the TX4 coolest is the bank. coolest Figure bank. 10 Figure shows 10 the show hots spot the withhot spot common-centroid with common-centroid distribution, distribution, which can be whichachieved can be achieved by the symmetrical by the symmetrical layout and layout the powerand the devices power placementsdevices placements theoretically. theoretically. However, the However,temperature the temperature distribution distribution is formed is by formed many factorsby many such factors as power such dissipations, as power dissipations, heat source heat locations, sourceand locations, thermal and sink thermal device sink areas device [24]. In areas practical [24]. In cases, practical the power cases, MOSFETthe power is MOSFET operated is under operated non-ideal underconditions, non-ideal suchconditions, as turned-on such as uniformity, turned-on bondinguniformity, bonding consistency, wire andconsistency, chip and and package chip symmetry.and packageTherefore, symmetry. the hotTherefore, spot is transferredthe hot spot to is the transferr left sideed ofto thethe chipleft side in Figure of the 11 chip due in to Figure the location 11 due of the to thepower location MOS. of the power MOS.

Power [W/um] 3.46 × 10-5

6.7% 3.43 × 10-5 (PMAX) 3.40 × 10-5

3.37 × 10-5

3.34 × 10-5 3.4% 3.31 × 10-5

3.28 × 10-5

3.25 × 10-5

3.22 × 10-5

3.19 × 10-5

(a) (b)

Figure 10. Cont.

Sensors 2017, 17, 1397 9 of 14 Sensors 2017, 17, 1397 9 of 14 Sensors 2017, 17, 1397 9 of 14

Potential [V] 0.7V Potential0.7 [V] 0.7V 0.7

0.688 0.688

0.676 0.676

0.664 0.664

0.652 0.652

-0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.64 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.64 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 (c) (d) (c) (d) Figure 10. R3D and ANSYS simulations of: (a) the power MOS layout; (b) the power density at Figure 10.10. R3DR3D and and ANSYS ANSYS simulations simulations of: (of:a) the(a) powerthe power MOS MOS layout; layout; (b) the ( powerb) the densitypower atdensity channel; at channel; (c) the drain side potential; (d) the source side potential at the top metal layer. (channel;c) the drain (c) the side drain potential; side potential; (d) the source (d) the side source potential side potential at the top at metal the top layer. metal layer.

Figure 11. ANSYS simulations of banks temperature results. Figure 11. ANSYS simulations of banks temperature results. Figure 11. ANSYS simulations of banks temperature results. Based on the 3D simulation results, we can predict the expected temperature imbalances to Based on the 3D simulation results, we can predict the expected temperature imbalances to determineBased the on sensitivity the 3D simulationand resolution results, of the we implemented can predict thesensors expected as shown temperature in Figure imbalances 11. The determine the sensitivity and resolution of the implemented sensors as shown in Figure 11. The simulationto determine shows the the sensitivity temperature and distribution resolution ofbase thed on implemented the boundary sensors conditions as shown of specific in Figure power 11 . simulation shows the temperature distribution based on the boundary conditions of specific power dissipations,The simulation volumes, shows and the material temperature properties. distribution Moreover, based conditions on the boundary of the power conditions dissipations of specific of dissipations, volumes, and material properties. Moreover, conditions of the power dissipations of banks,power the dissipations, places of heat volumes, sources, and and material the sizes properties. of thermal Moreover, sink components conditions can of thebe changed power dissipations to make banks, the places of heat sources, and the sizes of thermal sink components can be changed to make theof analyses banks, the more places accurate, of heat whereas sources, theand routing the sizesmetal, of bonding thermal wire, sink packaging components material, can be and changed testing to the analyses more accurate, whereas the routing metal, bonding wire, packaging material, and testing Printedmake thecircuit analyses board more (PCB) accurate, are the whereas part of the the routing thermal metal, sinkbonding devices. wire, However, packaging these material, boundary and (PCB) are the part of the thermal sink devices. However, these boundary conditiontesting Printed factors circuitwould board result (PCB) in the are difficulties the part ofof the the thermal analyses. sink Moreover devices., However,these factors these would boundary not condition factors would result in the difficulties of the analyses. Moreover, these factors would not addcondition new data factors regarding would to resultthe expected in the difficulties temperature of theimbalances. analyses. Moreover, these factors would not add new data regarding to the expected temperature imbalances. add new data regarding to the expected temperature imbalances. 4.2. Temperature Coefficient Extraction 4.2. Temperature Coefficient Extraction 4.2. Temperature Coefficient Extraction To verify the RC OSC and the temperature coefficient of the sensing poly-resistors (RT), the test To verify the RC OSC and the temperature coefficient of the sensing poly-resistors (RT), the test chip isTo placed verify in the a RCtemperature-controlled OSC and the temperature lab oven. coefficient The oscillation of the sensing frequency poly-resistors is 508.2 (kHzRT), thewhen test chip is placed in a temperature-controlled lab oven. The oscillation frequency is 508.2 kHz when Vhighchip = 2.35 is placed V and in V alow temperature-controlled = 0.15 V. Table 1 shows lab the oven. total The number oscillation of frequencies frequency Fi is and 508.2 frequencies kHz when Vhigh = 2.35 V and Vlow = 0.15 V. Table 1 shows the total number of frequencies Fi and frequencies increasedVhigh = 2.35 ΔFi,V measured and Vlow by= 0.15using V. the Table FPGA1 shows board. the The total first number row presents of frequencies the set temperatures.Fi and frequencies The increased ΔFi, measured by using the FPGA board. The first row presents the set temperatures. The secondincreased row ∆presentsFi, measured the measurements by using the of FPGA frequencies board. obtained The first rowby FREQCount presents the and set CALIB temperatures. from second row presents the measurements of frequencies obtained by FREQCount and CALIB from FPGA.The second The third row row presents is the the calibration measurements result of(ΔF frequenciesT = FT − CFT). obtained The temperature by FREQCount coefficient and CALIBis derived from FPGA. The third row is the calibration result (ΔFT = FT − CFT). The temperature coefficient is derived asFPGA. follows. The third row is the calibration result (∆FT = FT − CFT). The temperature coefficient is derived as follows. as follows. F100 = −F25= 45995− 43524= 33/. ◦ (9) TC = = ∆ = = == 33/33/. C. (9) ∆T ∆ 100− 25

SensorsSensors2017 2017, 17, 139717, 1397 10 of10 14of 14

Table 1. Calibration the total number of frequency versus temperature. Table 1. Calibration the total number of frequency versus temperature. 25 °C 50 °C 75 °C 100 °C ◦ ◦ ◦ ◦ Measured F 43,52425 C 5044,362C 75 C45,165 100 C 45,995 Measured ΔMeasuredF F 0 43,524 44,362 838 45,165 1641 45,995 2471 Measured ∆F 0 838 1641 2471 From Equations (2) to (3), it can be inferred that the frequency depends on the resistance as follows:From Equations(Fi − CFi)/ (2)CFito ∝ (3),(RTi it − can ROi be)/R inferredOi. The thatmeasured the frequency temperature depends coefficient on the resistance TC1M is as−0.0716%/°C follows: ◦ (Fi and− CF thei)/ simulatedCFi ∝ (RTi −temperatureROi)/ROi. Thecoefficient measured TC1 temperatureS is −0.072%/°C. coefficient Since theTC1 measurementM is −0.0716%/ timeC is and 83.34 ◦ thems, simulated the desired temperature TC is 396 coefficient Hz/°C (TC1TC/83.34S is − ms).0.072%/ The C.derived Since theTC measurementis a linear approximation time is 83.34 ms,of an theexponential desired TC isRC 396 OSC. Hz/ Figure◦C(TC /83.3412 shows ms). a Theplot derivedof temperaturesTC is a linear in the approximation horizontal axis of anand exponential frequency in RCthe OSC. vertical Figure axis, 12 showsthe frequency a plot of of temperatures the eight temper in theature horizontal sensors axisas a andfunction frequency of temperature in the vertical before axis,and the after frequency the calibration. of the eight In Figu temperaturere 12b, we sensors can see as the a functiondispersion of between temperature sensors before and and linearities, after thefitting calibration. the baseline In Figure of Table 12b, 1. we can see the dispersion between sensors and linearities, fitting the baseline of Table1.

(b) (a)

Figure 12. Frequency of the eight temperature sensors plotted as a function of temperature: (a) Before Figure 12. Frequency of the eight temperature sensors plotted as a function of temperature: (a) Before calibration;calibration; (b) ( afterb) after calibration. calibration.

Based on these results, the frequencies offsets of the resistance mismatches can be obtained in FigureBased 12a. on theseThe temperature results, the frequenciescoefficient offsetsTC can of be the estimated resistance according mismatches to canthe becalibration obtained in inpre-measurement Figure 12a. The temperatureprocess. Therefore, coefficient the absolute TC can temperatures be estimated can according be obtained to the by calibration the calibration. in pre-measurementThe probability errors process. of the Therefore, measurements the absolute are about temperatures 1% of the resistance can be obtained mismatch by thefor relative calibration. errors Theand probability ±30% of errorsthe resistor of the measurementstolerance for absolute are about errors. 1% of Despite the resistance the research mismatch on forthe relative maximal ± errorstemperature and 30% address of the of resistor the MOSFET tolerance bank, for absolute the abso errors.lute temperature Despite the information research on is the not maximal necessary. temperatureThe calibration address ΔF compensates of the MOSFET the bank,frequency the absolute error by temperaturethe subtraction information method. is not necessary. The calibration ∆F compensates the frequency error by the subtraction method. 4.3. Experiments and Discussion 4.3. Experiments and Discussion Figure 13 shows the experiment that involved a channel thermometer. In this experiment, Figure 13 shows the experiment that involved a channel thermometer. In this experiment, measurements were made by forcing the continuously dissipated power into the power MOS using measurements were made by forcing the continuously dissipated power into the power MOS using an an Agilent N6705B source meter. The FPGA board recorded the total number of frequencies. Agilent N6705B source meter. The FPGA board recorded the total number of frequencies. Table2 lists Table 2 lists the measured temperatures based on TC = 33/°C; the counts after calibration are shown the measured temperatures based on TC = 33/◦C; the counts after calibration are shown in parentheses. in parentheses. For comparison with each bank, the maximal and minimal temperatures are 102.7 °C For comparison with each bank, the maximal and minimal temperatures are 102.7 ◦C and 93.1 ◦C. and 93.1 °C. ANSYS simulations yield corresponding values of 98.55 °C and 95.34 °C. The maximal ANSYS simulations yield corresponding values of 98.55 ◦C and 95.34 ◦C. The maximal temperature temperature difference is 9.6 °C (TX7 vs. TX4). The proposed method is highly accurate because it difference is 9.6 ◦C (TX7 vs. TX4). The proposed method is highly accurate because it involved involved calibration using a lab oven. calibration using a lab oven.

Sensors 2017, 17, 1397 11 of 14 Sensors 2017, 17, 1397 11 of 14 Sensors 2017, 17, 1397 11 of 14

Figure 13. Photograph of measurement apparatus. Figure 13. Photograph of measurement apparatus. Table 2. CalibrationFigure 13. the Photograph total number of measurement of frequency versusapparatus. temperature.

Bank Table 0 W 2. Calibration 0.1 the W total number 0.5 of frequencyW versusversus1 temperature.temperature. W 1.5 W TX0 26.0°C (0) 33.2°C (237) 56.3 °C (1001) 78.1 °C (1719) 99.5 °C (2424) BankBank 0 0W W 0.1 0.1 W W 0.5 0.5 W W 1 W 1 W 1.5 W 1.5 W TX1 26.0°C (0) 34.5°C (282) 53.7°C (915) 80.9 °C (1812) 96.9 °C (2338) TX0TX0 26.0 26.0°C◦C (0) (0) 33.2 33.2°C◦C (237) (237) 56.3 56.3◦C °C (1001) (1001) 78.1 78.1◦C (1719)°C (1719) 99.5 ◦ 99.5C (2424) °C (2424) TX2 26.0°C◦ (0) 32.1°C◦ (202) 55.4°C◦ (970) 77.8◦ °C (1711) 95.2◦ °C (2284) TX1TX1 26.0 26.0°CC (0) (0) 34.5 34.5°CC (282) (282) 53.7 53.7°CC (915) (915) 80.9 80.9C (1812)°C (1812) 96.9 96.9C (2338) °C (2338) ◦ ◦ ◦ ◦ ◦ TX3TX2 26.0 26.0°CC (0)(0) 32.1 29.2°CC (202) (106) 55.4 55.7°CC (970) (981) 77.8 79.8C °C (1711) (1776) 95.2 95.6C (2284) °C (2298) TX2TX3 26.0 26.0°C◦C (0) (0) 29.2 32.1°C◦C (106) (202) 55.7 55.4°C◦C (981) (970) 79.8 77.8◦C (1776)°C (1711) 95.6 ◦ 95.2C (2298) °C (2284) TX4 26.0°C (0) 31.4°C (177) 52.8°C (883) 79.9 °C (1779) 93.1 °C (2215) TX3TX4 26.0 26.0°C◦C (0) (0) 31.4 29.2°C◦C (177) (106) 52.8 55.7°C◦C (883) (981) 79.9 79.8◦C (1779)°C (1776) 93.1 ◦ 95.6C (2215) °C (2298) TX5TX5 26.0 26.0°C◦C (0)(0) 32.5 32.5°C◦C (214) (214) 55.4 55.4°C◦C (971) (971) 80.4 80.4◦C °C (1794) (1794) 95.8 95.8◦C (2302) °C (2302) TX4 26.0°C◦ (0) 31.4°C◦ (177) 52.8°C◦ (883) 79.9◦ °C (1779) ◦ 93.1 °C (2215) TX6TX6 26.0 26.0°CC (0)(0) 33.5 33.5°CC (248) (248) 52.7 52.7°CC (882) (882) 81.4 81.4C °C (1829) (1829) 95.8 95.8C (2303) °C (2303) TX5TX7 26.0 26.0°C◦C (0) (0) 33.6 32.5°C◦C (252) (214) 53.7 55.4°C◦C (914) (971) 84.8 80.4◦C (1941)°C (1794) 102.7 ◦ 95.8C (2532) °C (2302) TX7 26.0°C (0) 33.6°C (252) 53.7°C (914) 84.8 °C (1941) 102.7 °C (2532) TX6 26.0°C (0) 33.5°C (248) 52.7°C (882) 81.4 °C (1829) 95.8 °C (2303) TX7 26.0°C (0) 33.6°C (252) 53.7°C (914) 84.8 °C (1941) 102.7 °C (2532) 4.4.4.4. Thermal Thermal Balancing Balancing by by PWM PWM Modification Modification

4.4. ToThermalTo verify verify Balancing the the effectiveness effectiveness by PWM Modification of of the the thermal thermal balancing balancing method, method, the the following following experiment experiment was was conducted.conducted. The The LDMOS LDMOS was was connected connected to to a a 6705B 6705B DC DC Power Power Analyzer Analyzer (Keysight, (Keysight, Santa Santa Rosa, Rosa, CA, CA, To verify the effectivenessP of the− thermal balancing method, the following experiment was USA)USA) to to force force a adissipation dissipation of of PD D= 0=−1.5W, 0 1.5W, and and each each gate gate was was controlled controlled by a by 50% a 50%duty duty signal. signal. To conducted. The LDMOS was connected to a 6705B DC Power Analyzer (Keysight, Santa Rosa, CA, provideTo provide one onepulse pulse room room for forPWM PWM modification, modification, one one pulse pulse out out of ofeight eight was was reduced, reduced, as as shown shown in in USA) to force a dissipation of PD = 0−1.5W, and each gate was controlled by a 50% duty signal. To FigureFigure 14a. 14a. This This will will allow allow another another seven seven pulses pulses to to turn turn on. on. Table Table 3 lists temperature measurement provide one pulse room for PWM modification, one pulse out of eight was reduced, as shown in resultsresults before thermalthermal balancing.balancing. Since Since the the MOS MOS power power dissipated dissipated at 0–0.5 at 0–0.5 W, the W, measurement the measurement results Figure 14a. This will allow another seven pulses to turn on. Table 3 lists temperature measurement◦ resultsfor each for bank each in bank Table in3 Tablewere close3 were to close each otherto each and other a significant and a significant temperature temperature difference difference of 9.5 C of at Presults before thermal balancing. Since the MOS power dissipated at 0–0.5 W, the measurement 9.5D °C= 1.5at P W.D = 1.5 W. results for each bank in Table 3 were close to each other and a significant temperature difference of 9.5 °C at PD = 1.5 W. TX0 TX0 TX1 TX1 TX0 TX0 TX2 TX2 TX1 TX1 TX3 TX3 TX2 TX2 TX4 TX4 TX3 TX3 TX5 TX5 TX4 TX4 TX6 TX6 TX5 TX5 TX7 TX7 TX6 K=8 TX6 K=8 TX7 (a) TX7 (b) K=8 K=8 FigureFigure 14. 14. EachEach gate gate signal signal(a) in in the the lateral lateral double-diffused double-diffused MOSFET MOSFET (LDMOS) (LDMOS) ((ba (a)) ) before before modification modification and (b) after modification. andFigure (b) 14. after Each modification. gate signal in the lateral double-diffused MOSFET (LDMOS) (a) before modification and (b) after modification.

Sensors 2017, 17, 1397 12 of 14 Sensors 2017, 17, 1397 12 of 14 Table 3. Measurement results of temperature at 7/8 × 50%.

Bank 0 W 0 A Table 0.1 3.WMeasurement 0.29 A results 0.5 W of0.63 temperature A 1 at W 7/8 0.87× 50%.A 1.5 W 1.03 A TX0 26.0 °C 32.7 °C 55.9 °C 77.6 °C 99.0 °C TX1 Bank 26.0 °C 0 W 0 A 34.4 °C 0.1 W 0.29 A 53.6 0.5 °C W 0.63 A 1 80.8 W 0.87 °C A 1.5 W 1.03 96.7A °C TX2 TX0 26.0 °C 26.0 ◦C 31.9 °C 32.7 ◦C 55.2 55.9°C ◦C 77.6 77.6 °C◦C 99.0 95.0◦C °C ◦ ◦ ◦ ◦ ◦ TX3 TX1 26.0 °C 26.0 C 34.2 °C 34.4 C 55.9 53.6°C C 80.0 80.8 °CC 96.7 95.8C °C TX2 26.0 ◦C 31.9 ◦C 55.2 ◦C 77.6 ◦C 95.0 ◦C TX4 TX3 26.0 °C 26.0 ◦C 31.1 °C 34.2 ◦C 52.5 55.9°C ◦C 79.7 80.0 °C◦C 95.8 92.9◦C °C ◦ ◦ ◦ ◦ ◦ TX5 TX4 26.0 °C 26.0 C 32.1 °C 31.1 C 55.0 52.5°C C 80.0 79.7 °CC 92.9 95.4C °C TX5 26.0 ◦C 32.1 ◦C 55.0 ◦C 80.0 ◦C 95.4 ◦C TX6 26.0 °C 33.1 °C 52.3 °C 81.0 °C 95.4 °C TX6 26.0 ◦C 33.1 ◦C 52.3 ◦C 81.0 ◦C 95.4 ◦C TX7 TX7 26.0 °C 26.0 ◦C 33.3 °C 33.3 ◦C 53.4 53.4°C ◦C 84.5 84.5 °C◦C 102.4 102.4◦C °C

Since TX7 and TX0 were the hottest banks at PD = 1.5 W, their effective duty cycle was reduced Since TX7 and TX0 were the hottest banks at PD = 1.5 W, their effective duty cycle was reduced to to 1/2 × 50% from 7/8 × 50% by PWMMod (as one of every two pulses was suppressed). To maintain 1/2 × 50% from 7/8 × 50% by PWMMod (as one of every two pulses was suppressed). To maintain the the overall duty cycle, the duties for coolest banks TX1–6 are increased to 8/8 × 50% (without overall duty cycle, the duties for coolest banks TX1–6 are increased to 8/8 × 50% (without suppressed). suppressed). Figure 14b plots each gate signal after PWM modification. The original active duty Figure 14b plots each gate signal after PWM modification. The original active duty cycles are all cycles are all 7/8 × 50% as shown in Figure 14a. Moreover, for maintaining the equal electrical 7/8 × 50% as shown in Figure 14a. Moreover, for maintaining the equal electrical characteristics characteristics of the power MOS, seven out of eight banks of the power MOS are turned on during of the power MOS, seven out of eight banks of the power MOS are turned on during each cycle. each cycle. Figure 15 shows the temperature profiles with and without PWM modification. The Figure 15 shows the temperature profiles with and without PWM modification. The temperatures of temperatures of TX0 and TX7 are reduced, whereas the temperatures of TX1-6 are increased because TX0 and TX7 are reduced, whereas the temperatures of TX1-6 are increased because their duty cycles their duty cycles are different from TX0 and TX7. The PWMMod yield the PWM signals without are different from TX0 and TX7. The PWMMod yield the PWM signals without suppressing the duty suppressing the duty cycle for 8/8 × 50% from 7/8 × 50% of TX1–6. Therefore, the original temperature cycle for 8/8 × 50% from 7/8 × 50% of TX1–6. Therefore, the original temperature difference of 9.5 ◦C difference of 9.5 °C is reduced to 2.8 °C (99.2–96.4 °C). is reduced to 2.8 ◦C (99.2–96.4 ◦C).

Figure 15. Photograph of measurement apparatus. Figure 15. Photograph of measurement apparatus.

4.5. Lifetime Improvement 4.5. Lifetime Improvement This paper shows that the equalized temperature in eight banks of power MOS. Based on the This paper shows that the equalized temperature in eight banks of power MOS. Based on the studies in [25,26], the lifetime can be predicted according to the temperature acceleration model studies in [25,26], the lifetime can be predicted according to the temperature acceleration model as follows. as follows. Ea 1 1 τOP × ( − ) AF = = e k TOP TS (10) T τS × = = (10) where AFT is the temperature acceleration factor. Ea is the activation energy, which is assuming to 0.7 eV for the silicon junction defect, and k is the Boltzmann constant is 8.617 × 10−5 eV. A lifetime where AFT is the temperature acceleration factor. Ea is the activation energy, which is assuming to 0.7 ◦ eVtest for for the reliability silicon junction requires defect,τOP = 1000and k h is (0.34 the Boltzmann y) at an operating constant channel is 8.617 temperature × 10−5 eV. A oflifetimeTOP = test 150 forC. Herein, TS is the stress temperature, and τS is the obtained lifetime. Table4 presents the estimated reliability requires = 1000 h (0.34 y) at an operating channel temperature of TOP = 150 °C. Herein, lifetime based on Figure 15. The worse bank determines. Therefore, the lifetime of the power MOS can TS is the stress temperature, and is the obtained lifetime. Table 4 presents the estimated lifetime be improved by 20%, while the balancing method changes the worst bank from TX7 to TX1.

Sensors 2017, 17, 1397 13 of 14

Table 4. Lifetime estimation at 1.5 W power dissipation.

Bank Before Lifetime (Before) After Lifetime (After) TX0 99.0 ◦C 4.73 y 98.2 ◦C 4.96 y TX1 96.7 ◦C 5.42 y 99.3 ◦C 4.65 y TX2 95.0 ◦C 6.00 y 98.1 ◦C 4.99 y TX3 95.8 ◦C 5.72 y 98.6 ◦C 4.84 y TX4 92.9 ◦C 6.81 y 96.4 ◦C 5.52 y TX5 95.4 ◦C 5.86 y 98.7 ◦C 4.81 y TX6 95.4 ◦C 5.86 y 96.4 ◦C 5.52 y TX7 102.4 ◦C 3.88 y 98.2 ◦C 4.96 y

5. Conclusions This paper proposes a thermal balancing method for monolithic power ICs. The method yields the exact chip temperature and heat distribution, which can thus be changed to improve the lifetime of the power MOS in the test chip. According to the readings of a real-time LDMOS junction thermometer, the thermal balancing method modulates individual gate PWM control and modifies the operating time of each MOSFET banks of the power MOS. The proposal includes a calibration mechanism that mitigates process variation and layout mismatches. A test chip with eight parallel MOSFET banks was fabricated by using the TSMC 0.25 µm HV BCD process. The balancing mechanism was developed through the FPGA board. The experimental results inferred that, under a power dissipation of 1.5 W, the maximal temperature variation among the eight banks was 9.5 ◦C without modification and 2.8 ◦C with modification. The full chip lifetimes of the power MOS are determined by the maximal temperature of the MOSFET bank. This paper verified that the temperature of the hottest bank was reduced from 102.4 ◦C (TX7) to 99.3 ◦C (TX1), which improves the overall lifetime by 20%. Since a large active die area increases temperature difference, the lifetime is proportional to the area of power MOS. According to the temperature acceleration model, the lifetime can be further improved in practical cases.

Acknowledgments: The authors would like to thank CIC for helping the chip’s tape-out and infrared measurement support, TSMC Semiconductor Fab for providing the 0.25 µm HV BCD process manufacture, and Department of Device Engineering of Vanguard International Semiconductor Corporation for the measurement and thermal simulation support. Author Contributions: Tingyou Lin is the project leader and developed and verified the whole circuits and the system. Yingchieh Ho gave helpful comments on project and planning, scheduling, and debugging the results of the experiments. Chauchin Su is the supervisor and provided insightful comments and suggestions. Conflicts of Interest: The authors declare no conflict of interest.

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