Overview of Computer Architecture

Tele 2060 Overview of Computer Architecture

• General Von-Neumann Approach

Other Architectural Approaches Also Exist • Components

ALU

Memory

Control

Input/Output

Martin B.H. Weiss Review of Digital Circuits - 1 University of Pittsburgh

Tele 2060 ALU

• Arithmetic-Logic Unit • Heart of a Computer • Basic Arithmetic Functions are Performed

Martin B.H. Weiss Review of Digital Circuits - 2 University of Pittsburgh Tele 2060 Memory

• Closely Tied to ALU • Used to Store Data Bytes • Classes of Memory Main Memory Cache Memory Registers

Martin B.H. Weiss Review of Digital Circuits - 3 University of Pittsburgh

Tele 2060 Control

• Controls Memory and ALU • Controls the Execution of Programs • Input/Output • Interface to the Rest of the World Terminals Printers Secondary Storage (disk)

Martin B.H. Weiss Review of Digital Circuits - 4 University of Pittsburgh Tele 2060 Logic circuits

• Used to Implement Logical Functions In Computers • Example Addition of Two Bits Operation: 0+0=00, 0+1=01, 1+0=01, 1+1=10 Result is Two Bits: SUM and CARRY Resultant Expression:

SUM = A'B + AB'

CARRY = AB

Truth Tables

S(A)01 C(A)01 0 01 0 00 (B) (B) 1 10 1 01

Martin B.H. Weiss Review of Digital Circuits - 5 University of Pittsburgh

Tele 2060 Representing Binary Functions

• Truth Tables • Algebraic Expression Canonical Forms

Sum of Products • Sum of Minterms • Minterm is a Product-Only Term

Product of Sums

Product of Maxterms

Maxterm is a Sum-Only Term Need New Algebra

Traditional Algebra Does Not Apply

New Relationships Hold

Martin B.H. Weiss Review of Digital Circuits - 6 University of Pittsburgh Tele 2060 Boolean Algebra

• Functions, Operators, and Truth Tables AND OR NOT XOR

Martin B.H. Weiss Review of Digital Circuits - 7 University of Pittsburgh

Tele 2060 AND Function

A AND B = AB = A.B = AB∧

Truth Table: 01(A) 000 (B) 101

Logic Diagram:

Martin B.H. Weiss Review of Digital Circuits - 8 University of Pittsburgh Tele 2060 OR Function

A OR B = A+B = AB∨

Truth Table: 01(A) 0 01 (B) 1 11

Logic Diagram:

Martin B.H. Weiss Review of Digital Circuits - 9 University of Pittsburgh

Tele 2060 NOT Function

NOT A = A' = A

Truth Table: A 0 1 1 0

Logic Diagram:

Martin B.H. Weiss Review of Digital Circuits - 10 University of Pittsburgh Tele 2060 XOR Function

A XOR B = AB⊕

Truth Table: 01(A) 0 01 (B) 1 10

Logic Diagram:

Martin B.H. Weiss Review of Digital Circuits - 11 University of Pittsburgh

Tele 2060 Properties of Boolean Algebra

• Idempotence x+x=x x.x=x x+1=1 x.0=0 x+0=x x.1=x • Communtativity x+y=y+x x.y=y.x

Martin B.H. Weiss Review of Digital Circuits - 12 University of Pittsburgh Tele 2060 Properties of Boolean Algebra

• Associativity (x+y)+z=x+(y+z) (x.y).z=x.(y.z) • Complementation x+x'=1 x.x'=0 • Distributivity x.(y+z)=x.y+x.z x+y.z=(x+y).(x+z) • De Morgan's Theorem Important Boolean Algebra Theorem (A+B)' = A'B'

Martin B.H. Weiss Review of Digital Circuits - 13 University of Pittsburgh

Tele 2060 Example

•Show:xyxyxy⊕=⋅+⋅ • Proof by Truth Table Compute the Intermediate Products Compare the Two Outputs Since They Are Identical, The Relation is Valid

Input Output Output xy xy⋅ xy⋅ xy⋅ +xy⋅ xy⊕ 00 0 0 0 0 01 1 0 1 1 10 0 1 1 1 11 0 0 0 0

Martin B.H. Weiss Review of Digital Circuits - 14 University of Pittsburgh Tele 2060 Karnaugh Maps

• Alternate Form of Digital Representation • Can Be Used to Design Circuits • Two Variable Karnaugh Map:

Y' Y

X' X'Y' X'Y

X XY' XY

For F = XY+XY': Y 01 X 0 - -

1 1 1

Martin B.H. Weiss Review of Digital Circuits - 15 University of Pittsburgh

Tele 2060 Three Variable Karnaugh Maps

• Adjacent Squares Are Minterms That Differ Only in a Single Variable

Y'Z' Y'Z YZ YZ'

X' X'Y'Z' X'Y'Z X'YZ X'YZ'

X XY'Z' XY'Z XYZ XYZ'

Martin B.H. Weiss Review of Digital Circuits - 16 University of Pittsburgh Tele 2060 Three Variable K-Map Examples

Example: F=+++=+∑ m(,,,)0234 XYZ XYZ XYZ XYZ YZ XY

YZ 00 01 11 10 X 0 1- 11

1 1- --

Example: F==++++=+∑ m(,,,,)01246 XYZ XYZ XYZ XYZ XYZ Z XY

YZ 00 01 11 10 X 0 11 -1

1 1- -1

Martin B.H. Weiss Review of Digital Circuits - 17 University of Pittsburgh

Tele 2060 Four Variable Karnaugh Maps

• The Map Has 16 States (4 Rows x 4 Columns) • Simplification Rules One Square Represents a Minterm of Four Literals Two Adjacent Squares Represent a Product Term of Three Literals Four Adjacent Squares Implies the Product Term of Two Literals

Eight Adjacent Squares Implies the Product Term of One Literal

Martin B.H. Weiss Review of Digital Circuits - 18 University of Pittsburgh Tele 2060 Circuit Implementation

• Gate Representations NAND

Any Digital System Can Be Implemented with NAND

Widely Used in Practice NOR

Complement to NAND

Also Universal XOR

XY = XY'+X'Y • Two Level Implementation

F =AB+CD = ((AB)'(CD)')' NAND Implementation

Martin B.H. Weiss Review of Digital Circuits - 19 University of Pittsburgh

Tele 2060 Integration Levels

•SSI Several Gates in an IC The “Glass” Modem Uses SSI •MSI 10 to 100 gates in an IC Registers, Latches, Adders, etc. Could Be MSI • LSI 100 to a Few Thousand Gates CPU's, Memory, etc. • VLSI Large Memory Chips 32 bit CPU's, etc.

Martin B.H. Weiss Review of Digital Circuits - 20 University of Pittsburgh Tele 2060 Logic Families

•TTL Transistor-Transistor Logic One of the Oldest Normally Uses +5V and Ground as Supplies A "1" is Normally 3.5 to 5V A "0" is Normally 0 to 1.4V Medium Speed, Moderate Density, Moderate Power Consumption • CMOS More Recent Low Power, Moderate Speed, High Density Can Run Off of a Variety of Supply Voltages (+5, +12)

The Threshold is Normally About .5 of Vcc Martin B.H. Weiss Review of Digital Circuits - 21 University of Pittsburgh

Tele 2060 Logic Families

•ECL High Speed, High Power, Moderate Density Runs at Vcc of -3V

Threshold is About 1/2 of Vcc

Martin B.H. Weiss Review of Digital Circuits - 22 University of Pittsburgh Tele 2060 Logic Families of Popular CPU Chips

• Traditional High Speed Computers are Implemented in ECL IBM 3090 DEC VAX 9000 • Most New Chips are CMOS DEC

Alpha

NVAX IBM - PowerPC HP - PA-RISC

Intel - Pentium Sun/TI - SuperSPARC

Martin B.H. Weiss Review of Digital Circuits - 23 University of Pittsburgh

Tele 2060 Other Practical Concepts

• Fan Out Number of Inputs an Output Can Support Typically Around 10 Need a Driver if More Inputs are Attached • Propagation Delay Time it Takes for a Signal to Propagate from Input to Output The Lower the Propagation Delay, the Faster the Chip • Power Dissipation - Amount of Power Used by the Gate

Martin B.H. Weiss Review of Digital Circuits - 24 University of Pittsburgh Tele 2060 Standard Pin Arrangements

• 16 pin DIP

8 - Ground Dot or Notch 16 - Vcc • 14 pin DIP 7 - Ground 1 16 14 - Vcc • 8 pin DIP 4 - Ground

8 - Vcc 89

Martin B.H. Weiss Review of Digital Circuits - 25 University of Pittsburgh

Tele 2060 Definition of Combinational Circuits

• Perform a Mapping Between n Binary Inputs m Binary Outputs • Use a Combination of Gates

Martin B.H. Weiss Review of Digital Circuits - 26 University of Pittsburgh Tele 2060 Analysis Procedure for Combinational Circuits

• Identify Inputs • Identify Outputs • Write Outputs in Terms of Inputs • Create a Truth Table for the Function

Martin B.H. Weiss Review of Digital Circuits - 27 University of Pittsburgh

Tele 2060 Design Procedure for Combinational Circuits

• Determine the Required Outputs and Assign a Letter • Create a Truth Table for the Function • Write the Boolean Functions for Each Output • Simplify (Use Boolean Algebra or K-Maps) • Draw Logic Diagram

Martin B.H. Weiss Review of Digital Circuits - 28 University of Pittsburgh Tele 2060 Example of Combinational Circuit Design

A B C Z Z=++++ AB C A BC AB C AB C ABC 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 BC 00 01 11 10 1 0 1 1 A 1 1 0 0 0 1- -1 1 1 1 1 1 11 1-

ZACBCAC=++

Gate Schematic Martin B.H. Weiss Review of Digital Circuits - 29 University of Pittsburgh

Tele 2060 Combinational Building Blocks

•Adder • Decoder/Encoder • Multiplexer

Martin B.H. Weiss Review of Digital Circuits - 30 University of Pittsburgh Tele 2060 Adder

• Half Adder Adds Two Bits Produces SUM and CARRY Truth Table & Logic Circuit (p. 89) • Full Adder Adds Three Bits

Two Bits

Carry from Previous Stage Produces SUM and CARRY

Truth Table & Logic Circuit (p. 90, 91)

Martin B.H. Weiss Review of Digital Circuits - 31 University of Pittsburgh

Tele 2060 Decoder

• Function Convert a Binary Input to a Single Line Output eg Three Digit Binary Number has Eight Values (or Lines) Associated With It • Truth Table & Diagram: p. 97 • Encoder is the Inverse Function

Martin B.H. Weiss Review of Digital Circuits - 32 University of Pittsburgh Tele 2060 Multiplexer

• Function Select One of Four Inputs Under Control of CONTROL Signals • Logic Implementation Block Diagram Truth Table • Gate Representation (Fig 1.18, p. 38)

Martin B.H. Weiss Review of Digital Circuits - 33 University of Pittsburgh

Tele 2060 Timing Considerations

• Most First-Order Analyses Assume Immediate Gate Response • More Sophisticated Analyses Must Include Gate Delays • Race Conditions Occur When the Output of A Combintational Circuit Depends on the Order in Which Signals Arrive at Various Gates The Signals Are in a “Race” to Get to the Input

Usually the Result of a Bad Design May Need a Clock Signal to Elimate

Martin B.H. Weiss Review of Digital Circuits - 34 University of Pittsburgh