AR214 Microcoded Microprocessor Simplifies Virtual-Memory

4R214 ticrocoded microprocessor simplifies Yirtual-memory management When the operating system handles virtual-memory operations the programmer is liberated from clumsy restrictions by ThOmaS W. Starnes, Motorola Ltd., Semiconductor Products Sector, Milton Keynes, Engtand fl Virtual-memory techniques have been implemented lets a user write a program that is too large to fit com- successfully in mainframes and minicomptuers in the fortably in the available semiconductor memory. past. But schemes to extend the memory in microproces- A good way to determine what information the primary sor systems have had two major drawbacks. Either they should contain is to allow the natural flow of instructions required an additional microprocessor to perform virtual- and references to data to feed primary memory as the memory operations or their software had to be written in executing program demands. This method takes the bur- overlays within well-defined boundaries. Motorola's den from the application programmer and places it on MC68010, however, allows the operating system to han- the processor supported by the operating system and is dle virtual-memory operations, freeing the application ideal for virtual memory systems. programmer from the restrictions previous designs had. tanaging data intelligonily To fully support a virtual-memory scheme, the 16-bit microcoded microprocessor has seventeen 32-bit general Because instructions normally follow in sequence, a purpose registers, a 32-bit program counter, a l6-bit sta- program usually executes within a relatively narrow win- tus register, a 32-bit vector register, and two 3-bit alter- dow around the current instruction. That is, if instruc- nate-functi,on code registers. tioq n is executing, chances are that fhe next instruction Permanent storage and tempotary random-access to execute is fairly close by, and most likely is n + 1. memory need to be finely balanced to make a system Therefore, if the primary always contains the current both cost-efficient and operationally sound. Virtual mem- instruction and the sections of code immediately before ory combines primary memory-the semiconductor ariO after it, chances are good that the processor will memory to which the processor has direct access-with a continue to execute the instructions out of primary mem- secondary storage unit, such as a tape, drum, or hard or ory: the primary's contents are filled with information floppy disk, to yield a low-cost-per-bit increase in the that falls within a short range of the present instruction. system's apparent memory. In practice, virtual memory The MC68010, however, easily manages situations that T .r- x x MMU T E L tL tL ,L (MAIN} + + PHYSICAL MEMO RY I I IL Enl L (MAIN} I PHYSICAL MEMO RY SECONOARY DISK SECONOARY DISK MEMO RY MEMO RY (a) (b) l. Xew plga When the data to be accessed is outside the primary memory's physical boundaries, the correct intormation block must be copied lrom secondary memory. To access the ADD instruction (a), a new section must be moved from socondary into main memory (b). Reprinted from ELECTRONICS, December 1, 1983. Copyright O 1983, McGraw-Hill lnc. All rights reserved. Scheme$ fw managing vittral memor! A nurnber of virtual-mornory schemes have been tried dynamically, and the programmer must be constantly aware previously in microprocessor-based systems; most of them of the segment's boundaries. He or she is better ofi if such turned out to be clumsy and inefficient, putting additional considerations are unnecassary. burdens on either the programmer or the microprocessor, or both. The pro- cesses basic to most schemes, how- ilI680 (l ADORESSES otsK L0cATloNs ever, sound very simple. Typically, 150 150 (see part a of the figure), when the RAND0lul-ACCESS MEIUIORY LOCATIOilS central processing unit attempts to (ltlEi,l0 RY' }IANAGEIIET{T Ut{IT access a memory location outside AOORESS OUTPUT} the physical memory, a bus-fault sig- 150 nal notifies the procassor that some- thing is amiss. At this point, the operating system must determine which block of secondary memory to copy 150 into primary memory. Once the oper- PHYSICAL (tulAlil) ating system has shifted the propor ME}IO RY block of memory and updated the memory rnanager, the CPU can continue to access the needed information frorn the physical memory. A more practical system breaks up memory into more defined pieces and SECOI{DARY IUTE}IO RY keeps many more active blocks in primary memory (see part b of the DrsK LocATl0l{s figure). One block might contain in- 150 structions, another necessary data. Sorne CPUs segment memory in ir6_80!,0 Aqo_REssE9 15 0 an attempt to manage memory use RAr{D0il-AccEss efficiently, but this introduces rnore rEtroRY L0cATl0ils - problerns than it solves. The operat- (ilEm0RY' ITAIiIAGEMETllT UNIT ing system must determine the prima- AODRESS OUTPUT} ry's best contents. This may b basd 150 on the Upe or sections of code that are expcted to be executed and the data that the code needs. It is the programmer who must Pro- 150 vide this information to the operating PHYSICAL (MAIN) TIEMO RY systern each time a portion of code executes, which forces the programmer to match the program's mernory requirements to the arrangement of physical memory. This could cause great problems if all the needed segments to be accessed exceeds the primary memory's physical bounds. 150 Segment constraints and size limita- SECONOARY TUIE]UIORY tions thus restrict the freedom of any (b) of these segments to grow, especially require an instruction beyond the reach of the primary The central procesing unit knows the primary only as memory's current contents or require data from a section 0 through L. When the processor accesses the memory of memory not in the vicinity of the data recently ac- .address at L+ 1 (aOn), no information can come directly cessed. In a simplified example (Fig. la), if primary from primary memory. But in order to access this word, memory is L words long and contains an L-sized copy of which is really at X+L+l, the block of information secondary mernory, and the memory block begins at X in surrounding X+L+l must first be copied into the pri- the second &f!, the primary memory's contents may be mary. A convenient block may be between X + L and described as being bounded by X and X + L. X+L+L, which is the next L-sized block in secondary memory. This block is now copied into primary memory, enabling the processor to fetch not only the original BUS. address at L+ I (noo) but also the next address at L+2 ERROR MC68010 (cur) from the primary (Fig. lb). SIG NAL, In reality, of course, bringin g a block of new informa- BERR FAU LT- tion into primary memory may be more complex. The t[ili!fii''- OEPENDENT) programmer must make sure that the data existing in STACK BUS.E R RO R primary memory is not overwritten and lost. To ensure POINTER rr{F0 RMAT|0ir that the old information is safe, the existing block in the INTERNAL. primary might first have to be copied back into the STATE secondary. The operating system determines whether sec- IN FO RMATIO N ondary memory needs updating, and action is facili- this SUPERVISOR tated by a modified bit in the memory manager. This bit STACK indicates if any write operations have taken place in the memory block after it was moved into the primary. (a) Bus.eror reeouert FAU Lr- RE-T,qlN-f!9M The MC68010 uses instruction continuation to support COnnLClOn EXCEPTI0N CONTINUE ROUTI*'I ATTEMPT \ O LO virtual memory. Basically, this approach involves starting oLD D tNsrnucnor\ (SYSTEM. V BUs cYcLE Y an instruction, flagging a fault to the cPU before the OEPENOENT) lSrrrr'0, instruction ends, and suspending the instruction in an orderly fashion (Fig. 2a). It then provides a mechanism to allow the instruction to pick up where it left off once the fault is corrected and continue through completion. To do this, when a page fault occurs, the processor stores its internal state; after the page fault is repaired, it re- stores that internal state and continues to execute the instruction. Though this technique is difficult to imple- ment in random-logic CPUs, it is relatively simple with a microcoded processor. Instruction continuation appears to be b'est for the user and frees the application programmer from the restric- 2. Recovery. Using an instruction-continuation technique, Motoro- tions of other schemes. An alternative is instruction re- la's MC68010 receives a bus-error signal (BERR) when a page fault start. Here, the processor must remember the system's occurs (a) and then aborts the instruction. lt saves all the information exact state before each instruction starts in order to on the supervisor stack so that when the CPU returns from the restore the stage if a page fault occurs during execution. correction routine, the return-from-exception (RTE) i nstruction reruns In addition, no memory fault is fully recoverable. the faulted bus cycle and the instruction continues to execute. To implernent intruction continuation, the MC68010 uses a bus-error (nenn) signal-which can cause any and The cPU gets external information, such as the type of all instructions to abort befope even a bus cycle is com- error from the memory-management unit. If the system pleted-to warn the processor that there is a problem uses an error-detecting circuit, it might be polled to with the bus cycle in progress. When the MC680l0 re- determine the nature of the error it found on the data ceives a bus-error signal, it aborts the bus cycle and bus.

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