Silicon Photonic Platforms and Systems for High-Speed Communications

Silicon Photonic Platforms and Systems for High-speed Communications

Ari J. Novack

Submitted in partial fulﬁllment of the requirements for the degree of Doctor of Philosophy in the Graduate School of Arts and Sciences

COLUMBIA UNIVERSITY

Silicon Photonic Platforms and Systems for High-speed Communications

Ari J. Novack

Data communication is a critical component of modern technology in our society.

There is an increasing reliance on information being at our ﬁngers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced pro- ductivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the diﬃculties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs.

Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications.

The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication.

Details regarding the optimization and test of modulators are also presented with the ﬁrst-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform.

Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating

Metal-Semiconductor Field Eﬀect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical ﬁnal piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser.

In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the ﬁrst published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform. Contents

List of Figures v

List of Tables xii

Glossary xiii

Acknowledgments xvi

Chapter 1 Introduction 1

1.1 Optical Interconnects and the Drive for More Data ...... 1

1.2 Next Generation Optical Links ...... 6

1.3 Silicon Photonics Devices and Platforms ...... 10

1.4 Scope of Thesis ...... 12

Part I Silicon Photonics: Devices and Platform 14

Chapter 2 Germanium Photodetector with 60 GHz Bandwidth Us-

ing Inductive Gain Peaking 15

2.1 Introduction ...... 16

i 2.2 Baseline Detector Modeling ...... 17

2.3 Gain-peaked Detector Modeling ...... 19

2.4 Fabrication ...... 22

2.5 Experimental Results ...... 23

2.6 Conclusion ...... 26

Chapter 3 Low Power 50 Gb/s Silicon Traveling Wave Mach-Zehnder

Modulator Near 1300 nm 27

3.1 Introduction ...... 28

3.2 Traveling Wave Design ...... 29

3.3 Fabrication ...... 32

3.4 Device Characterization ...... 33

3.5 Conclusion ...... 38

Chapter 4 Silicon Parallel Single Mode 48 x 50 Gb/s Modulator and

Photodetector Array 41

4.1 Introduction ...... 42

4.2 Fabrication and Platform Capabilities ...... 44

4.3 System Design ...... 46

4.4 Testing Methodology ...... 51

4.5 Results ...... 52

4.6 Conclusion ...... 61

ii Part II Complimentary Components 62

Chapter 5 Monolithically Integrated MESFET Devices on a High-

Speed Silicon Photonics Platform 63

5.1 Introduction ...... 64

5.2 Platform Fabrication and Design Contraints ...... 66

5.3 Results and Discussion ...... 69

5.4 Conclusion ...... 74

Chapter 6 Widely-tunable, Narrow-linewidth III-V/silicon Hybrid

External-cavity Laser for Coherent Communication 75

6.1 Introduction ...... 76

6.2 Laser Design ...... 78

6.3 Laser Fabrication and Integration ...... 83

6.4 Laser Characterization ...... 84

6.5 Coherent Transmission ...... 91

6.6 Discussion ...... 95

6.7 Conclusion ...... 96

Part III Highly Integrated Optical Links 97

Chapter 7 A Silicon Photonic Transceiver and Hybrid Tunable Laser

for 64 Gbaud Coherent Communication 98

7.1 Introduction ...... 99

iii 7.2 Hybrid Laser Integration and Performance ...... 101

7.3 Performance in a Coherent Link ...... 103

7.4 Conclusion ...... 104

Chapter 8 Thesis Conclusion 106

8.1 Summary of Contributions ...... 106

8.2 Recommendations for Future Work ...... 106

8.3 Final Remarks ...... 111

Bibliography 112

iv List of Figures

1.1 Plot of various historical technologies across time and their relative BL [1]. 2

1.2 Capacity-Distance performance of generations of optical communication

technologies across the late 1900s [2]...... 4

1.3 Global internet traﬃc by device type for 2017-2022 [3] ...... 6

1.4 Datacenter traﬃc growth through 2019. [4] ...... 7

1.5 Penetration of optical links into communications. (a) Timeline of optical

interconnect into digital application area by link distance and bandwidth.

(b) Data-rate vs Distance for electrical and optical interconnects [5]. . . . 8

1.6 Diagram showing the thesis hierarchy...... 13

2.1 Junction capacitance per unit area as a function of reverse bias voltage

(positive voltage on graph is reverse bias). The curve was measured by

determining the capacitance from the detector S11 parameter (as seen in

inset) using a number of test structures of diﬀerent areas...... 19

2.2 Gain peaking circuit model. The addition of an inductor is used to peak

the frequency response of the photodetector...... 20

v 2.3 Optical micrograph of the gain peaked photodetector using the 360 pH

inductor. The inductor is approximately 100 um x 100 um in size. . . . . 21

2.4 OpSIS-IME platform schematic. The detector is built using germanium

grown epitaxially on unetched silicon. The inductors use the two metal

layers. The lower via layer provides contact to the germanium. The anode

of the detector is not shown...... 22

2.5 Photodetector cross section showing the detector p-i-n junction and metal

contacts. The anode and cathode are shown...... 23

2.6 a) EO S21 and b) detector S11 response at 2V reverse bias of the unpeaked

detector as well as the detectors with both small and large inductors.

Points are from data, colored lines are smoothed data and black dashed

lines are ﬁts to the circuit model...... 25

2.7 a) Phase delay of EO S2S211 normalized to the unpeaked detector. b)

Group delay variation of EO S21 calculated from the circuit model ﬁt to

show eﬀective group delay variation of measured data...... 26

3.1 (a) Micrograph of the device. (b) Simpliﬁed cross sectional diagram of the

phase shifter, not to scale...... 30

3.2 (a) Typical spectrum at various reverse biases. (b) Phase shift vs reverse

bias of typical phase shifter. A small-signal Vπ is measured to be 8.8 and

8.1 V for the bottom and top arms, respectively, between 0 V and 1 V

reverse bias. (c) C-V curve of the pn junction of the phase shifter. (d)

Measured I-V curve of the device without RF termination...... 34

vi 3.3 (a) Simpliﬁed cross section of the thermal phase tuner. (b) Tuning eﬃ-

ciency of the thermal tuner. The power required to shift the wavelength

by π is measured to be 27 mW...... 35

3.4 (a) Electrooptic S21 of each arm at 0 V reverse bias. Input light is set to

the -3 dB point in the optical spectrum. (b) S11 of the device...... 36

3.5 50 Gbps eye diagrams using a diﬀerential pseudorandom 215-1 signal. (a)

1.5 Vpp amplitude and 0 V reverse bias. (b) 2.0 Vpp amplitude and 0 V

reverse bias. (c) 3.0 Vpp amplitude and 1.0 V reverse bias. In all eye

diagrams, input light is biased at the -3 dB optical point, 1301.91 nm. . . 38

4.1 Cross-section and rendering of the key devices of the OpSIS platform (not

to scale) [6] ...... 44

4.2 (a) The small signal VπL versus bias voltage of the PDK traveling wave

Mach-Zehnder modulator. The small signal VπL is 2.6 V-cm at a -1 V

reverse bias. (b) EOS21 response of the Mach-Zehnder modulator at 0 V

and -1 V reverse bias...... 46

4.3 (a) PDK gain-peaked photodetector I-V response under illumination and

dark showing 0.75 A/W responsivity and 0.61 µA dark current at -2 V

bias. (b) Frequency response showing 3-dB bandwidth in excess of 40 GHz. 47

4.4 Block diagram (a, c) of each channel of the transmitter and receiver and

photographs (b, d) of the transmitter and receiver chips with key features

identiﬁed...... 48

vii 4.5 Block diagrams of the test setup for the transmitter (a) and receiver (b)

chips...... 50

4.6 (a) Average insertion loss across the 48 channels of the transmitter is -

11.89 dB ± 0.83 dB. (b) The thermal tuning eﬃciency of the phase tuners

is 90 mW/π...... 51

4.7 Measured S11 of the traveling wave modulator with on-chip termination

resistor...... 53

4.8 (a) Bit error rate versus received optical power of all 48 channels of the

silicon transmitter using a PRBS31 signal. A comparison trace using a

commercial LiNbO3 modulator in place of the transmitter is shown in

red. (b) Optical eye diagrams of a typical silicon modulator channel at 50

Gb/s, (c) as well as the LiNbO3 modulator at 50 Gb/s for comparison (c). 55

4.9 Statistics of the BER versus received optical power of the silicon trans-

mitter. Receiver sensitivities at a BER of 10-9 (a) show high uniformity

across all channels, as do the slopes (b) of the BER1/2 vs. power traces. . 56

4.10 Typical receiver eye diagrams at 43 Gb/s (a) and 50 Gb/s (b)...... 57

4.11 Electrical S21 of driving transmission line contact pads of adjacent arms

of two neighboring modulators...... 59

5.1 Cross-section of silicon photonic platform showing grating couplers, ger-

manium detectors, modulators, and n-type MESFET. Inset shows the

detailed geometry of the MESFET...... 67

viii 5.2 Data taken from photonic devices on the same wafer as the transistors. (a)

Photodetector responsivity at 1550 nm, (b) Photodetector dark current

and (c) 1310 nm modulator 40G eye diagram...... 68

5.3 Measured ID –VDS of the NMES transistor...... 69

5.4 Measured IDD–VDS of the NMES transistor...... 70

5.5 Measured ID–VG curves for the NMES at various drive voltages in linear

scale (top) and log scale (bottom)...... 71

5.6 Measured IG–VG curves for the NMES at various drive voltages...... 72

5.7 Plot of a NMES gate capacitance and cutoﬀ frequency as a function of

gate voltage...... 72

6.1 A schematic view of the tunable laser...... 78

6.2 Magnitude of the electric ﬁeld for (a) the silicon nitride waveguide on the

silicon photonic chip, and (b) for the RSOA chip...... 80

6.3 Simulated mode mismatch between the silicon photonics chip and the SOA

as a function of misalignment in the horizontal (x) and vertical direction

(y)...... 81

6.4 (a) Reﬂected spectra of the Vernier ring, normalized to the maximum

power of the reﬂected spectra. The red line is the simulated spectrum,

while the red dots are the measured spectrum. (b) Reﬂected spectra of

R1 (red) and R2 (blue). The solid lines are the simulated spectrums, and

the red dots are measured spectrums...... 82

ix 6.5 (a) Optical image showing the Vernier ring reﬂector. The left ring res-

onator has a radius of 20 µm (R1), and the right ring resonator has a

radius of 16.3 µm (R2). (b) Optical image showing the III-V die and

waveguide coupler. Two laser channels are aligned and packaged simulta-

neously...... 84

6.6 (a) L-I-V curve of hybrid laser. Blue and red curve are L-I and I-V curves

correspondingly. (b) Extracted experimental WPE. (at 1546.88 nm) . . 86

6.7 (a) Spectral-L-I data without wavelength stabilization. (b) Spectra-L-I

data with wavelength stabilization control...... 86

6.8 Lasing wavelength under diﬀerent R1 and R2 basing powers. The diamond

markers indicate the basing powers at diﬀerent ITU grid...... 88

6.9 Measured lasing spectra of the tunable laser across the C-band...... 88

6.10 (a) Measured laser output power spectrum with the highest SMSR of

55 dB. (b) Measured SMSR at C-band, 100-GHz-spacing DWDM ITU

grid. (c) FM-noise spectrum using heterodyne laser linewidth measure-

ment method at 1553 nm. (d) Measured linewidth at diﬀerent wavelengths

across the C-band...... 89

6.11 34-Gbaud DP-16QAM experimental setup (main). Image of IMRA (inset). 92

6.12 Measured BER vs. OSNR at 1547.2 nm...... 93

6.13 Constellation diagram of the 34 Gbaud DP-16 QAM using (a), (c) our

ECL, and (b), (d) reference laser...... 94

x 7.1 (a) Block diagram of the tunable laser. Microscope images of (b) the

external cavity and (c) hybrid integrated RSOA (backside ...... 101

7.2 Measurements of one sample of the silicon photonic hybrid integrated laser:

(a) linewidth vs. wavelength, (b) SMSR vs. wavelength, (c) lasing wave-

length as a function of ring tuning powers, and (d) lasing spectrum at

various points across the C-band...... 101

7.3 (a) Block diagram of the CSTAR PIC, (b) underside of the CSTAR pack-

age (footprint 15 x 18 mm), (c) populated CSTAR substrate pre-ﬁber at-

tach, (d) CSTAR assembled into a CFP2-ACO, and (e) VNA measurement

of the CFP2-ACO transmitter showing 40 GHz electro-optic bandwidth. 102

7.4 (a) A 34 Gbaud DP-16QAM constellation using the CSTAR. The silicon-

photonic hybrid laser is used as a light source in two applications (b)

Single-pol 64 Gbaud QPSK BER vs. OSNR of the CSTAR-based CFP2-

ACO, measured on an OMA. (c) Dual-pol 34 Gbaud 16QAM BER vs.

OSNR of an Integrated Modulator and Receiver Assembly (IMRA) com-

paring our ECL to a commercially available low- linewidth µITLA. . . . 104

xi List of Tables

2.1 Fit and expected photodetector parameters. For values that vary between

the detectors, three measurements are shown for the unpeaked/small in-

ductance/large inductance detectors...... 25

3.1 Comparison to Other Traveling-Wave Modulators in Silicon at 40 Gbps

and Above...... 40

6.1 Performance comparison of recent C-band tunable laser works ...... 95

xii Glossary

ADC Analog-Digital Converter. DWDM Dense Wavelength-division

ASE Ampliﬁed Spontaneous Emission. Multiplexing.

ECL External Cavity Laser. BER Bit-error Rate. EDFA Erbium-doped Fiber Ampliﬁer. BGA Ball Grid Array. EO Electro-optic.

CMOS Complimentary Metal Oxide ER Extinction Ration.

Semiconductor. FDTD Finite Diﬀerence Time Domain.

CSTAR Coherent Silicon Transmitter FEC Forward Error Correction.

and Receiver. FSR Free Spectral Range.

CW Continuous Wave. HR High Reﬂectivity.

DAC Digital-Analog Converter. I/O Input/Output.

DC Directional Coupler. IC Integrated Circuit.

DCA Digital Communications Analyzer. IME Institute of Microelectronics.

DP Dual-Polarization. IMRA Integrated Modulator and Re-

DSP Digital Signal Processor. ceiver Assembly.

xiii ITLA Integrated Tunable Laser Assem- PD Photodetector.

bly. PDK Process Design Kit.

ITU International Telecommunication PIC Photonic Integrated Circuit.

Union. PM Polarization-maintaining.

PMES P-type Metal-Semiconductor MESFET Metal-Semiconductor Field- (Field-eﬀect Transistor). eﬀect Transistor. PRBS Pseudo Random Bit Sequence. MFD Mode Field Diameter.

MOSFET Metal-Oxide-Semiconductor Q Quality.

Field-eﬀect Transistor. QAM Quadrature Amplitude Modula-

MPD Monitoring Photodetector. tion.

MPW Multi-project Wafer. QPSK Quadrature Phase Shift Keying.

MQW Multiple Quantum Well. RF Radio Frequency. MZI Mach-Zehnder Interferometer. RIN Relative Intensity Noise. MZM Mach-Zehnder Modulator. RMS Root Mean Square.

NMES N-type Metal-Semiconductor RSOA Reﬂective Semiconductor Optical

(Field-eﬀect Transistor). Ampliﬁer.

NRZ Non-Return to Zero. RX Receiver.

OOK On-oﬀ Keying. SM Single Mode. OpSIS Optoelectronic System in Silicon. SMSR Side-mode Suppression Ratio. OSA Optical Spectrum Analyzer. SOA Semiconductor Optical Ampliﬁer. OSNR Optical Signal to Noise Ratio. SOI Silicon on Insulator.

PCB Printed Circuit Board. SSC Spot Size Converter.

xiv TE Transverse Electric. VOA Variable Optical Attenuator.

TEC Thermo-electric Cooler.

TIA Trans-impedance Ampliﬁer. WDM Wavelength-division Multiplex-

TM Transverse Magnetic. ing.

TX Transmitter. WPE Wall Plug Eﬃciency.

VNA Vector Network Analyzer. WSR Wavelength-selective Reﬂector.

xv Acknowledgments

There are many people who made signiﬁcant contributions directly and indirectly to the research in this thesis.

First, I would like to thank my academic advisors. My path to a degree had many turns and their support of my eﬀort to complete this course of study is greatly appreciated. Dr. Michael Hochberg and Dr. Tom Baehr-Jones have my heart-felt thanks for their guidance in the world of silicon photonics and in silicon photonics around the world, from the University of Washington, to the University of Delaware to the National University of Singapore. My thanks to Dr. Patrick Lo and Dr. Andy Eu-

Jin Lim for supporting me during my attachment to the Institute of Microelectronics,

Singapore. Many thanks to Professor Keren Bergman for her guidance at Columbia

University, especially when the last 10% of the work takes 90% of the eﬀort.

Next, I would like to thank the members of the dissertation committee, Prof.

Keren Bergman, Dr. Michael Hochberg, Prof. Michal Lipson, Dr. Alexander Gaeta, and Dr. Peter Magill, for their time and feedback.

I would also like to thank Prof. Adeyeye Adekunle and Prof. Aaron Danner for their support at the National University of Singapore.

xvi I’ve been very fortunate to work in teams where collaboration and learning was the goal, as opposed to personal results. I’d particularly like to thank the senior students/collaborators, Ran Ding, Yang Liu, Matt Streshinsky and Noam Ophir who shared their seasoned understanding of both lab and life.

Many thanks as well to my academic collaborators along this journey. At the

University of Washington: Mike Gould, Jing Li, Alexander Spott, Li He. At the

University of Delaware: Nicholas Harris, Zhe Xuan, Christophe Galland, Yisu Yang,

Dennis Prather. At the National University of Singapore: Jingcheng Tao, Kang Tan,

Yufei Xing. At the Institute of Microelectronics: Xiaoguang Tu, Edward Koh Sing

Chee, Roger Tern, Chen Kok Kiong. At Elenion Technologies: Dominick Scordo,

Yi Zhang, Shuyu Yang, Ruizhi Shi, Yangjin Ma, Alexander Rylyakov, Rick Younce,

Hang Guan, Tal Galfsky, Saeed Fathololoumi, Alexandre Horth, Tam Huynh, Jose

Roman, Michael Caverley, Yaojia Chen, Amir Hanjani, Yury Dziashko, Kishore Pad- maraju, Raﬁd Sukkar, Harald Rohde, Robert Palmer, Guido Saathoﬀ, Torsten Wuth,

Marc Bohn, Abdelrahman Ahmed, Mostafa Ahmed, Christopher Williams, Daihyun

Lim, Abdellatif Elmoznine, Xiaoliang Zhu. At Columbia University: Qi Li, Dessislava

Nikolova, David Calhoun, Sebastien Rumley, Alexander Gazman, Nathan Abrams.

Elsewhere: Giovanni Capellini.

Finally, I’d like to thank my family who encouraged me every step of the way.

xvii This thesis is dedicated to my wife, my parents, my brother and my grandparents:

To my wife, Jae.

To my parents, Jeﬀ and Donna.

To my brother, Jeremy.

To my grandparents.

xviii Chapter One

Introduction

1.1 Optical Interconnects and the Drive for More

Data

Society depends on technology for an increasing number of applications (transporta- tion, payments, computation, entertainment) and these applications all require data communication to function efficiently. The purpose of data communication is to get information from one place to another, however, this process can take many different forms. The medium of communication can be electrical (e.g. telegraph, cable, USB, telephone), optical (e.g. fiber optic, free space optical, semaphore, heliograph), radio (e.g. cellular modems, satellite), acoustic (e.g. underwater acoustic), mechanical

(e.g. carrier pigeon, pony express, snail mail) or other. For modern, high-bandwidth, terrestrial communication links, the list of widely-used communications technologies narrows to just electrical or optical communication.

1 Figure 1.1: Plot of various historical technologies across time and their relative BL [1].

Beginning with the telegraph, electrical communication dominated short and long distance communication. The bit-rate, B, of the telegraph was a massive (for it’s time) 10 bits per second. This was a huge increase over previous long distance methods [1]. Typically, a communication method has a limited distance that the signal can go before it is too degraded to recover. The maximum length, L, to the receiver or next repeater is the key parameter for the performance of a communication system. Often, both the bit-rate and max length are critical requirements. Thus the bit-rate-length product, BL can be used as a standard performance metric to compare communication systems.

2 Electrical vs Optical Communication

It is necessary to ﬁrst examine the diﬀerences between electrical and optical communication to understand the available application spaces for each technology.

The fundamental diﬀerences between electrical and optical communication stem from the nature of the transport medium. Electrons have mass and charge and are also fermions which obey the Pauli exclusion principle (two or more identical fermions cannot occupy the same quantum state simultaneously). Photons are massless and chargeless and are also bosons, which can occupy the same quantum state (do not obey the Pauli Exclusion Principle).

There are a few immediate practical tradeoffs that result from the difference in medium of transit. The first is that length-dependent losses are much more significant for electrical communication channels. In an electrical channel, the resistive loss limits the bit-rate if no repeater is used to the following relation [7],

A B ≤ B (1.1) 0 L2

where B0 is a constant which depends on the resistive/inductive properties of the electrical line and can vary in the range of 1016 to 1018 bits/second, A is the cross sectional area of the channel and L is the length of the electrical channel.

On the other hand, optical channels are limited by a number of factors including optical loss, dispersion and high power non-linearity. However, optical communications systems, once developed, were able to quickly surpass the best electrical systems in term of BL, leading to their introduction for all longer distance communication.

3 Figure 1.2: Capacity-Distance performance of generations of optical communication technologies across the late 1900s [2].

Advances in Optical Communications

After telecommunication systems migrated to optical links in the mid-1970s, further optimization was needed to keep up with the exponential expansion of network data

ﬂow. Multiple generations of optical communication systems were developed to enable signiﬁcant increases in BL as shown in Figure 1.2.

The ﬁrst generation of optical systems used the early continuous wave lasers available at 0.85 µm. These systems were intermodal-dispersion-limited, if step-index

ﬁbers were used and loss-limited, if graded-index ﬁbers were used. The bit-rate limits of these two cases are given in Equation 1.2 and Equation 1.3, respectively [1].

B = c/2n∆L (1.2)

4 B = 2c/2n∆2L (1.3)

where c is the speed of light, n is the refractive index of the ﬁber (typically 1.46) and ∆ is the index contrast of the ﬁber (typically .01).

The second generation of optical systems moved to single mode ﬁbers at 1.3 µm to take advantage of the lower dispersion and loss. These systems were limited by dispersion-induced pulse broadening due to the sources’ large spectral width, with the bit-rate limit given in Equation 1.4

1 B = (1.4) 4|D|σλL

where D is the dispersion coeﬃcient and σλ is the root-mean-square (RMS) width of the source spectrum.

Third generation optical systems used ﬁber at 1.55 µm to take advantage of the low optical loss in this wavelength and use single mode lasers to reduce the problem of dispersion. The bit-rate limit for these systems is given in Equation 1.5

1 B ≤ 1/2 (1.5) 4L|β2|

2 where β2 is deﬁned by β2 = −λ D/2πc.

In the fourth and current generation, optical ampliﬁers and wavelength-division multiplexing (WDM), were used to drastically increase the amount of data that could be sent over a given ﬁber.

5 Figure 1.3: Global internet traﬃc by device type for 2017-2022 [3]

The ﬁfth-generation of optical telecommunication systems expands on the previous generation by extending the wavelength band of operation to add more channels and increases the bit-rate of each channel.

1.2 Next Generation Optical Links

Exponential Growth in Internet Traﬃc

The demand for optical data communications is expected to continue the exponential growth pattern of the past decades into the foreseeable future. Internet traﬃc is expected to continue its rapid growth driven by smartphones and other internet connected devices [3]. An internet data growth rate of 30% is expected through

2022 (see Figure 1.3).

The Rise of Datacenter Optics

Telecommunications is no longer the singular application for optical communications.

In the past decade, the datacenter has risen as a formidable deployer of optical interconnect links. The trend showing signiﬁcant optical bandwidth growth in the

6 Figure 1.4: Datacenter traﬃc growth through 2019. [4] datacenter is shown in Figure 1.4. Total traﬃc has risen by 73% in recent years and doesn’t show any signs of immediate slowdown.

Datacenter optical interconnects have diﬀerent requirements than telecommunication optics. Datacenters have higher numbers of shorter links and thus typically have more stringent requirements in terms of cost, thermal performance and size than telecommunications interconnects.

Requirements for next generation optical interconnects

Future generations of optical interconnects are expected to both improve performance in their current applications and as the replacement to shorter links, where electrical interconnects are currently in use. Electrical interconnects currently reach their performance limits around a BL of 100 Gbps · m as show in Figure 1.5(a). Optical

7 Figure 1.5: Penetration of optical links into communications. (a) Timeline of optical interconnect into digital application area by link distance and bandwidth. (b) Data- rate vs Distance for electrical and optical interconnects [5]. interconnects have the opportunity to be the viable technology in high-bandwidth, short distance link as shown in the upper right hand corner of Figure 1.5(b).

To compete with electrical interconnects for smaller links, optical interconnects must improve in terms of cost, density, and power consumption. A rough idea of the costs for a given distance are shown in Figure 1.5(a). Power consumption for short links is critical and is expected to move towards 1 pJ/bit and below [5,8].

8 Moving towards integrated optics

For early optical assemblies, each assembly is composed of several, independently fabricated optical components, each of which is optically aligned to the next. For example, a laser package would consist of a gain media, a wavelength tuning element a monitor photodiode and an output ﬁber. These components would be optically aligned with precisely-placed lenses between many of them.

In the quest for improved cost, density and power consumption required to compete for the next generation interconnect applications, integrating the functionality of many devices into a single chip that is produced via a semiconductor fab (integrated optics) is a promising approach. Fabricating all devices needed for a system and linking them optically in a single chip reduces cost, density and power all at once. Often, the packaging is an order of magnitude more expensive than the chips themselves [9]. Using a single chip results in lower packaging costs, especially when there are multiple sensitive optical alignments involved. Integrating optical functions also reduces package size and thus increases density. Reduced optical losses from fewer packaging interfaces and also can result in lower power consumption due to integration as well.

9 1.3 Silicon Photonics Devices and Platforms

The Case for Photonics in Silicon

Silicon has been used in electronic fabrication for decades and is fortunate to hold properties that make it useful for optics as well. The high crystal quality silicon and silicon dioxide used in standard CMOS processes can be used to achieve low-loss single-mode waveguides with loss of less than 1 dB/cm [10, 11]. Additional passive device functionality can be fabricated with the same silicon layers including grating couplers [12], polarization splitters and rotators [13–15], and WDM components [16–

18]. The other key components for silicon photonics systems are the photodetector, modulator and laser.

Photodetector

Silicon and it’s relatives silicon dioxide and silicon nitride have large bandgaps which are convenient for designing low-loss waveguides, but are poor at absorbing light for use in photodetection. The most common type of photodetector currently used in silicon photonics is the germanium photodetector. Germanium is a companion to silicon in Group IV of the periodic table and is already in use in CMOS fabs as an enhancement to transistors [19]. Germanium photodetectors are typically doped as a p-i-n junction to apply an electric ﬁeld either in the horizontal or vertical orientations

[20–27].

10 Modulator

Modulators are needed to impart a signal onto the optical carrier wave. Multiple techniques exist to create modulation in silicon. The thermal-optic eﬀect is eﬃcient and gives large phase swings, but is typically too slow for modulating signals [28].

The Franz-Keydelsh or it’s close relative, the quantum-confined Stark effect, are efficient and high speed, but require operation at the band edge and thus result in a limited range of wavelengths, limited extinction and higher loss [29–31]. The plasma- dispersion effect is the most common for high-speed, tunable wavelength applications, but is relatively weak and requires a significant modulation length to achieve full modulation [27,32]. Modulators can also come in different shapes and sizes from the compact ring modulator [33–35] to the more standard Mach-Zehnder Interferometer

[36,37].

Transistor

While silicon photonics uses shared facilities with CMOS electronics, transistors are not necessarily part of a silicon photonics platform. However, there have been many examples of monolithic integration of transistors and photonics onto the same wafer, often at the expense of one type of device [38,39].

Laser

A critical limitation of silicon relative to other platforms is the lack of a built-in light source. Eﬀort has been made to create lasers both in silicon [40, 41] and germanium

11 [42, 43], however, these lasers struggle to be eﬃcient. The other typical strategy to add optical gain to silicon photonics is by bonding on III-V material, either by wafer/chiplet bonding that is then post-processed [44–46] or by aligning and bonding a fully formed III-V chip [47–49].

1.4 Scope of Thesis

This thesis is derived from the author’s work which has been published in peer- reviewed journals or conference proceedings where the author of this thesis is a co- author of the previously published work.

The goal of this research was to improve the state-of-the-art systems for optical communication. In order to achieve high performance optical communication systems, work needed to ﬁrst be done to improve the building blocks. Then, additional capabilities needed to be added to enhance the platform beyond the standard devices. Finally, the pieces are combined into a complete optical system. A sketch of the hierarchical ﬂow of this thesis are shown in Figure 1.6.

Part I of this thesis is the design and improvement of building block photonic devices into a fully-capable silicon photonics platform. Chapter 2 discusses research in enhancing photodetector bandwidth by tuning the electrical parameters of the photodetector circuit. Chapter 3 covers research on modulators, which were shown to work at 50 Gbps. Chapter 4 combines the photodetector and modulator work, demonstrating the capabilities of a silicon photonic platform to scale to large numbers of parallel optical channel with an aggregate data throughput of 2.4 Tbps (48x50

12 Figure 1.6: Diagram showing the thesis hierarchy.

Gbps).

Part II contains results on components that compliment the standard silicon photonics platform. Chapter 5 shows work on a transistor that can be integrated into a silicon photonics platform without process modiﬁcation, that allows more sophisticated control of the photonics. Chapter 6 demonstrates the integration of a fully tunable laser into the silicon photonics platform, demonstrating that the laser is capable of supporting a coherent optical link.

Finally, Part III puts all of the previous work together to show how the improved components and platform can be built into a state of the art optical transceiver.

Chapter 7 demonstrates this high-speed silicon photonics transceiver consisting of a silicon photonics chip with modulators and photodetectors. The silicon photonics chip is co-packaged with drivers and TIAs into a compact coherent engine. The coherent engine is powered by a silicon photonic based tunable laser and the full system is demonstrated to work at 64 GBaud QPSK.

13 Part I

Silicon Photonics: Devices and

Platform

14 Chapter Two

Germanium Photodetector with 60

GHz Bandwidth Using Inductive

Gain Peaking

High receiver datarate is critical for high-speed optical links and is governed by the

Nyquist rate (B = 2F log2M) where B is the bitrate, F is the bandwidth frequency and M is the number of signal levels. From the Nyquist rate equation, bandwidth of the photodetector is directly proportional to datarate although other factors often play a role. This chapter covers my work optimizing the bandwidth of photodetectors by adding, modeling and tuning on chip electrical-components. In this work, the bandwidth enhancement techniques led to a doubling of the photodetector bandwidth from 30 GHz to 67 GHz. This was the highest reported silicon photonics photodetector bandwidth at the time of publication (2013). I performed the device measurement,

15 parameter ﬁtting and analysis. Mike Gould did the device design and layout based on his previous published work [44]. Yisu Yang and Zhe Xuan assisted with additional measurements. This work was published in Optics Express.

A. Novack, M. Gould, Y. Yang, Z. Xuan, M. Streshinsky, Y. Liu, G. Capellini,

A. E.-J. Lim, G.-Q. Lo, T. Baehr-Jones et al., “Germanium photodetector with 60

GHz bandwidth using inductive gain peaking,” Optics express, vol. 21, no. 23, pp.

28 387–28 393, 2013

2.1 Introduction

Silicon has in the past decade become the subject of intense interest for use in photonics. There are a number of advantages to using silicon as a platform for photonics including the high degree of confinement that silicon offers, the ability to leverage the fabrication knowledge and investments developed by the CMOS electronics industry and the possibility of integrating many components into complex photonic integrated circuits (PICs) [50]. Recently, the silicon photonics community has begun to move from working on individual devices to creating more complex systems [51]. However, continued effort into improving the performance of individual devices is required to ensure stability and raise the performance of such systems.

A critical component of the silicon photonics infrastructure is the germanium photodiode. Germanium is widely used as the detector absorption element due to its ability to absorb light at communications wavelengths and its CMOS compatibility.

Techniques have been developed to grow germanium epitaxially on a silicon substrate

16 with few defects [52, 53]. However the relatively low absorption coeﬃcient of germanium necessitates larger detectors to obtain reasonable responsivity. The increased area increases the capacitance of the detector junction, which correspondingly reduces the detector bandwidth. Signiﬁcant work has been done to minimize this capacitance and develop high-speed waveguide-coupled germanium photodetectors [54–57]. By optimizing both the detector fabrication and geometry, detector bandwidth above

100 GHz has been reported [58]. However, for integrated photonics in silicon it is often not practical to optimize the process solely to lower detector capacitance. Gain peaking is a technique that has been used in the design of electronics systems such as CMOS amplifiers [59, 60] and photoreceiver amplification [61–63]. However, the authors are unaware of any previous demonstration of detector peaking that has been integrated directly on a silicon photonics chip. We have demonstrated that it is possible to significantly increase detector bandwidth using metal layers that are commonly available in CMOS-compatible silicon photonics processes [64].

2.2 Baseline Detector Modeling

Modeling of detectors can involve complex models and simulations [65, 66]. Due to the small width of the intrinsic region of the germanium on silicon, waveguide-coupled detectors, the RC constant is the limiting factor in the bandwidth and transit time eﬀects can be largely ignored [67,68]. The RC circuit often gives a reasonably accurate model for the response of a photodetector. We denote Rload as the load resistance, Cpd as the detector capacitance and Rpd as the detector resistance. The cutoﬀ frequency

17 for this simple model is given by Equation 2.1.

1 fc = (2.1) 2πCpd (Rload + Rpd)

We take the bandwidth denoted by fc to be the 3 dB point at which the pho- √ tocurrent has been reduced by a factor of 2. The load resistance can be considered either the input to a transimpedance ampliﬁer (TIA) or another type of 50-Ω load.

It is possible to increase the bandwidth by reducing either the detector capacitance or resistance. The detector capacitance scales with the area of the detector and is dependent on a number of variables such as the detector’s intrinsic width and the doping concentrations. While the capacitance can be estimated analytically, it is more accurate to measure the capacitance for a given process. Using a number of test structures of diﬀerent areas, the capacitance per unit area was measured as a function of voltage as seen in Figure 2.1.

In this work, the detectors were 8 um wide and 10 um long at the base with a

4x7.6 um junction for a junction capacitance of about 15 fF. As the detector area is minimized and the bias voltage increased, the capacitance of the photodetector is decreased and other parasitics in the circuit play a larger role. The largest of these parasitics is the capacitance due to the contact pads. The pads used in this study are 60 um x 60 um with a 100 um pitch and have a total capacitance of about 13 fF calculated by both simulation (Ansoft HFSS) and direct measurement. With smaller detectors, the parasitic pad capacitance is on the order of the detector capacitance and must be accounted for in the detector circuit model as a load parallel to the load

18 Figure 2.1: Junction capacitance per unit area as a function of reverse bias voltage (positive voltage on graph is reverse bias). The curve was measured by determining the capacitance from the detector S11 parameter (as seen in inset) using a number of test structures of diﬀerent areas.

resistance (Cload).

2.3 Gain-peaked Detector Modeling

It has previously been shown that adding an inductor to a photodetector circuit will act to increase the 3-dB bandwidth by peaking the EO response [69]. In order to evaluate how the detector circuit will respond to the addition of an inductor, we introduce another circuit model shown in Figure 2.2.

In this model, a non-ideal inductor element [61,62] has been added that contains an inductance Lind and a series resistance Rind in parallel with a capacitance Cind.

19 Figure 2.2: Gain peaking circuit model. The addition of an inductor is used to peak the frequency response of the photodetector.

The transfer function of this circuit is given by,

Vload(s) −1 H(s) = = Zload · [Rload · (Cpd · s · (Rpd + Zind + Zload)) + 1] (2.2) Ipd(s)

s = j2πf (2.3)

where the impedances Zind and Zload are given by

1 Zind = (2.4) Cpk · s + 1/ (Lpk · s + Rpk)

20 Figure 2.3: Optical micrograph of the gain peaked photodetector using the 360 pH inductor. The inductor is approximately 100 um x 100 um in size.

1 Zload = (2.5) Cload · s + 1/Rload

Two diﬀerent inductors were designed for use in gain peaking. Both inductors utilize two-loop square spiral geometries built using 1.5-um thick aluminum traces with 10-um width. The majority of the loop uses the thick top metal layer while only the metal crossing occurs in the thinner lower metal to minimize resistance. The small inductor (see Figure 2.3) used an inner loop width of 20 um and an outer loop width of 50 um while the large inductor used a 50 um inner loop and an 80 um outer loop.

21 Figure 2.4: OpSIS-IME platform schematic. The detector is built using germanium grown epitaxially on unetched silicon. The inductors use the two metal layers. The lower via layer provides contact to the germanium. The anode of the detector is not shown.

Three-dimensional electromagnetic simulation was done on these inductor geometries using a commercial software package (Ansoft HFSS). The simulations showed that the small inductor had about 360 pH of inductance and 9.7 fF self-capacitance, while the large inductor had 580 pH of inductance and 19.8 fF self-capacitance. Both inductor elements had a relatively low series resistance of about 1Ω/GHz1/2.

2.4 Fabrication

The detectors were fabricated at the Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) as part of the OpSIS-IME MPW service [70]. The platform uses a 220 nm thick SOI wafer with

2-um buried oxide (BOX) as seen in Figure 2.4. A 60 nm silicon etch is used to deﬁne the grating coupler layer while a 220 nm silicon etch is used to build the 500 nm waveguides.

The detector was built using selectively grown epitaxial germanium on top of the silicon. The germanium layer was 500 nm thick and had an angled sidewall. A 90

22 Figure 2.5: Photodetector cross section showing the detector p-i-n junction and metal contacts. The anode and cathode are shown. nm slab layer was also used to maximize the evanescent coupling between the silicon and the germanium. The silicon beneath the germanium was doped with boron to form the p-type side of the junction. The top of the germanium was implanted with phosphorous to form the n-type side of the p-i- n junction as seen in Figure 2.5.

A lower level of via was fabricated to contact both the n-type germanium as well as the p- type silicon. The ﬁrst metal layer was then added, followed by an additional layer of vias and the second metal layer. An oxide cladding was deposited and opened above the metal pads that were used for probing the detector.

2.5 Experimental Results

Testing conﬁguration

The photodetectors were tested using a ﬁber array with polarization maintaining

(PM) fiber to couple light on and off chip using a pair of grating couplers. A well- calibrated y-junction split the light path to go both to the detector and to an output grating coupler. This configuration allowed for accurate alignment to the grating couplers and precise calculation of the power incident on the detector. For the detector

S-parameter measurement, a vector network analyzer was used to drive a high-speed

23 lithium niobate modulator and measure the detectors electrical response. The frequency response of the modulator was calibrated using an ultra-high-speed (70 GHz), commercial photodetector and normalized out of the response of the detector under test. A GSG microprobe was used to contact the metal pads of the detector.

Device Performance

Three detectors were tested to determine the eﬃcacy of the gain peaking technique using the small inductor and the large inductor as well as a detector with no inductor to provide a baseline. Using a 2V reverse bias, DC responsivity and dark current were measured to be 0.75 A/W and 3 uA respectively with small variations between detectors due to fabrication-coupler alignment and fabrication variation. The approximate photodetector resistance (Rpd) was measured by ﬁtting the IV curve of the detector at a forward bias of around 1V.

An EDFA was used to increase the signal to noise ratio and allow measurement of the detector response up to a frequency of 67 GHz as seen in Figure 2.6. From the frequency response of these detectors, it is evident that gain peaking does have a significant effect at frequencies beginning around 10 GHz. The detector with no added inductance exhibits the lowest 3 dB bandwidth of around 30 GHz. The detector with the large, 580 pH inductor shows a large response peak near 35 GHz followed by a steep drop in response and a 3 dB bandwidth near 50 GHz. The detector with the small, 360 pH inductance on the other hand has less of an extreme peak, but has a higher 3 dB bandwidth near 60 GHz. A least-squares circuit model fit was obtained

24 Figure 2.6: a) EO S21 and b) detector S11 response at 2V reverse bias of the unpeaked detector as well as the detectors with both small and large inductors. Points are from data, colored lines are smoothed data and black dashed lines are ﬁts to the circuit model.

by using the simulated and measured detector parameters with the EO S21 response of Eq. (2). The ﬁt parameters are shown in Table 1. A few of the ﬁt values such as

Cpd vary between detectors. This may be due to either fabrication variation of the p-i-n junction or an inexact ﬁt of the detector response.

The above ﬁts of EO S21 are fairly accurate in both the frequency of the peaking and magnitude of the peaking. However, there is a small discrepancy in the EO S21

ﬁt at lower frequencies that is likely due to measurement error.

Table 2.1: Fit and expected photodetector parameters. For values that vary between the detectors, three measurements are shown for the unpeaked/small inductance/large inductance detectors.

Parameter Fit Value Expected Value m Rpd 140 Ohms 125 Ohms m Cload 13 fF 13 fF m Cpd 17/14/15 fF 15 fF s Lind 0/360/580 pH 0/360/580 pH s Cind 1/8/10 fF 0/9/20 fF 1/2 s Rind 0 Ohms 1.2 Ω/GHz mParameter measured directly from photodetectors sParameter found via simulation

25 Figure 2.7: a) Phase delay of EO S2S211 normalized to the unpeaked detector. b) Group delay variation of EO S21 calculated from the circuit model ﬁt to show eﬀective group delay variation of measured data.

The phase delay is calculated from the model and closely ﬁts the measured phase as seen in Figure 2.7(a). The addition of an inductor increases the group delay variation as seen in Figure 2.7(b) from -1.5 ps at 40 GHz for the unpeaked detector to 2.1 ps and 12.3 ps at 40 GHz for the small inductor and large inductor respectively. The group delay of the large inductor detector is approaching the 25 ps period at 40 GHz, which may negatively impact digital signal quality. We do not expect a signiﬁcant increase in detector noise from the inductor as shown in [69].

2.6 Conclusion

We have shown experimental evidence that the bandwidth of germanium on silicon can be signiﬁcantly enhanced with the addition of a peaking inductor. The inductor can be fabricated with metal processes that currently exist on CMOS-compatible integrated photonics platforms. Using a spiral inductor of 360 pH, the bandwidth of a non-peaked detector was enhanced from 30 GHz to 60 GHz.

26 Chapter Three

Low Power 50 Gb/s Silicon

Traveling Wave Mach-Zehnder

Modulator Near 1300 nm

This chapter covers my work on high-speed modulators. Modulator power and bit rate are critical components of high-speed links. In this work, optimization of the modulator led to a data rate of 50 Gbps and a modulator power consumption of

450 fJ/bit. This was the fastest reported silicon photonics modulator data rate in the

O-band at the time of publication (2013). This work was led by Matthew Streshin- sky. I assisted with device measurement and analysis. Yang Liu and Ran Ding did the dopant design and transmission line design. This work was published in Optics

27 Express.

M. Streshinsky, R. Ding, Y. Liu, A. Novack, Y. Yang, Y. Ma, X. Tu, E. K. S. Chee,

A. E.-J. Lim, P. G.-Q. Lo et al., “Low power 50 Gb/s silicon traveling wave Mach-

Zehnder modulator near 1300 nm,” Optics express, vol. 21, no. 25, pp. 30 350–30 357,

2013

3.1 Introduction

Mach-Zehnder silicon modulators are attractive for data communications due to their relative thermal insensitivity and wide optical bandwidth [71]. Furthermore, by fabricating these devices on a silicon platform, highly complex and integrated systems are possible [72, 73]. Signiﬁcant progress has been made for Mach Zehnder modulators operating near 1550 nm, with devices that have been demonstrated to be suitable for high speed digital [74,75], low drive voltage [76,77], and analog applications [78,79].

However, there have been relatively few presentations of silicon modulators operating near 1300 nm with similar performance. Most recently, Fujikata, et al. present a

Mach-Zehnder modulator using a MOS junction to achieve 25 Gbps performance for light near 1.3 µm [80].

The wavelength band near 1300 nm is attractive for telecommunication systems, such as upstream/downstream communication in passive optical networks or working beyond the dispersion limit at long transmission distances in high-speed communications [81]. While many hybrid silicon modulators have also been demonstrated in this band [82–84], these geometries are not currently compatible with standard

28 silicon photonic platforms. We present a 3-mm silicon traveling wave Mach-Zehnder modulator fabricated in a silicon-on-insulator (SOI) platform capable of operating at

50 Gb/s. Using a diﬀerential 1.5 Vpp drive voltage at a 0 V reverse bias, the device achieves an energy eﬃciency of 450 fJ/bit.

3.2 Traveling Wave Design

The device presented here is similar in architecture to that of [76] with several key modiﬁcations. First, the waveguides are scaled from 500 nm to 420 nm to support primarily the TE0 mode in the 1300 nm band and optimally overlap the optical mode with the pn junction. Secondly, intermediate p + and n + implants are used to decrease series resistance. The new junction proﬁle is shown in Figure 3.1. This device also utilizes components in the OpSIS PDK at 1.3 µm, such as a compact Y- junction and grating coupler [85]. Finally, thermal phase tuners are integrated into each arm of the Mach-Zehnder interferometer.

The intermediate dopants are found to result in drastic improvements in performance by significantly reducing junction series resistance, Rpn. There is a fundamental tradeoff in the design of the pn junction between bandwidth, modulation efficiency,

Vπ, and optical loss. From the derivations in [86], in a traveling wave modulator with well-matched RF and optical modes, the bandwidth is limited by RF attenuation, αrf.

Furthermore, the electrooptic 3-dB bandwidth is related to the RF 6.4 dB bandwidth by αrf (f3dB) · Ldev = 6.4dB, where Ldev is the length of the device.

29 Figure 3.1: (a) Micrograph of the device. (b) Simpliﬁed cross sectional diagram of the phase shifter, not to scale.

From the derivation in [87], RF attenuation can be expressed as:

αrf (f) = αrf,metal + αrf,Si (3.1)

2 2 2 1 RTL(f) 2π f RpnCpnZdev αrf (f) ≈ + 2 (3.2) 2 Zdev 1 + (2πRpnCpnf)

where f is frequency, Cpn is the junction capacitance, Zdev is the device characteristic impedance, and RTL is the transmission line series resistance. In the case where losses due to the shunt conductance from the pn junction dominate, the above relationship indicates that the electrooptic 3-dB bandwidth is proportional

2 −1/2 to (LdevRpnCpn) . Thus, it is clearly advantageous to reduce Rpn to enhance band-

30 width. While the simplest method to reduce Rpn is to reduce the clearance between the waveguide and high dopant concentration regions, this results in a tradeoﬀ between insertion loss and bandwidth. Instead, by introducing intermediate dopants, we are able to primarily sacriﬁce process complexity for bandwidth. We have chosen the dopant exclusions such that the simulated waveguide loss is not expected to increase from the geometry of what is reported in [76].

The implant layout as reported in [76] resulted in 1.6 Ω cm series resistance in the partially etched silicon due to sheet resistance from the n-type and p-type silicon.

From simulation, the sheet resistances of the p+ and n+ intermediate dopants in partially etched silicon are expected to be 3.8 kΩ/ and 1.5 kΩ/, respectively. With the junction as depicted in Figure 3.1(b), this corresponds to a series resistance in the partially etched silicon of 0.65 Ω cm.

Using the scaling proportionalities deﬁned above, this reduction in series resistance should improve the previous 3-dB bandwidth of 18.5 GHz for the 3 mm long device to approximately 29 GHz.

The transmission line is designed to have a 33 Ω impedance when loaded with the pn junction. Each arm of the Mach-Zehnder consists of a 3 mm long lateral pn- junction phase shifter. To insure the current travels through the metal rather than laterally through the silicon, each 10 µm of phase shifter length is broken into a 9.2 µm length with the pn-junction followed by 0.8 µm of undoped silicon. The transmission lines are driven by a set of GSGSG input pads and terminated by a set of GSSGSSG output pads. Additionally, a 250 µm long thermal phase tuner is also appended on each arm of the interferometer after the pn junction phase shifters to enable the bias

31 point to be appropriately set. Resistors for the phase tuners are integrated into the waveguides by overlaying the n-type implant with the waveguide.

3.3 Fabrication

Fabrication occurred at the Institute of Microelectronics (IME), A*STAR, Singa- pore [88] in a multi-project wafer run through the OpSIS foundry service [89]. The fabrication process follows the ﬂow reported in [90] and in all cases 248 nm pho- tolithography is utilized. The starting material is a 220 nm top-silicon thickness SOI wafer with a 2 µm thick buried oxide layer and a high-resistivity 750 Ω cm silicon substrate, necessary for high-speed RF performance [91]. First, a 60 nm anisotropic dry etch is applied for the grating couplers, followed by additional etch steps to deﬁne the 90 nm slab layer. The p + + , p + , p, n, n + , and n + + implants were performed next on the exposed silicon before oxide deposition. The peak doping densities for the p + , p, n, and n + layers were chosen to be 2 × 1018 cm−3, 7 × 1017 cm−3,

5 × 1017 cm−3, 3 × 1018 cm−3, respectively. The implants were followed by a rapid thermal anneal at 1030 ◦C for 5 seconds. Finally, two layers of aluminum vias and interconnects were formed.

It should be noted that although this device could theoretically be designed and fabricated with only a single layer of metal, due to inclusion in a multi-project wafer shuttle run through OpSIS, both of the oﬀered metal layers were utilized. Thus, the thicker top aluminum layer (M2) is used for the transmission lines and the via-stack from M2 to silicon is determined by design rules as well as via and contact resistance

32 considerations.

3.4 Device Characterization

DC Measurements

Light is coupled onto and oﬀ of the chip via grating couplers. A pair of grating couplers near the device is used to extract the insertion loss of the testing apparatus.

Device insertion loss is then measured as the diﬀerence between the response of the test loop with no Mach-Zehnder modulator and the response of the loop with the device. The total insertion loss of the device is measured to be 5.5 dB. Of this 5.5 dB, 1.6 dB excess loss is due to two Y-Junctions, 0.1 dB is due to tapers from ridge to rib waveguides, 0.16 dB is due to the thermal tuner, and the remaining 3.34 dB is due to the 3 mm long phase shifter. Within a 2π phase shift in the thermal tuners, the variation in thermal tuner loss as a function of applied phase shift is insigniﬁcant relative to the loss due to the implanted silicon.

The Mach-Zehnder interferometer is intentionally unbalanced by 100 µm to enable easy testing by tuning the input wavelength. To test the DC performance of the phase shifters, wavelength sweeps are measured at various reverse bias voltages. Due to the unbalanced interferometer, the phase shift may be tracked by observing the shift in null points of the fringes in the spectrum. A typical spectrum at diﬀerent DC bias voltages is shown in Figure 3.2(a) and the phase shift versus reverse bias is shown in

Figure 3.2(b). The small-signal VπL between 0 V and 1 V reverse bias is 2.64 V cm

33 Figure 3.2: (a) Typical spectrum at various reverse biases. (b) Phase shift vs reverse bias of typical phase shifter. A small-signal Vπ is measured to be 8.8 and 8.1 V for the bottom and top arms, respectively, between 0 V and 1 V reverse bias. (c) C-V curve of the pn junction of the phase shifter. (d) Measured I-V curve of the device without RF termination. and 2.43 V cm for the bottom and top arm, respectively. Additionally, since the device is intended to operate with no or low bias, C-V and I-V curves are presented in Figure 3.2(c) and Figure 3.2(d).

The cross section of the thermal tuner is shown in Figure 3.3(a). The n-type doped waveguide core acts as a heater and is measured to have a resistance of approximately

42 Ω. The shift in null point is also used to test the eﬃciency of these thermal phase shifters. A constant DC bias is applied to the resistor and the power required to achieve a π-phase shift is measured to be 27 mW. The phase shift versus power into

34 Figure 3.3: (a) Simplified cross section of the thermal phase tuner. (b) Tuning efficiency of the thermal tuner. The power required to shift the wavelength by π is measured to be 27 mW. the resistor is shown in Figure 3.3(b). Based on the primarily linear dependence between phase shift and power, the total phase shift is dominated by thermal effects, rather than carrier refraction due to injected carriers.

High Speed Characterization

The high speed performance of the device is characterized by an electrooptic S- parameter sweep, and a typical trace is shown in Figure 3.4(a) and Figure 3.4(b).

In order to test the bandwidth, the wavelength was biased at the optical -3 dB point in the spectrum. An Agilent N4373C Lightwave Component Analyzer and a Newport

1414 photodetector were used to test the device. Each arm was driven individually with a GSGSG probe, where the arm not under test was connected to a 50 Ω termination resistor. A GSSGSSG probe is used to terminate the device, where each signal path is connected to two 50 Ω termination resistors in parallel, resulting in an equivalent 25 Ω termination impedance. Terminating with a lower impedance suppresses modulation depth at low speeds, which then improves operation bandwidth [92]. The bandwidth is shown in Figure 3.4(a), where the electrooptic response of the photode-

35 Figure 3.4: (a) Electrooptic S21 of each arm at 0 V reverse bias. Input light is set to the -3 dB point in the optical spectrum. (b) S11 of the device.

tector alone is removed from the measurement EO S21. Although there appears to be ripples on the order of 2 dB in the S21 of the bottom arm that fall below the -3dB point, as will be shown below, this does not prevent the device from achieving 50

Gbps performance.

To demonstrate high speed digital performance, a 50 Gbps PRBS signal is driven through the device. An Anritsu MP1822A Pattern Generator is used to generate a diﬀerential 215-1 PRBS signal, which is then applied to the input pads using a GSGSG

RF probe. Light at the -3dB point, in this case 1301.91 nm, is input into the device and then received by a Picometrix AD-10ir photodetector connected through a DC

36 block to an Agilent Digital Communications Analyzer (DCA). Although the received electrical signal is AC coupled, the extinction ratio may still be extracted. Knowing the responsivity of the photodetector, the DC optical power into the photodetector

(Pavg) can be recorded through a current monitor on the AD-10ir photoreceiver.

Similarly, the peak-to-peak voltage amplitude measured by the DCA can be converted to the peak-to-peak optical power, Pp-p. If we then assume that the PRBS signal consists of an even distribution of “1” and “0” bits, the extinction ratio is calculated as:

Pavg + Pp−p/2 ER = 10log10 (3.3) Pavg − Pp−p/2

Also of interest is the “1” bit excess loss of the device, deﬁned as the additional loss incurred for output representing a digital “1” bit compared to the maximum transmission. This loss is calculated based on the optical bias point, Pbias, as:

Pavg + Pp−p/2 1 bit loss = Pbias + 10log10 (3.4) Pavg

We demonstrate eye diagrams using three different drive voltage conditions. Driv- ing with a signal amplitude of 1.5 Vpp and 0 V bias yields an energy efficiency of 450 fJ/bit, extinction ratio of 3.4 dB, and “1” bit loss of 1.6 dB, shown in Figure 3.5(a); driving with a signal amplitude of 2.0 Vpp and 0 V bias yields an energy efficiency of 800 fJ/bit, extinction ratio of 4.6 dB, and “1” bit loss of 1.3 dB, shown in Fig- ure 3.5(b); and by driving with a 3.0 Vpp signal with a 1.0 V reverse bias we achieve an energy efficiency of 3.4 pJ/bit, extinction ratio of 4.2 dB, and “1” bit loss of 1.4

37 Figure 3.5: 50 Gbps eye diagrams using a diﬀerential pseudorandom 215-1 signal. (a) 1.5 Vpp amplitude and 0 V reverse bias. (b) 2.0 Vpp amplitude and 0 V reverse bias. (c) 3.0 Vpp amplitude and 1.0 V reverse bias. In all eye diagrams, input light is biased at the -3 dB optical point, 1301.91 nm. dB, shown in Figure 3.5(c). Note that with an equivalent 25 Ω termination resistance, energy per bit is calculated by:

N (V /2)2 V 2 Energy/bit = input pp + bias (3.5) B 50Ω 25Ω

where Ninput is the number of electrical inputs and B is the data rate in bits per second. Since the PRBS signal generator uses a 50 Ω output impedance, this value is used for estimating power consumption. Note that since the transmission line impedance is 33 Ω, the on-chip drive voltage is less than the drive voltage that is reported here. A comparison of the performance of our modulator to other Mach-

Zehnder modulators, including results at 1550 nm, is shown in Table 1.

3.5 Conclusion

Since the wavelength band near 1300 nm is important for many telecommunications systems, silicon devices that can modulate light in this band are desirable. We present the ﬁrst silicon modulator to operate at 50 Gb/s near 1300 nm. We measure a small-

38 signal VπL as low as 2.43 V-cm, as well as demonstrate a thermal phase tuner with tuning eﬃciency 27 mW/π. By introducing intermediate dopants in the phase shifter to reduce series resistance we are able to improve bandwidth while maintaining a small

VπL and low insertion loss. We have demonstrated a 50 Gb/s eye diagram using a diﬀerential 1.5 Vpp signal at a 0 V reverse bias, and achieved a power consumption of 450 fJ/bit.

39 Table 3.1: Comparison to Other Traveling-Wave Modulators in Silicon at 40 Gbps and Above.

PN junction type, Driving Data rate, Extinction Electro- VπL at Phase DC Phase Conﬁguration, Wave- voltage Energy- Ratio, “1” bit optic bias (V- shifter Shifter In- length and biasa per-bitb loss (dB) Bandwidth cm) length sertion loss (GHz) (mm) (dB)

Vertical pn, single- 6.0 Vpp, -3 40 Gb/s, ER: 1.1 dB, 30 4 1 1.8 arm, 1550 nm [93] V bias 4.5 pJ/bit Loss: NA Lateral pn, single- 6.5 Vpp, -5 60 Gb/s, ER: 3.6 dB, 28 2.05 0.75 1.2 arm, 1550 nm [75] V bias 3.5 pJ/bit Loss: 1.6 dB Wrapped pn single- 6.0 Vpp, -3 40 Gb/s, ER: 6.5 dB, NA 11 1.35 7.7 arm, 1550 nm [94] V bias 4.5 pJ/bit Loss: 10 dB Lateral pn, single- 6.5 Vpp, -4 50 Gb/s, ER: 3.1 dB, NA 2.8 1 3.2 arm, 1550 nm [95] V bias 4.2 pJ/bit Loss: 3.2 dB Pipin diode, single- 7.0 Vpp, 40 Gb/s, ER: 6.6 dB, 20 3.5 4.7 4.7 arm, 1550 nm [96] NA bias 6.1 pJ/bit Loss: 0 dB Pipin diode, single- 7.0 Vpp, 40 Gb/s, ER: 3.2 dB, 40 3.5 0.95 0.95 arm, 1550 nm [96] NA bias 6.1 pJ/bit Loss: 2 dB Lateral pn, single- 4.0 Vpp, 40 Gb/s, 2 ER: 7 dB, NA 2.7 3.5 15.75 arm, 1550 nm [97] NA bias pJ/bit Loss: 0 dB Lateral pn, single- 6.5 Vpp, 40 Gb/s, ER: 3.5 dB, NA 2.7 1 4.5 arm, 1550 nm [97] NA bias 5.2 pJ/bit Loss: 0 dB c Lateral pn, single- 7.0 Vpp, -5 50 Gb/s, ER: 5.56 dB, 25.6 2.67 4 4.1 arm, 1550 nm [74] V bias 4.9 pJ/bit Loss: NA Lateral pn, single- 5.0 Vpp, -5 40 Gb/s, ER: 6 dB, NA 2.08 4 4.8 drive push-pull, 1550 V bias 3.1 pJ/bit Loss: NAe nm [98] Lateral pn, single- 5.0 Vpp, -6 50 Gb/s, ER: 4.7 dB, NA 2.4 2 2.4 drive push-pull, 1550 V bias 2.5 pJ/bit Loss: NAf nm [98] d Lateral pn, two-arm 0.36 Vpp, 0 40 Gb/s, ER: 0.92 dB, 20 0.75 2 4.5 differential drive, 1550 V bias 0.036 Loss: 0 dB nm [77] pJ/bit This work Lateral pn, 1.5 Vpp, 0 50Gb/s, ER: 3.4 dB, 30 2.43/2.64 3 3.34 two-arm differential V bias 0.45 pJ/bit Loss: 1.6 dB drive, 1310 nm aBias voltage for eye-diagram and/or bandwidth measurement. bPossible DC power consumption at the termination resistor is excluded for [93], [95], and [96]. cMeasurement plot in [74] suggests that EO response rolls off about 5 dB at this frequency. Other numbers in this column are 3 dB bandwidth. d EO S21 bandwidth in [77] is simulated from a measured RF S21 trace of the device transmission line eLight is biased at the optical -3 dB point, though “1” bit loss is not reported fThe authors of [98] report that the measurement was performed “with a wavelength close to the minimum transmission point.”

40 Chapter Four

Silicon Parallel Single Mode 48 x

50 Gb/s Modulator and

Photodetector Array

This chapter covers my work scaling photonic designs to large number of high-speed parallel channels. The modulator and detector array consisted of 48 channels, each tested to operate at 50 Gbps. The aggregate bandwidth of this chip was far larger than any previously published (2014). Matt Streshinsky led the design, layout, and test. I contributed to design, fabrication and test. This work was published in the

Journal of Lightwave Technology.

M. Streshinsky, A. Novack, R. Ding, Y. Liu, A. E.-J. Lim, G.-Q. Lo, T. Baehr-

Jones, and M. Hochberg, “Silicon parallel single mode 48× 50 Gb/s modulator and photodetector array,” Journal of Lightwave Technology, vol. 32, no. 22, pp. 3768–3775,

41 2014

4.1 Introduction

Silicon photonics is a promising platform for low-cost and high-speed optical interconnects [100, 101]. Particularly, the monolithic integration of high-speed photodetectors [102–104], modulators [105–107], and low-loss passive components [108–111] enables the design of large-scale integrated photonic circuits. As consumer demand for services such as streaming media and cloud computing rise, there is greater need for high complexity and low cost optical transceiver technologies.

Within modern data centers the computing infrastructure to support this demand may extend between racks or even between buildings and will require integrating more communications ports into the same rack space with reaches of up to 2 km [112,113].

This level of networking scale will necessitate cost effective many-channel links using single mode fiber at aggregate bandwidths of terabit/s and beyond [114]. While silicon is not the best platform for every device in such a link, several silicon devices are already competitive with best-in-class performance [103,115]. Moreover, a single silicon photonic chip can integrate hundreds to thousands of what may formerly have been discrete components. Additionally, using glass arrays of fiber or multi-core

ﬁber interfaces, tens to hundreds of optical I/O are possible [116]. Thus, ultrahigh- throughput systems can be built up on a single silicon chip.

A key unexplored question is whether it is, in fact, possible to obtain high yields across numerous channels on a silicon photonics chip, thus realizing the potential of

42 the technology. The primary challenges in achieving this level of performance are the development of a well-characterized fabrication process and a library of stable and fabrication-tolerant devices. To address the former, there are several silicon platforms available to the public and in private industry, which include: Luxtera’s

130 nm Freescale platform, Mellanox’s 150 mm foundry, and MPW services through ePIXfab and OpSIS. In collaboration with the OpSIS-IME foundry service, we have access to a full suite of modulators, detectors, and passive devices capable of operating at data rates up to 50 Gb/s [117,118].

There are several architectures, modulation schemes, and ﬁber arrangements that may be used to construct an ultra-high bandwidth silicon link, each with their own tradeoﬀs [119–128]. Recent work includes demonstrated links up to 320 Gb/s using an 8-channel wavelength-division-multiplexed (WDM) ring transmitter [119]. Other results in silicon have used the Mach-Zehnder modulator (MZM) to demonstrate a WDM 250 Gb/s transmitter and WDM 200 Gb/s transmitter [120, 121]. WDM photodetector arrays up to 40 channels at 40 Gb/s each have also been demonstrated

[122]. While WDM links can signiﬁcantly improve the spectral eﬃciency of each

fiber channel, this type of transmitter does incur additional expense in the form of lasers and wavelength filtering. In contrast, parallel single mode (PSM) links require fewer lasers but do need additional optical fibers. We propose and demonstrate a silicon transceiver with 48 x 50 Gb/s channels, for a total aggregate data rate of 2.4 terabits/s. The transmitter channels have been individually tested for sensitivity, insertion loss and power consumption. The photodetectors are tested for open eyes at 50 Gb/s.

43 Figure 4.1: Cross-section and rendering of the key devices of the OpSIS platform (not to scale) [6]

4.2 Fabrication and Platform Capabilities

Fabrication occurred at the Institute of Microelectronics, A*STAR, Singapore [129].

The starting material was a 200 mm SOI wafer with a top silicon thickness of 220 nm and buried oxide thickness of 2 µm. The handle silicon substrate has a resistivity of approximately 750 Ω cm. A SiO2 hardmask is deposited above the 220 nm layer, defined by the first lithographic mask. Then, a 60 nm etch is performed to define the 160 nm thick grating coupler layer. This is followed by a 70 nm etch to form the 90 nm thick slab layer. After the hardmask is stripped, six silicon implants are performed: n++, n+, n, p, p+, and p++. The peak doping densities for the n+, n, p, and p+ were chosen based on simulation to be 3 × 1018 cm−3, 5 × 1017 cm−3,

7 × 1017 cm−3, 2 × 1018 cm−3, respectively. A rapid thermal anneal is then performed at 1030 ◦C for 5 seconds. After the silicon anneal, epitaxial Ge is selectively grown on top of the silicon to a height of 500 nm with an angled sidewall. A phosphorous implant is used to form the n-type contact of a p-i-n photodetector. The Ge implant

44 is then activated with a 500 ◦C anneal for 15 s. Finally, two layers of aluminum metallization are deposited. Note that no chemical-mechanical planarization is used and all process steps were performed using 248 nm lithography. See Figure 4.1 for a cross section of the major devices.

In order to construct the link, we utilized a set of devices as part of the OpSIS process development kit (PDK) with minimal changes in order to ensure high yield and reliability. For testing purposes, light is coupled onto and oﬀ of the chip using a grating coupler with an insertion loss of 4.4 ± 0.2 dB at 1550 nm and 1.5 dB bandwidth of 50 nm [130]. Three types of waveguides are used on chip: 500 nm channel for short routing, strip-loaded 500 nm rib for the pn junction phase tuner and thermal phase shifter, and a wide 1.2 µm channel waveguide for long routing.

The wide routing waveguides, which constitute most of the on-chip optical path, result in 0.27±0.06 dB/cm loss [117]. A Y-junction with 0.28±0.02 dB excess loss is used as part of an on-chip splitter network and in the arms of the Mach-Zehnder modulator [131].

The traveling-wave modulator used here has a 3-dB bandwidth of 30 GHz and a similar geometry for 1.3 um light has been shown to operate at 50 Gb/s [107, 118].

A 3-mm long pn-junction phase shifter is used with periodic undoped striations such that the pn-junction encompasses 90% of the total phase shifter length. The implants add 11.1 dB/cm additional loss to the 2.0 dB/cm strip-loaded rib waveguide loss.

The phase shifter has a small-signal VπL at a -1 V bias of 2.6 V-cm, and the 3-dB bandwidth of the modulator is 30 GHz at a -1 V reverse bias, as shown in Figure 4.2(a) and Figure 4.2(b). The gain-peaked photodetector in the receiver chip has been

45 Figure 4.2: (a) The small signal VπL versus bias voltage of the PDK traveling wave Mach-Zehnder modulator. The small signal VπL is 2.6 V-cm at a -1 V reverse bias. (b) EOS21 response of the Mach-Zehnder modulator at 0 V and -1 V reverse bias. previously shown to have a bandwidth of 67 GHz, responsivity of 0.75 A/W, and dark current of 0.61 µmA at a 2 V reverse bias [102]. Photodetector responsivity and bandwidth data from this wafer is shown in Figure 4.3(a) and Figure 4.3(b).

4.3 System Design

The modulators and photodetectors are placed on separate chips on the same wafer.

The modulator chip is 13.2 mm x 32 mm and the detector chip is 11.8 mm x 32 mm.

46 Figure 4.3: (a) PDK gain-peaked photodetector I-V response under illumination and dark showing 0.75 A/W responsivity and 0.61 µA dark current at -2 V bias. (b) Frequency response showing 3-dB bandwidth in excess of 40 GHz.

The large size of these chips is to enable easier eventual packaging (the optical devices for the transceiver consume much less area than the total available chip area). Block diagrams and photographs of each channel of the transmitter and receiver chip are shown in Figure 4.4(a-d).

Light is coupled into the chips via grating couplers and, whenever possible, 1.2

µm wide waveguides are used to minimize waveguide loss. On the modulator chip, there are 12 total laser inputs, each split 4 times to form 48 output channels. There are also 2 additional dedicated grating couplers to perform active alignment with a

ﬁber array for eventual packaging. Thus, there are a total of 62 input grating couplers

47 Figure 4.4: Block diagram (a, c) of each channel of the transmitter and receiver and photographs (b, d) of the transmitter and receiver chips with key features identiﬁed.

48 in the modulator chip. The receiver chip is similarly laid out with 48 input and 2 alignment grating couplers. All grating couplers are located in the center of the chips and are uniformly spaced in a single line at a 127 µm pitch.

In order to reduce crosstalk, each photodetector is placed on a 900 µm pitch and each modulator is placed on an approximately 815 µm pitch, where the outer ground wires of the modulator transmission lines are separated by at least 300 µm. The 70

µm x 70 µm RF input pads of the modulators are placed around the periphery of the chip in a GSGSG conﬁguration, and are connected to 25 µm long tapers that directly lead into the transmission line of each traveling wave modulator. On-chip

RF termination is accomplished by using the n++ implanted silicon layer. These termination resistors are located at the end of the traveling wave modulator. DC pads for the thermal phase tuners in each arm of the Mach-Zehnder interferometer are placed along the bottom edge of the chip. Two layers of metal are used to route the DC phase tuner signals from each Mach-Zehnder to their respective pads. In total there are 98 DC bond pads evenly spaced along the bottom edge of the chip (2 thermal phase tuners for each channel and 2 common ground pads).

The layout of the traveling wave modulator has been slightly modiﬁed from what is found in the OpSIS-IME process development kit (PDK). On the original PDK device, RF contact pads are present at either end of the transmission line. In our device, we replace the RF contact pads with on-chip termination resistors formed by

220 nm silicon implanted with n++ doping. The typical n++ sheet resistance is 65

Ω/2 and the termination resistor was targeted to be 33 Ω to match the transmission line impedance. Finally, resistors are embedded next to the waveguide after the pn

49 Figure 4.5: Block diagrams of the test setup for the transmitter (a) and receiver (b) chips. junction phase shifter to form thermal phase tuners. These resistors are constructed from n++ doped silicon implanted in the 90 nm thick strip portion of a strip-loaded rib waveguide. Using thermal phase tuners to bias the device rather than changing the bias on the RF phase shifters is desirable for several reasons. First, it allows for much lower power operation than applying a bias on the transmission line since the device requires termination. Second, it allows the junction to operate at the same bias voltage across the chip, only the tuning power varies from device to device. Finally, since the depletion-mode phase shifters exhibit deminishing phase shifts at higher voltages, thermal phase tuners enable proper optical biasing no matter the electrical bias condition.

50 Figure 4.6: (a) Average insertion loss across the 48 channels of the transmitter is -11.89 dB ± 0.83 dB. (b) The thermal tuning eﬃciency of the phase tuners is 90 mW/π.

4.4 Testing Methodology

The chip was tested on a wafer-scale test setup with optical and electrical probing.

Optical coupling was achieved by a ver-tically incident array of fibers and input into on-chip grating couplers, which redirect the light from the fiber mode into the on-chip waveguide mode. The fiber array consists of a linear array of polarization maintaining

fibers at a 127 µm pitch. All testing is performed on a thermally-controlled chuck kept at 30 ◦C, although no significant changes in performance are expected based on small fluctuations in temperature. With only one test setup the two chips are tested separately: the transmitter is tested with a commercial receiver, and the receiver is tested with a commercial modulator.

For high speed testing of the transmitter, a tunable laser source was set to 1550 nm and input into an EDFA, the device under test, a second EDFA, a low pass

ﬁlter, and ﬁnally a variable attenuator before being received by a Picometrix AD10-ir photoreceiver. The photoreceiver has a rated sensitivity at 40G of -8 dBm. Each

Mach-Zehnder modulator was biased at the -3 dB point by changing the power input

51 to the thermal phase tuners embedded in each arm of the interferometer. For BER and eye diagram testing, an Anritsu MP1822A is used to generate and analyze the

50 Gb/s PRBS31 pattern. Eye diagrams were measured using an Agilent 86100C

Digital Communications Analyzer (DCA). The reference lithium niobate modulator that we used to compare our transmitter against is a Covega LN05S MZM driven to high extinction with a Centellax OA4MVM3 modulator driver. Similarly, the receiver is tested using the same tunable laser, first EDFA, and bandpass filter. Each photodetector in the receiver is probed with a 50 Ω terminated microprobe and input into the same Centellax amplifier used to drive the lithium niobate modulator. See

Figure 4.5(a) and Figure 4.5(b) for a block diagram illustration of these two respective test setups.

4.5 Results

DC Performance

All 48 channels of the transmitter were tested for insertion loss and BER vs received optical power. The on-chip insertion loss is -11.89 ± 0.83 dB, which includes routing waveguides and two Y-junctions to split each input channel into four output channels.

The variation of the on-chip insertion loss is likely an overestimate of the actual variation due to unaccounted-for differences in the grating coupler efficiencies between channels as well as measured differences in optical waveguide path lengths. The grating couplers used in this testing have been previously characterized and found to

52 Figure 4.7: Measured S11 of the traveling wave modulator with on-chip termination resistor. have an average insertion loss of 4.4 ± 0.2 dB. Loss due to rout-ng waveguides varies from 0.3 dB to 1.0 dB due to path length diﬀerences between channels. The optical losses across the 48 channels are summarized inFigure 4.6(a).

Thermal phase tuners using 185 Ω resistors next to the waveguides are integrated into both arms to bias the device. The average thermal tuning power to bias each arm of the device is 22.5 mW, shown in Figure 4.6(b). Linewidth nonuniformity induces random phase errors in these devices [132]. Due to a relatively short coherence length, the 0 V bias point for each channel is eﬀectively random, and thus requires manual tuning to reach the desired bias point on each channel.

53 High-speed Performance

The measured termination resistance is found to be 40 Ω. A plot of a typical S11 is shown in Figure 4.7. RF reﬂections are kept near or below -10 dB up to 30 GHz and do not prevent the attainment of 50 Gb/s performance. Future iterations of this device will include termination resistors that are more accurately matched to the transmission line.

Each channel of the transmitter is tested for bit error rate vs. received optical power using an external photoreceiver and the results are shown in Figure 4.8(a).

The traveling wave modulator transmission line characteristic impedance is 33 Ω, which is terminated by a 40 Ω resistor constructed from n++ implanted silicon (the termination resistor was targeted at 33 Ω but is subject to fabrication variation). We drive each channel of the transmitter with a diﬀerential 3.5 Vpp signal with 1.5 V reverse bias. With the optical bias set to the quadrature point, a random sample of six modulators achieved 7.0 ± 0.96 dB of extinction. The 20%-80% rise time across the same random sample is measured to be 10.4 ± 1.1 ps, and the peak-to-peak jitter is measured to be 8.17 ± 1.65 ps. Note that 1 channel of this set of modulators had only 1 neighbor, while the remaining modulators had neighboring channels on both sides. All testing is performed while modulating only a single channel.

Across all 48 channels of the modulator array, the sensitivity at a BER of 10-9 is -2.87 ± 0.63 dBm with a slope of -0.32 ± 0.05 dB1/2dBm−1. The random sample of six modulators mentioned previously exhibited a sensitivity of -3.0 ± 0.76 dBm.

A commercial lithium niobate modulator driven to high extinction with a 5.0 Vpp

54 Figure 4.8: (a) Bit error rate versus received optical power of all 48 channels of the silicon transmitter using a PRBS31 signal. A comparison trace using a commercial LiNbO3 modulator in place of the transmitter is shown in red. (b) Optical eye diagrams of a typical silicon modulator channel at 50 Gb/s, (c) as well as the LiNbO3 modulator at 50 Gb/s for comparison (c). signal is also tested in the same link. It is found to result in a sensitivity of -1.48 dBm at the same BER. A typical eye diagram for one channel of our transmitter is shown in Figure 4.8 (b), and an eye diagram of the LiNbO3 modulator is shown in Figure 4.8(c). The statistics of bit-error-rate versus received optical power of the transmitter is shown in Figure 4.9(a) and Figure 4.9(b). As can be seen from the histogram, the sensitivity of every channel falls within a 3 dB window and the slopes of the BER curves are relatively uniform.

The receiver is not packaged, and is thus only tested at the die level for open

55 Figure 4.9: Statistics of the BER versus received optical power of the silicon transmitter. Receiver sensitivities at a BER of 10-9 (a) show high uniformity across all channels, as do the slopes (b) of the BER1/2 vs. power traces.

50 Gb/s eye diagrams. Typical eye diagrams at 43 Gb/s and 50 Gb/s are shown in

Figure 4.10(a) and Figure 4.10(b). From the eye diagram at 50 Gb/s of one of the photodetector channels, the 20%-80% rise time is 9.8 ± 0.3 ps and the peak-to-peak jitter is 10.5 ± 0.6 ps. Given the RF performance and dark current and considering shot and thermal noise, if we assume this PD is input to an ideal TIA with 5 dB noise ﬁgure and 30 GHz bandwidth, the receiver sensitivity is theoretically predicted to be -9.5 dBm.

Previous measurements have shown the photodetectors to have responsivities of

0.74 ± 0.13 A/W [117]. Assuming the same responsivity distribution on this wafer, receiver sensitivity would then vary from -8.6 dBm to -10.13 dBm for the 5 dB amplifier noise figure case. The receiver sensitivity of the chip will also ultimately be affected to a large degree by the insertion loss from fiber to chip, the packaging scheme, and the design of the amplifier receiver chain. Grating couplers are used here due to their ease of testability. However, future iterations may make use of edge couplers, which have been shown to have coupling losses as low as 2 dB in this platform [133].

Cross talk between modulators is potentially a serious issue in tightly packed

56 Figure 4.10: Typical receiver eye diagrams at 43 Gb/s (a) and 50 Gb/s (b). photonic systems. Thermal cross talk from the neighboring channel was found to be approximately 1.8 rad/W for the pn modulator termination resistor and 0.36 rad/W for the thermal tuners. While BER degradation due to RF crosstalk is also an important parameter to characterize, it is infeasible to directly measure due to geometrical limitations with our current test setup. It is physically impossible to optically probe our device as well as apply two bulky RF probes and the two DC probes to adjacent channels. Instead, we present the electrical S21 between the input

RF contact pads of neighboring devices, with the general conﬁguration outlined in

Figure 4.11(a) and Figure 4.11(b). By knowing that the impedance of the RF probes is 50 Ω, that the transmission line impedance is 33 Ω, and that the termination resistor is 40 Ω, it is possible to estimate the coupling, k, between adjacent arms.

From Figure 4.11(c), the largest value for the S21 between adjacent modulator input pads is -41.5 dB. We make the conservative assumption that the entire coupling between adjacent modulators is due to the forward propagating wave, and that the measured S21 is due to the reﬂection of this forward coupled wave. Thus, we may

57 solve for the coupling, k, with the expression:

2 2 S21 = 2Γ2(k − k )(1 − |Γ1|) (4.1)

where Γ1 is the reflection coefficient between the probe and the modulator transmission line, and Γ2 is the reflection coefficient due to the on-chip termination. While a likely overestimate of the coupling, this suggests that the coupling between adjacent devices is at most -23 dB at 14.2 GHz, and is lower than this at other frequencies.

Observing the rule of thumb presented by [134], there is expected to be less than 0.74 ps of crosstalk-induced jitter in this modulator array.

In future work to package these chips, it will be important to carefully manage the electrical crosstalk between neighboring channels. Flip chip bonding would provide the lowest parasitic eﬀects [124]. Due to the large size of the chip, accommodating wire bonds to a PCB is also possible, though this introduces signal integrity challenges.

Diﬀerential signaling through the wirebonds will help to reduce crosstalk compared to the wirebonding for a single-drive modulator. On the receiver, it would be ideal to directly wirebond from the photodetectors to a TIA. A typical highspeed TIA die may be on the order of 1.2 mm to a side, and thus for 48 channels would require at least 57.6 mm of total chip edge length, assuming only single-channel TIA dies are used. By using multi-channel TIA chips, and given the large size of the receiver chip, it should be possible to accommodate such an array of ampliﬁers.

58 Figure 4.11: Electrical S21 of driving transmission line contact pads of adjacent arms of two neighboring modulators.

59 Energy Eﬃciency

We estimate power consumption of this device by assuming an ideal NRZ input signal and measuring the average thermal tuning power. The total energy eﬃciency of each channel of this transmitter may then be described by the equation:

N (V /2)2 V 2 P Energy/bit = input pp + bias + tuning,avg (4.2) B 40Ω 40Ω B

where Ninput is the number of electrical inputs (two due to diﬀerential drive), B is the data rate in bits per second, and Ptuning,avg is the average power consumption to bias the Mach-Zehnder interferometer. The coherence length of the waveguides is found to be shorter than the Mach-Zehnder arm length. Since there is a thermal phase tuner in both arms of the Mach Zehnder the necessary thermal bias power of each channel is randomly distributed between 0 and Pπ/2. Operating at 50 Gb/s using a 3.5 Vpp signal with 1.5 V reverse bias, the energy eﬃciency of the transmitter is 5.1 pJ/bit where 2.4 pJ is due to the driving signal, 2.2 pJ is due to heating in the transmission line termination resistor due to the bias voltage, and 0.45 pJ is due to thermal tuning.

For improved power consumption, this device could be operated at 0 V bias with a 2.0 Vpp drive signal (though with reduced sensitivity performance) [107]. The eﬃciency of the thermal tuners could also be improved by lightly doping the core of the waveguide to act as a resistor [118,135], or by performing isolation etches around the thermal tuners [136]. Ultimately though, the system power consumption will be largely dominated by the modulator driver ampliﬁers and high power lasers.

60 4.6 Conclusion

In conclusion, we have demonstrated a single-chip parallel single mode transmitter and receiver fabricated in a fully-integrated SOI platform with 2.4 terabit/s aggregate data rate. The transceiver makes use of the OpSIS PDK device library and fabrication process steps. The transmitter is based on the Mach-Zehnder modulator and consists of 48 channels, each operating at 50 Gb/s. The receiver utilizes a gain-peaked Ge p-i-n photodetector. While in our experiments we use an EDFA, the bandpass filter before the receiver removes the majority of the amplifier noise. Thus, the link may be effectively compared against other unamplified links one might find within data center networking or high-performance computing.

While we demonstrate a parallel single mode ﬁber link, one could use devices already demonstrated in this platform to construct other architectures, such as polarization or wave-length-division multiplexing based transceivers [119, 137]. The high-uniformity across all channels demonstrates that it is possible to scale large highly parallel silicon transmitters to many terabit/s and beyond.

61 Part II

Complimentary Components

62 Chapter Five

Monolithically Integrated

MESFET Devices on a High-Speed

Silicon Photonics Platform

This chapter covers my work integrating MESFET transistors into a silicon photonics platform without any process change. This was the first demonstration of the silicon photonics MESFETs and one of a very few demonstration of a no-change integration of transistors into a silicon photonics platform. Most ”no-change” processes go the other direction, adding silicon photonics to a CMOS electronics process [138]. In this paper, both NMES and PMES transistors are shown to work with cutoff frequency up to 2.2 GHz and transconductance of 46.4 µS/µm, sufficient for common control applications such as driving a thermal phase shifter or amplifying a monitor photodiode. I performed the device design, measurement, parameter fitting and analysis.

63 Ruizhi Shi, Matt Streshinsky, Jingcheng Tao and Kang Tan contributed to test and analysis. This work was published in the Journal of Lightwave Technology.

A. Novack, R. Shi, M. Streshinsky, J. Tao, K. Tan, A. E.-J. Lim, G.-Q. Lo,

T. Baehr-Jones, and M. Hochberg, “Monolithically integrated MESFET devices on a high-speed silicon photonics platform,” Journal of Lightwave Technology, vol. 32, no. 22, pp. 3743–3746, 2014

5.1 Introduction

Increasing requirements for interconnects in terms of bandwidth, power, integration density and cost have fueled extensive research for technologies that meet rapidly evolving technical demands. Silicon photonics has emerged as one possible technology for next generation interconnects due to the high index-contrast between silicon and silicon dioxide and CMOS compatibility, which enable low-cost optical systems-on- chip with high integration density [140]. The performance of many devices built in silicon now rival their counterparts in other material platforms. Further research into silicon photonics will shift from individual device performance to the creation of integrated photonic circuits such as the recently published 100G silicon photonic coherent transceiver [141].

Electrical ampliﬁcation and feedback are critical components of such large-scale systems. One method of integrating electronics and photonics is by developing the photonic circuitry on an established CMOS electronics process, such as what has been shown by Luxtera [142] and IBM [143]. These single chip solutions have high

64 performance electronics and achieve tight electronic- photonic integration, but are complex, costly, and diﬃcult to modify. Alternatively, a multi-chip architecture can be used in which the photonic chip and electronic chip are built in separate processes.

This approach beneﬁts from the fact that optical devices do not require the extremely small feature sizes in the most advanced CMOS technologies.

As complexity grows, the chip-to-chip interconnects may create a bottleneck for further improvement of the multi-chip architecture. Advances in wire bonding, bump bonding and through-silicon-vias will enable high-performance multi-chip architectures in the near term. However, limitations in pin counts for chip-to-chip communication may inhibit future development of medium to large-scale systems in silicon photonics.

One approach that would alleviate the chip-to-chip congestion is to develop a reduced set of transistors on the photonics chip. This reduced set of transistors would not replace the digital logic chip, but would be simple additions to the processing of the silicon photonics chip and would provide on-chip feedback for applications such as ring resonator stabilization and modulator biasing. This approach significantly reduces the number of off-chip connections needed between the photonic chip and the logic chip. Similar efforts in this direction include the integration of germanium photodetectors and 180 nm MOSFETs on a single platform [144], but requires significant processing changes to the photonics flow. Using metal-semiconductor field-effect transistors (MESFETs) instead of MOSFETs eliminates the need for process complexity introduced by the gate oxide. MESFETs make a direct contact between metal and silicon which creates a Schottky junction. Varying the gate voltage modulates the

65 depletion width of the junction, which changes the current between source and drain.

Recent research on silicon MESFETs have shown transistors with cutoﬀ frequency as high as 45 GHz [145–148]. Photonic integration with MESFETs has previously been demonstrated in GaAs platforms [149, 150] but has not yet been demonstrated on a silicon photonic platform.

We present MESFET devices integrated in a high-speed silicon photonics platform with no process modifications. The photonics platform consists of high-speed modulators [151] and detectors [152] capable of 50G performance. The addition of a MESFET to such a platform will enable the construction of more elaborate photonic systems that incorporate electrical feedback. Additionally, the simplicity and compatibility of this transistor design with current silicon photonics platforms, such as the photonics-only foundry services offered by OpSIS and ePIXFab, enables rapid integration with these processes with minimal or no process changes. The additional design flexibility of a MESFET offered to these photonics platforms will enable a significantly higher level of system complexity.

5.2 Platform Fabrication and Design Contraints

The MESFET devices were fabricated at the Institute of Microelectronics as part of the OpSIS foundry service. Details about the process have been previously reported

[153]. The silicon-on-insulator wafer with 220 nm top silicon layer and 2-µm buried- oxide layer is patterned using 248-nm lithography. Three anisotropic etches are used to deﬁne silicon heights of 220, 160, 90 and 0 nm. Ion implantation is then performed

66 Figure 5.1: Cross-section of silicon photonic platform showing grating couplers, germanium detectors, modulators, and n-type MESFET. Inset shows the detailed geometry of the MESFET. with a series of six silicon implants (p++, p+, p, n++, n+, n) that were optimized for modulators. The same implants were utilized for the MESFETs as shown in

Fig. 1. The p++ and n++ implants were used for contacts and the p+ and n+ were used exclusively for the modulator. The n and p implants were used for the channel region of the MESFET and consisted of a doping concentration of roughly

7 × 1017 atoms/cm3 for p and 5 × 1017 atoms/cm3 for n. The post-anneal doping cross sections were designed to be consistent with depth. Germanium was grown for the detectors followed by germanium implants. The aluminum back end was then fabricated. Contact to silicon consists of a thin TaN buﬀer layer. Sample results from detectors and modulators on the same wafer as the transistors are shown in

Figure 5.2.

67 Figure 5.2: Data taken from photonic devices on the same wafer as the transistors. (a) Photodetector responsivity at 1550 nm, (b) Photodetector dark current and (c) 1310 nm modulator 40G eye diagram.

The MESFET was designed with the constraints of ﬁxed doping levels, silicon heights and feature sizes. To minimize the threshold voltage (VT ), the lowest concentration n-type and p-type implants were chosen for the channel doping. The channel height (hch ) was chosen to be the 90 nm silicon layer to increase the channel control of the gate and keep VT low. The silicon height (hsi) on either side of the channel remained unetched (220 nm) to enable the use of the smallest feature sizes oﬀered by the platform. Since the metal gate is longer than the channel length, part of the metal gate sits above 220 nm silicon while the center of the gate sits on the 90 nm silicon. The channel length (Lch ) was chosen to be 220 nm as a compromise between high speed and adequate channel control. The metal gate contact (Lcontact) was 800 nm wide and the access lengths to the contact doping (Lad and Las ) were both 1

µm. The channel width was chosen to be 4 µm for all MESFETs in this work.

68 Figure 5.3: Measured ID –VDS of the NMES transistor.

5.3 Results and Discussion

Measurements were taken of the NMES and PMES transistors at dc. The characterized transistor all used a width of 4 µm. Drive current of the NMES exceeded

250 µm/µA at a gate voltage of 0 V and a drain voltage of 1.5 V as shown in Fig- ure 5.3. This value is comparable or exceeds previously published MESFETs with similar geometries [146].

The PMES transistor showed a slightly lower drive current as expected from the lower hole mobility in silicon as shown in Figure 5.4. The threshold voltage of the

PMES was also signiﬁcantly larger and the breakdown voltage was smaller. Due to these limitations, the NMES was chosen as the focus for further investigation.

The Id–Vg characteristic of the NMES was then measured (see Figure 5.5). The threshold voltage was calculated from measurements of ﬁve transistors on a single wafer and was measured to be 1.42±.06 V. The transconductance of the transistor

69 Figure 5.4: Measured IDD–VDS of the NMES transistor. is 46.4 µSv/µm for the 4-µm transistor. High drive currents over 200 µA/µm at relatively low drive voltages show that this type of transistor will be useful in integrated photonics applications. One simple example of such use is for thermal tuning of photonic switches. An on-chip photodetector could be used to trigger switching assuming enough power can be driven to the optical switch. Depending on the eﬃciency and geometry of the switch, tuning power can vary from 1 mW for ultra- eﬃcient rings [154], to 27 mW for un-optimized, 42-Ω thermal-shifters integrated into

Mach–Zehnder interferometers (MZIs) [151]. Using the case of the MZI and assuming the driving transistor is sized to have just 10% of the resistance of the thermal phase shifter (4.2 Ω, the MESFET would require a width of about 200 µm, which is comparable in size to the thermal phase shifter itself. Thus using the MESFETs in this work to drive an MZI using thermal phase shifters should be practical.

Despite the non-optimized contacts, gate leakage is manageable for moderate gate voltages. At an operating point of 0.6 V and drain voltage of 1.2 V, the leakage is

70 Figure 5.5: Measured ID–VG curves for the NMES at various drive voltages in linear scale (top) and log scale (bottom).

71 Figure 5.6: Measured IG–VG curves for the NMES at various drive voltages.

Figure 5.7: Plot of a NMES gate capacitance and cutoﬀ frequency as a function of gate voltage.

72 approximately 1 µA (see Figure 5.6), which is less than 1% of the drain current.

Reducing the length of the gate contact would likely enable a lower gate current.

High-speed transistors can be used to build superior feedback systems in which the ampliﬁer response time is minimized. Speed is critical for certain switching applications [155]. For thermal feedback applications, high-speed performance is not as crucial as the thermal time constant is relatively slow, on the order of 1 ms [156].

The NMES capacitance was extracted from the calibrated S11 response of the transistor and is shown in Figure 5.7. The capacitance decreases as a function of the gate voltage due to the depletion of the channel region. The cutoﬀ frequency (ft) of the transistor, also shown in Figure 5.7, is given by

g f = m (5.1) t 2πC

where gm is the transconductance and C is the sum of the gate-source and gate- drain capacitances. At VD of 1.2 V and VGS of 0.6 Vm, which is near VT /2, the cutoﬀ frequency is 2.2 GHz.

There are a number of improvements that could be made to this MESFET design.

The most critical element of the FET is the gate contact. The TaN gate contact was chosen for it’s low contact resistance, but could be replaced with a material that would make a better Schottky junction to minimize gate leakage. Minimizing the access length, which would reduce the source-drain resistance, could enhance the drive current. However, optimization of the transistor process would have to be done carefully to avoid aﬀecting the photonic performance.

73 5.4 Conclusion

We have demonstrated both n-type and p-type MESFETs integrated on a high-speed silicon photonics platform. Drive currents over 200 µA/µm and cutoﬀ frequencies in the GHz range enable the creation of single chip, electronic-photonic feedback circuits that will enable the development of large integrated photonic systems. The MESFET was designed with no process changes, which allows the photonics to be optimized and enables integration with the current generation of silicon photonic platforms.

74 Chapter Six

Widely-tunable, Narrow-linewidth

III-V/silicon Hybrid

External-cavity Laser for Coherent

Communication

This chapter covers my work in adding a light source to a silicon photonics platform.

An InP-based gain chip is bonded to a silicon photonics chip with precision alignment.

A silicon-based external cavity reﬂector is used to provide feedback for the laser and tune the wavelength. The laser was shown to have a linewidth of <80 kHz across the C-band enabling its use in coherent systems that require low linewidth light sources. The laser was then demonstrated in operation in a system with a coherent transceiver operation at 34- Gbaud (272 Gb/s) dual-polarization 16-QAM. This was

75 the ﬁrst published demonstration of a completely silicon-photonic-based coherent link. This work was led by Hang Guan who led the test eﬀort. I led the design for packaging design, assembly and assembly test. Yangjin Ma led the laser cavity design. Tal Galfsky, Saeed Fathololoumi, Tam Huynh, Michael Caverley and Jose

Roman assisted with testing. Ruizhi Shi and Alexander Horth assisted with device design. This work was published in Optics Express.

H. Guan, A. Novack, T. Galfsky, Y. Ma, S. Fathololoumi, A. Horth, T. Huynh,

J. Roman, R. Shi, and M. Caverley, “Widely-tunable, narrow-linewidth III-V/silicon hybrid external-cavity laser for coherent communication,” Optics express, vol. 26, no. 7, pp. 7920–7933, 2018

6.1 Introduction

Silicon photonics (SiPh) devices have gained significant market traction in metro, data center interconnect, and intra-data center applications, and are widely viewed as a key technology for next-generation networks which will require high data rates, high density, energy efficiency, and low cost [158–164]. This kind of technology can be used to address a wide range of applications from short-reach interconnects [165–167] to long-haul communications [168–172]. However, practical silicon-based light sources are still missing, despite the progress in germanium lasers [173, 174], as both silicon and germanium are indirect-band semiconductors and inefficient at light generation.

This situation has propelled the study of III/V-based laser integration on silicon-on- insulator (SOI) platform.

76 Laser integration approaches fall into three general categories: monolithic, heterogeneous, and hybrid. Monolithic integration involves the direct hetero-epitaxy of

III-V materials [175–177]. Heterogeneous integration consists of the attachment of unprocessed III-V material to a silicon chip or wafer and the subsequent co-fabrication to form a laser [178–182]. Hybrid integration refers to the integration of a ﬁnished gain chip with a silicon chip or silicon wafer [183–192].

In this paper, we present a tunable laser with an ‘external’ silicon cavity for coherent communications. The laser is integrated by hybridizing a III-V reﬂective semiconductor optical ampliﬁer (RSOA) chip into etched pit receptor sites inside the silicon-on-insulator wafer. Our laser integration approach is designed to require only passively aligned bonding and allows multiple lasers to be integrated at the same time, which guarantees scalability, increases throughput, and lowers cost. The laser shows a measured wavelength tuning range larger than 60 nm with a maximum output power of 11 mW, lowest linewidth of 37 kHz (<80 kHz across C-band), and largest side-mode suppression ratio (SMSR) of 55 dB (>46 dB across C-band).

In addition, we have successfully demonstrated a 34-Gbaud (272 Gb/s) dual- polarization 16-ary quadrature amplitude modulation (16-QAM) back-to-back transmission using our III-V/silicon hybrid external cavity laser (ECL) and a silicon photonic transceiver. Although a variety of coherent transceivers in silicon photonics have been demonstrated [168–172], none use a silicon photonic based laser. To the best of our knowledge, this is the ﬁrst experimental demonstration of a complete silicon photonic based coherent link.

77 Figure 6.1: A schematic view of the tunable laser.

6.2 Laser Design

Laser Structure

The tunable laser is constructed with a passively bonded RSOA, a spot-size converter

(SSC), and a reﬂective external cavity built from ring resonators [193, 194]. The schematic of the III-V/silicon hybrid laser is shown in Figure 6.1.

For this work, we use 600 µm long Indium-Phosphide (InP) multi-quantum-well

(MQW) based RSOA as gain material. The output waveguide of the RSOA is angled by 9° and anti- reﬂection (AR) coated to reduce the back reﬂection at the facet.

The rear facet of the RSOA is coated with a high-reﬂectivity (HR) coating. The

SSC is implemented to provide mode-matching between the RSOA and the silicon waveguide. A directional coupler (DC) is connected to the SSC in order to split 37% of the power to the laser output port and 63% (or -2 dB) to the external cavity. For this prototype, a high coupling ratio is chosen to guarantee enough feedback provided by the external cavity and achieve lower threshold currents. On a production level, the coupling ratio can be optimized to trade for higher laser power.

A dual-ring Vernier ﬁlter is put at the end of the external cavity to form a tunable

ﬁlter with wide tuning range. The details of the ring design are discussed in section

78 2.3. The dual-ring structure is connected to a Y-junction to form an inline reﬂector.

The Y-junction with dual-ring as a whole can be regarded as a wavelength-selective reﬂector (WSR). Compared to dual-ring designs with Sagnac loop mirror at the end

[189], light travels in the WSR only once, reducing the round-trip loss by a half and hence increasing the feedback amplitude. A phase tuner is included before the WSR to ﬁne-tune the longitudinal mode of the laser cavity, in order to control mode hop behavior. By increasing the biasing voltage of the phase tuner, the longitudinal mode of the laser red shifts with respect to the WSR and can be aligned to the center of the WSR reﬂectivity peak. Between the WSR and phase tuner, a 2% DC tap to a monitoring photodetector (MPD) allows us to monitor of the feedback within the external cavity. We used 500 nm x 220 nm ridge waveguide for routing in the SOI chip. The total routing waveguide length of on the silicon photonics chip is 1100

µm, which results in the simulated longitudinal laser mode spacing of 0.18 nm. The laser output consists of a 5-µm mode ﬁeld diameter edge coupler intended to couple light into a lensed ﬁber.

Spot-size Converter

Due to the large mode mismatch between RSOA waveguide and silicon waveguide, we introduce an optical spot-size converter on the silicon photonics chip to reduce the coupling loss between the chips. Simulation result in Figure 6.2 shows how the electric

ﬁeld of the Si3N4 SSC waveguide (a) is comparable to the mode of the RSOA chip (b), here the mode mismatch is only -0.18 dB representing a 96% mode overlap. The SSC

79 Figure 6.2: Magnitude of the electric ﬁeld for (a) the silicon nitride waveguide on the silicon photonic chip, and (b) for the RSOA chip. coupler has an experimentally measured eﬃciency of (0.73 ± 0.06) dB on precision

6-axis alignment stages. Although the mode mismatch between the modes can be small, practically the coupling efficiency is lower than 96% given misalignments and the presence of a chip-to-chip gap. From 3D FDTD simulations shown in Figure 6.3, we find that a 0.5 µm vertical misalignment (y-axis) increases the mode mismatch by 1.2 dB; the coupler is more resilient in the horizontal direction (x-axis) given the asymmetric mode shape, the same 0.5 µm misalignment would result in a 0.5 dB increase in insertion loss. Further, the waveguides from RSOA and the SiPh chips are not in contact, there is a chip-to-chip gap. The Si3N4 waveguide is recessed from the facet of the SiPh chip by 1.1 µm and a 15° sidewall angle of the SiPh chip limits how close the two chips can be brought together. From simulations, we find that a 2

µm chip-to-chip gap increases the total insertion to 2.82 dB. In our best samples, we achieved an insertion loss for our ﬂip-chip bounded laser chip of 2.8 dB; we estimate that 2 dB is due to the chip-to-chip gap and that the remaining is caused by x/y misalignments.

80 Figure 6.3: Simulated mode mismatch between the silicon photonics chip and the SOA as a function of misalignment in the horizontal (x) and vertical direction (y).

External Double-ring Resonator Laser Cavity

The ring resonator layout is similar to our previous work [195]. The add-drop ring resonator performance is simulated by analytical means [196, 197] with parameters extracted from experimental data. One ring resonator has a bend radius of 20 µm

(R1) and an FSR of 4.99 nm near 1550 nm. The measured Q-factor is 5500. The other ring resonator has a bend radius of 16.3 µm (R2) and an FSR of 6.13 nm near

1550 nm. The measured Q-factor is 4800. The Vernier ring reflected spectrum is plotted in Figure 6.4(a). When the rings reflection is aligned at 1570 nm, the side mode extinction is larger than 8 dB across a 60nm range (1510 nm – 1570 nm), more than sufficient to operate over the entire C-band. Q-factor of the highest peak (where threshold condition is met) is about 8000.

The simulated and measured reﬂected spectra of R1 and R2 are shown in Fig- ure 6.4(b). We observe excellent agreement between simulation and experiment.

The experimental data (with grating coupler envelope de-embedded) is measured on

81 Figure 6.4: (a) Reflected spectra of the Vernier ring, normalized to the maximum power of the reflected spectra. The red line is the simulated spectrum, while the red dots are the measured spectrum. (b) Reflected spectra of R1 (red) and R2 (blue). The solid lines are the simulated spectrums, and the red dots are measured spectrums. wafer-scale through grating coupler, and hence limited from 1525 nm to 1575 nm, due to degradation of grating coupler efficiency at the edge wavelengths. Out of this range, extinction ratio of ring resonances becomes limited by power-meter noise

floor, which affects modeling accuracy in simulation. With the extracted ring model, we also aligned the reflection peak to other wavelengths from 1510 nm to 1570 nm and observed >8 dB side mode extinction ratio in all cases. The spectra at different wavelengths are slightly different from a shifted spectrum of Figure 6.4(a), due to dispersion in silicon waveguide. With >8 dB side mode extinction ratio and 60 nm tuning range, the dual-ring design is readily integrated with a RSOA to build a stable, C-band tunable single mode laser.

82 6.3 Laser Fabrication and Integration

The silicon photonic chip was fabricated at a complementary metal-oxide-semiconductor

(CMOS) foundry using standard CMOS-compatible processes. The substrate is an

SOI wafer with a 220-nm device layer. Front end etching and doping processes are used to build the waveguides and active components. A pit is formed with hard-stop structures embedded, in order to aid in aligning the silicon photonics chip with the

III-V device.

The InP RSOA chip was built in a III-V foundry using standard III-V processing techniques. The substrate was a 100 mm InP wafer with an epitaxial grown 1.9 µm wide ridge waveguide layer. The MQW layer was built using five AlGaInAs quantum wells with a gain spectrum centered in the C-Band at operating temperatures. The optical mode was roughly centered in the quantum well region which was located directly under the ridge. The extracted waveguide loss for RSOA is 12 1/cm. A series of etches defined the hard stop at the MQW layer as well as a recessed gold contact pad for bonding with the locations of these features matching that of the silicon photonic chip. The InP wafer was cleaved into bars which were HR coated on the back facet and anti-reflection coated on the front facet. AR facet was coated to

1.45 to match the eﬀective index of the mode in the silicon photonics and of the index matching gel making a pair of low reﬂection interfaces. The bars were then cleaved into chips comprising two channels each.

InP integration onto the silicon photonics chip was accomplished using a high- precision bonder with placement accuracy of ±0.5 µm. Vertical alignment was accom-

83 Figure 6.5: (a) Optical image showing the Vernier ring reﬂector. The left ring resonator has a radius of 20 µm (R1), and the right ring resonator has a radius of 16.3 µm (R2). (b) Optical image showing the III-V die and waveguide coupler. Two laser channels are aligned and packaged simultaneously. plished using the hard stop features on the silicon photonics and InP chips. Angular and planar alignments were accomplished using the bonder’s vision system which utilized alignment features deﬁned on both chips. Figure 6.5 shows the optical image of the Vernier rings and the hybrid assembled chips.

6.4 Laser Characterization

Mode-hop Free Light-Current Curve at Fixed Wavelength

The investigated device can be tuned across C-band for any ITU channel. The device is temperature controlled to 25◦C using a thermoelectric cooler (TEC). The output

fiber coupler is a 5-µm mode field diameter edge coupler. There is an off-chip isolator with 30 dB isolation connected during the measurements. Figure 6.6(a) shows the L-

I-V (Light-Current-Voltage) curve of the laser with the lasing wavelength at 1546.88 nm (193.8 THz). The lasing threshold is observed at 30 mA. For the fabricated device the observed threshold and output power suggest additional unaccounted loss of 1.2 dB in addition to the expected 2.8 dB coupling loss. The total loss of the device is 4

84 dB. Wall-plug eﬃciency (WPE) can be determined by dividing the on-chip power by the amount of power going into driving the RSOA chip. As shown in Figure 6.6(b) the ECL achieves peak WPE of 4.2% around at an injection current of 90 mA.

A major challenge for III-V/silicon hybrid external cavity lasers is overcoming wavelength drift and mode-hopping during the lifetime of the laser [198, 199]. An example of both wavelength drift and mode-hopping can be seen in Figure 6.7(a), where the laser spectrum is plotted as a function of injection current, without employing any ring or phase tuning. The lasing wavelength is seen to drift until it mode hops around 160 mA by 0.1 nm to the next longitudinal mode. This wavelength drift at the mode hop is smaller than the laser longitudinal mode spacing calculated previously, which is similar to the observation in [184]. Additionally, the wavelength drift before the mode-hop (or between the two mode hops) is larger than laser longitudinal mode spacing. The reason is that as the RSOA’s current increases, not only does the RSOA’s temperature increase, but also the temperature of the Si slightly increases as well, resulting in red-shifted ring wavelengths. Both wavelength drift and mode-hopping can be prevented over the long term by dynamically changing the biasing voltages to hold both of the rings at a given wavelength, and by modifying the bias on the phase shift element (PS0) to hold the longitudinal mode of the laser cavity steady.

To obtain the graph shown in Figure 6.7(b) we tune two rings (R1 and R2) and the phase shift element (PS0) for every current data point, using thermal phase tuners on each element [200]. The ring biases are initially set to power values corresponding to the selected wavelength (Figure 6.8). For the graphs shown in Figure 6.6(a) and

85 Figure 6.6: (a) L-I-V curve of hybrid laser. Blue and red curve are L-I and I-V curves correspondingly. (b) Extracted experimental WPE. (at 1546.88 nm)

Figure 6.7: (a) Spectral-L-I data without wavelength stabilization. (b) Spectra-L-I data with wavelength stabilization control.

Figure 6.7(b) R2 power is set to 0 mW, and R1 power is varied within 0.5 mW around a center value of 8 mW based on the maximum current reading from the

MPD. This corresponds to a lasing wavelength of 1546.88 nm. The phase tuner is initially set to a value corresponding to maximum reading on the MPD. Aligning the rings as described result in maximum reﬂectivity and hence maximum power on the

MPD. The rings are hence aligned with each other by maximizing the photocurrent reading on the MPD. The laser cavity phase tuner is then scanned and set to a value that biases the laser longitudinal mode to the center double ring resonance [200].

86 This way we keep the lasing mode away from mode-hop regions. However, tuning the phase tuner might cause the lasing wavelength to drift, consequently requiring further adjustment of the ring biases. This procedure is iteratively repeated until the measured wavelength matches the target wavelength. For this procedure, we use an optical spectrum analyzer (OSA) to monitor the lasing wavelength as the injection current is increased. This method allows us to tune and maintain the lasing peak around the desired wavelength to within OSA’s resolution of 0.02 nm for every injection current, corresponding to tuning accuracy of ±1.25 GHz in frequency. Such accuracy is within the tolerance needed in most communications applications (±2.5

GHz) [201]. This procedure is employed to demonstrate a mode-hop and wavelength- drift free operation as shown in Figure 6.7(b) and ensure ITU-compliant operation away from mode-hop points. Further work is needed to ensure that wavelength is continuously stabilized during the laser operation.

Tunability

Figure 6.8 shows the lasing wavelengths under diﬀerent thermal tuning power applied to the ring resonators with RSOA drive current of 180 mA. For every data the phase tuner was scanned between the ﬁrst and second π shift and optimized to a center maximum. This ensures operation away from mode-hop regions. Single-wavelength lasing with a SMSR in excess of 46 dB was obtained across a 60-nm tuning range.

The tuning range covers the entire telecommunication C-band. The color plot shows the laser tunability from 1515 nm to 1575 nm. The hue gradient along the diagonal

87 Figure 6.8: Lasing wavelength under diﬀerent R1 and R2 basing powers. The diamond markers indicate the basing powers at diﬀerent ITU grid.

Figure 6.9: Measured lasing spectra of the tunable laser across the C-band. color lines shows that the wavelength can be continuously tuned. Each one of the diamonds overlaid on the color plot represents the wavelength for an ITU channel in a 100 GHz ITU grid across the entire C-band. Figure 6.9 also shows that the tuning range of the laser covers the entire C-band.

88 Figure 6.10: (a) Measured laser output power spectrum with the highest SMSR of 55 dB. (b) Measured SMSR at C-band, 100-GHz-spacing DWDM ITU grid. (c) FM- noise spectrum using heterodyne laser linewidth measurement method at 1553 nm. (d) Measured linewidth at diﬀerent wavelengths across the C-band.

Spectral Performance (SMSR and Linewidth)

The SMSR was measured using an OSA with a resolution of 0.02 nm at room temperature, with a drive current of 180 mA. The highest measured SMSR was 55 dB, as indicated in Figure 6.10(a). Figure 6.10(b) shows the measured SMSR at diﬀerent wavelengths according to the C- band 100-GHz spacing dense wavelength division multiplexing (DWDM) ITU grid. The measured SMSR is larger than 46 dB from

1525 nm to 1575 nm, being smaller at the edges of the gain bandwidth.

The linewidth of the laser cannot be determined from the spectrum in Fig- ure 6.10(a), because the laser linewidth is smaller than the resolution of the OSA.

To measure the linewidth, we adopt a heterodyne measurement method [181, 202].

89 The output from our laser was mixed with a tunable laser (Keysight N7711A) and passed through a coherent receiver. The electrical signal is then observed on a real- time scope. The combined linewidth is analyzed from the FM noise spectrum, by taking the average of the ﬂat region of the noise spectrum (between 20 MHz and 80

MHz) and multiplying by π [202]. The linewidth integration time of our measurement can be calculated to be 25 µs. Our linewidth integration time was set properly to measure the entire FM-noise spectrum, especially the bottom ﬂat region of the

FM-noise spectrum (where we extracted the linewidth). The intrinsic linewidth of the reference Keysight laser was measured using the same method (≈40 kHz). The intrinsic linewidth of our ECL laser can be obtained by subtracting linewidth of the reference laser from the combined value. The measured linewidth for the ECL is below 80 kHz for 7 wavelengths selected as samples across the C-band as shown in

Figure 6.10(d). As a complimentary measurement to the linewidth we have also measured the relative-intensity-noise (RIN) of our laser at various wavelength using a

Sycatus RIN measurement system. We have the determined that for wavelengths in the C-band the maximal RIN in a frequency range from 100 MHz to 13 GHz was better than – 135 dB/Hz. Due to the limited sensitivity of the system values lower than -135 dB/Hz cannot be measured.

90 6.5 Coherent Transmission

Experimental Setup

To further evaluate the real-world performance of the laser, a coherent optical transmission experiment is needed [203]. We tested our laser in a noise-loaded, high-speed, dual- polarization (DP), 34 Gbaud, 16-QAM, non-diﬀerential coherent transmission system operating at 272 Gb/s with 25% FEC overhead and 3x10-2 threshold. Fig- ure 6.11 illustrates the setup used for this test. One highlight of this system is the integrated, silicon photonics-based, modulator/receiver assembly (IMRA). The IMRA houses a silicon photonic integrated circuit (PIC) containing a DP-QPSK modulator

(transmitter) and an optical hybrid. The IMRA also houses four low-noise TIAs, which, along with the optical hybrid, form the coherent receiver. The IMRA package has three fibers: one fiber is used for the external continuous-wave (CW) laser (our laser), which is split internally inside the package to serve as both the laser source for the transmitter and the local oscillator for the receiver. The second fiber is used for the output of the optical transmitter (Tx). The third fiber is used for the input signal into the coherent receiver (Rx).

A commercial, four channel, high-speed DAC and driver provided the high-speed

34 Gbaud, 16-QAM signals driving the DP-QPSK modulator. The transmitted 272

Gb/s optical signal was noise-loaded and looped back into the Rx signal port of the

IMRA. A commercial high-speed ADC and DSP were used to digitize and process the output signals from the IMRA receiver and measure the bit-error-rate (BER) performance of the system. The noise-loading setup (ASE source, optical ﬁlter, and

91 Figure 6.11: 34-Gbaud DP-16QAM experimental setup (main). Image of IMRA (inset). variable optical attenuator (VOA)) allowed us to control the optical signal-to-noise ratio (OSNR). An erbium-doped fiber amplifier (EDFA) and VOA were placed at the Tx output to boost and control the optical power into the receiver. An optical spectrum analyzer measured the signal power and OSNR into the receiver. With this setup, we can measure BER vs OSNR performance of the transmission system. Our tests were performed in loopback (back to back) mode. This configuration provided a simple way to test whether the DSP can handle the linewidth of the laser source.

We note that in coherent transmission systems, the section of the DSP which handles the laser linewidth is separate from the section of the DSP section which handles

ﬁber dispersion. Therefore, for this particular test, we chose not to propagate the Tx signal over long lengths of ﬁber.

Experimental Results of 34-Gbaud 16-QAM Transmission

In order to assess the performance of our laser source in the coherent system, we made two measurements. First, a reference measurement was made with a commercial

92 Figure 6.12: Measured BER vs. OSNR at 1547.2 nm. tunable laser source (Santur ITLA) suitable for long-haul coherent systems. The

CW laser power was 16 dBm. The laser wavelength was 1547.2 nm. The optical signal power into the receiver was -10 dBm. This ﬁrst measurement provided a baseline OSNR vs BER curve at -10 dBm input into the receiver. For the second measurement, the commercial laser was replaced with our laser source (this work).

An EDFA was used to boost the output from our laser to 16 dBm.

Figure 6.12 shows the comparison between the OSNR vs. BER curves measured at 1547.2 nm with both the commercial laser and our laser (this work). No noticeable shift was observed between the two curves, and no uncorrected errors were detected up to the FEC threshold. Similar results were obtained with a slightly diﬀerent setup, in which we compared our laser against the reference laser as source for a noise-loaded,

LiNbO3-based, 16-QAM, 272 Gb/s transmitter looped back into our SiPh Rx, but using a commercial laser (ITLA) as the local oscillator.

Figure 6.13 depicts the constellation diagrams of the 34 Gbaud dual-polarization

93 Figure 6.13: Constellation diagram of the 34 Gbaud DP-16 QAM using (a), (c) our ECL, and (b), (d) reference laser.

16-QAM using (left) our ECL, and (right) reference laser. The quality of the received signals in both cases are comparable. We note that it would not be possible to record a clean 16-QAM constellation if our laser was not high quality. These results confirm the suitability of our laser for coherent transmission applications. To the best of our knowledge, this is the first experimental demonstration of a complete silicon photonic based coherent link. This is also the first experimental demonstration of >250 Gb/s coherent optical transmission using a silicon micro-ring-based tunable laser, which is

>4 times faster than the previous result [203].

94 6.6 Discussion

The demonstrated III-V/silicon hybrid external cavity laser has three advantages:

(1) multiple laser channels can be passively aligned simultaneously, which is suitable for high-volume production of single and multi-channel lasers, (2) the high Q-factor

Vernier ring provides a wide tuning range and a narrow linewidth, and (3) mode-hop- free operation and wavelength locking operation are achieved by active controls.

Table 1 compares the performance of our work with other III-V/silicon hybrid external cavity lasers. SMSR and linewidth are the best results in C-band. Power and WPE are the maximum output power and largest wall-plug eﬃciency. Of these devices, our tunable ECL achieves the largest tuning range by a factor of 2 and the narrowest linewidth by a factor of 5.

Table 6.1: Performance comparison of recent C-band tunable laser works

Property [27] [28] [24] [22] [23] [33] This 2012 2012 2013 2013 2013 2014 work (2018) Integration Hybrid Hybrid Hetero- Hetero- Hetero- Hybrid Hybrid geneous geneous geneous Alignment Active Passive Passive Passive Passive Active Passive Coupling Butt Butt Butt Vertical Vertical Butt Butt Laser DBR Single DBR Single Vernier Vernier Vernier Laser Type DBR Single DBR Single Vernier Vernier Vernier Ring + Ring + Ring Ring Ring DBR DBR Tuning 8 NA >20 8 >40 35 >60 Range(nm) Power 6 15 8 10 3.3 20 11 (mW) WPE (%) 9.5 7.6 NA NA NA 7.8 4.2 SMSR(dB) 45 40 40 50 45 40 55 Linewidth NA NA 200 1700 338 27000 37 (kHz)

95 6.7 Conclusion

We demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm around the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is embedded in the silicon chip and is edge-coupled into the silicon chip. The demonstrated packaging method requires only passive alignment and thus potentially suitable for mass production. The laser has a largest output power of

11 mW with a maximum WPE of 4.2%. and a SMSR as large as 55 dB. The measured linewidth is as narrow as 37 kHz, which is the narrowest linewidth using a silicon-based

(not silicon nitride-based) external cavity. In addition, we demonstrate successfully a

34 Gbaud DP-16 QAM transmission using our laser and a silicon photonic transceiver on par with the performance of commercially available lasers. To the best of our knowledge, this is the ﬁrst experimental demonstration of a complete silicon photonic based coherent link. This is also the ﬁrst experimental demonstration of >250 Gb/s coherent optical transmission using a silicon micro-ring based tunable laser, which is the fastest coherent optical transmission speed using a silicon micro- ring based tunable laser.

96 Part III

Highly Integrated Optical Links

97 Chapter Seven

A Silicon Photonic Transceiver and

Hybrid Tunable Laser for 64

Gbaud Coherent Communication

This chapter covers my work combining various components into a full coherent optical system. A hybrid silicon photonic tunable laser is combined with the CSTAR, a compact coherent transceiver in a BGA form factor, and shown to operate up to

64 Gbaud QPSK. This work showed a combination of silicon photonic functions and performance that had not been previously demonstrated. I led the laser design for packaging, assembly and assembly test as well as the CSTAR design for packaging, assembly and assembly test. Matthew Streshinsky, Tam Huynh made signiﬁcant contributions to design and test. A number of other co-authors made contributions to design, assembly and test. This work was presented as a post-deadline paper at the

98 2018 Optical Fiber Communications Conference.

A. Novack, M. Streshinsky, T. Huynh, T. Galfsky, H. Guan, Y. Liu, Y. Ma, R. Shi,

A. Horth, Y. Chen et al., “A silicon photonic transceiver and hybrid tunable laser for

64 GBaud coherent communication,” in Optical Fiber Communication Conference.

Optical Society of America, 2018, pp. Th4D–4

7.1 Introduction

Silicon photonics has proven to be a compelling platform for next-generation coherent optical communication by integrating complex electro-optical circuits onto a single silicon chip [205]. High-speed modulators and photodetectors, low-loss ﬁlters and couplers, and high yields on low-cost SOI wafers have allowed for multiple successful commercial ventures based on this technology. However, the principle challenge of many silicon photonic platforms is still the cost and complexity of packaging and lack of a native light source. Moreover, the packaging and light source must be in a form factor that can conform to the size, power, performance, and price point that future coherent applications, such as 400G-ZR, require. In this paper, we address both of these points with our silicon photonic platform for advanced hybrid integration and packaging.

Approaches to laser integration in silicon have included epitaxially-grown III-V- on-Si [206], III-V chips bonded onto Si followed by wafer-level processing [207], and hybrid integration [208]. The ﬁrst two approaches pose signiﬁcant process development challenges and preclude compatibility with commercial CMOS foundries. In

99 contrast, hybrid integration allows the product to keep the complexity (and, ergo, challenges of yield) in silicon and use standard silicon processing tools. In order to take advantage of existing multi-chip module assembly infrastructure, though, optical modules must also accept manufacturing tolerances that have been “good-enough” for leading-edge electronic assembly: Lateral alignment tolerances of ±0.5 µm for critical steps (and 10 µm for everything else), compatibility with reﬂow assembly processes, and wafer-level processing. Once a platform demonstrates this compatibility, many more options for packaging and assembly become available, such as high-speed and high-density BGA form factors [209].

In order to keep the III-V processing as low-cost and high-yield as possible, we elected to use a simple, internally-designed reﬂective-semiconductor-optical-ampliﬁer

(RSOA) Indium Phosphide chip with spot-size converters, monitoring, and an external cavity on the silicon chip. For integration, we use standard pick-and-place tools, passive alignment, and solder-based bonding. To fit into a compact BGA form factor, our silicon photonic platform leverages the ability to bump copper pillars onto silicon wafers, optically couple light without lenses to standard 10-µm MFD fibers, and high- performance devices fabricated in a commercial CMOS foundry. We show a scalable, cost-effective Coherent Silicon Transmitter And Receiver (CSTAR) multi-chip module for next-generation coherent optical communication. Our coherent transceiver in a BGA package is assembled into a CFP2-ACO but tested with an external narrow- linewidth silicon hybrid tunable laser as the light source instead of the commercial

µITLA and then characterized at 64Gbaud.

100 Figure 7.1: (a) Block diagram of the tunable laser. Microscope images of (b) the external cavity and (c) hybrid integrated RSOA (backside

Figure 7.2: Measurements of one sample of the silicon photonic hybrid integrated laser: (a) linewidth vs. wavelength, (b) SMSR vs. wavelength, (c) lasing wavelength as a function of ring tuning powers, and (d) lasing spectrum at various points across the C-band.

7.2 Hybrid Laser Integration and Performance

A 600-µm-long Indium Phosphide (InP) multi-quantum-well reflective semiconductor optical amplifier (RSOA) is passively placed and bonded into an etched pit in a silicon photonics chip. Hard-stop layers on the PIC and InP allow for tight vertical alignment, while the bonding tool enables ±0.5 µm lateral alignment with the aid of a computer-vision system and on-chip fiducials. The external cavity structure on the PIC consists of a dual-ring Vernier filter which supports a wide tuning range.

101 Figure 7.3: (a) Block diagram of the CSTAR PIC, (b) underside of the CSTAR package (footprint 15 x 18 mm), (c) populated CSTAR substrate pre-ﬁber attach, (d) CSTAR assembled into a CFP2-ACO, and (e) VNA measurement of the CFP2- ACO transmitter showing 40 GHz electro-optic bandwidth.

Figure 7.1(a-c) show the cavity structure, dual-ring ﬁlter, and RSOA chip bonded to the silicon PIC.

We tested the silicon hybrid laser for parameters critical for coherent-communication light sources. Linewidth was measured using coherent heterodyne detection [210].

Figure 7.2(a,b) show linewidth ¡100 kHz and side-mode suppression ratio (SMSR)

¿45 dB at several wavelengths across the C-band. Relative-intensity noise is measured to be ¡-135 dB/Hz, limited by the measurement system. High SMSR and consistent output power is shown across a 60nm wavelength range. Tuning the power applied to the resistive heaters in both rings allows for a wide tuning range, as shown in Figure 7.2(c) with example spectra in Figure 7.2(d).

102 7.3 Performance in a Coherent Link

The hybrid tunable laser is characterized in two links with different optical engines: a first-generation Integrated Modulator and Receiver Assembly (IMRA) in a ceramic package with peripheral leads and a second-generation Coherent Silicon Transmit- ter and Receiver (CSTAR) in a BGA package. The IMRA is composed of a silicon die with integrated modulator, optical hybrid, and high-speed photodetectors and is wirebonded to two dual-channel TIAs. The CSTAR consists of a a low-temperature co-fired ceramic substrate with flip-chip-attached silicon photonic integrated circuit

(PIC), two custom dual-channel MZ-drivers, and two custom dual-channel TIAs (similar to what is presented in [211]). Standard 10-µm mode-ﬁeld-diameter (MFD) optical ﬁbers are actively aligned to the PIC. See Figure 7.3(a-c) for an overview of the

CSTAR.

Several of the CSTAR devices were assembled into CFP2-ACOs, as shown in Fig- ure 7.3(d). Vector Network Analyzer (VNA) measurements in Figure 7.3(e) of the

CFP2-ACO demonstrate >40 GHz electro-optic Tx bandwidth with a 200 mVppd stimulus. The dual-polarization CFP2-ACO transmitter constellation is shown in page 104(a) for 34Gbaud DP-16QAM. The CFP2-ACO, with our external silicon hybrid laser used instead of the on-board commercial µmITLA, is also characterized under 64 Gbaud QPSK operation one polarization at a time with a Tektronix Optical

Modulation Analyzer (OMA). Resulting BER vs. OSNR measurements are shown in Figure 7.4(b). The transmitter is driven with a DAC evaluation board and ca- bling with 14 GHz 3-dB bandwidth and tested in a CFP2-ACO module compliance

103 Figure 7.4: (a) A 34 Gbaud DP-16QAM constellation using the CSTAR. The silicon- photonic hybrid laser is used as a light source in two applications (b) Single-pol 64 Gbaud QPSK BER vs. OSNR of the CSTAR-based CFP2-ACO, measured on an OMA. (c) Dual-pol 34 Gbaud 16QAM BER vs. OSNR of an Integrated Modulator and Receiver Assembly (IMRA) comparing our ECL to a commercially available low- linewidth µITLA. board. Test equipment limitations prevent the characterization of the CFP2-ACO at 64Gbaud using higher-order modulation formats. The IMRA is also characterized with our hybrid laser at 34 Gbaud, 16QAM in a loopback conﬁguration with the same

ADC and DAC evaluation boards, as shown in Figure 7.4(c).

7.4 Conclusion

In conclusion, we have shown coherent links based on a silicon photonic transceiver at speeds up to 64Gbd QPSK using a narrow-linewidth silicon photonic hybrid tunable laser. Once the transceiver and laser are integrated on the same chip, this will be a powerful platform for next-generation coherent communication. The performance of the hybrid laser is comparable to that of commercially available micro-ITLAs. The silicon photonic coherent transceiver is built with a BGA package, including custom drivers and TIAs, and is assembled into a CFP2-ACO module operating at 64Gbaud.

To our knowledge, this result represents the ﬁrst reported all-silicon-photonic

104 coherent link, including the laser. Flip-chip assembly, large MFD coupling, and passively-aligned III-V chips enable ultra-dense low-cost silicon photonic coherent multi-chip modules.

105 Chapter Eight

Thesis Conclusion

8.1 Summary of Contributions

In this work, a coherent silicon photonics communication system was assembled piece by piece. The fundamental communication devices (photodetectors and modulators) were improved in term of speed, power consumption and turned into a repeatable platform. The transistors and lasers were then added to the platform to enable complex system building. Finally the fully coherent transceiver was built with tunable laser, and silicon photonics-powered optical engine.

8.2 Recommendations for Future Work

As the demand for data communication bandwidth continues to increase exponen- tially, further improvements in optical systems will be required. Individual components will need steady improvement to meet the demand of higher performance

106 systems. Further components will be needed to augment the silicon photonics platform and provided additional capability. More sophisticated systems will need to be designed with advanced packaging tying the parts together.

Future Work in Silicon Photonic Components

For photodetectors, there is a fundamental quantum eﬃciency limit to responsivity.

Just one electron is generated per photon. However, there is room to improve what happens next. The number of electrons coming out of a photodetector can be enhanced by gain, such as in avalanche photodetector that have shown promising results in silicon [212–214]. Higher gain photodetectors may not be necessary in coherent optical systems in which a local oscillator is already required for wavelength selec- tion and signal gain, but datacenter optical links will likely require photodetector gain in the future. Another area for improvement of the photodetector is with closer co-design with the TIA or other receiver electronics such as electronic/photonic integration or co-packaging to remove parasitics [215] or with novel schemes to optimize sensitivity [216].

The silicon photonic modulator is, in some ways, the weakest part of the platform, which leaves the most room for improvement. Modulators using the plasma-dispersion affect have a difficult tradeoff between modulator length, static loss and modulation efficiency. Optical resonance may allow performance beyond the typical limits. Ring modulators [217–219] or ring-assisted Mach-Zehnders [220] could provide the path forward if solutions can be found for the instabilities and non-linearities of resonance-

107 based devices. Segmented drivers [221], monolithic modulator/driver integration [222] or ﬂip-chip driver integration [223] are possible paths to achieving enhanced transmitter performance by reducing parasitics and optimizing for bandwidth or power consumption.

Speciﬁc recommendations for future work on silicon photonic components:

• Circuit modeling of avalanche photodetector and bandwidth optimization with

inductance peaking.

• Circuit modeling and optimization of a silicon photonics receiver with ﬂip-chip

TIA.

• Optically time-sampled receiver with inductive gain peaking

• Low power ring-assisted Mach-Zehnder modulator for high-speed and low power

consumption.

• Segmented ring-assisted Mach-Zehnder with ﬂip-chip driver.

Future Work in Complimentary Silicon Photonic

Components

As the complexity of silicon photonic components increases, enhanced integration with control circuitry will be required. This can take the form of the transistor integration into silicon photonics as presented in Chapter 5. In order for such a transistor integration to be usable for products more work is needed to characterize and optimize these transistors. Wafer-level measurements of the transistor cutoﬀ frequency and transconductance are needed. Simple control circuits (e.g. an FIR

108 ﬁlter or low-pass feedback loop) that can be the foundation for future circuit blocks need to be proven.

Gain media integration with silicon photonics has near limitless possible directions for future research. At a bare minimum, work needs to be done to reduce the coupling loss show in Chapter 6. After that, laser stability could be enhanced by the addition of an on-chip isolator [224] or temperature-independent wavelength reference. Enhanced laser functionality at high temperature could be obtained with the use of a quantum dot gain media [225] or multi-wavelength lasers could be targeted to source a carrier to multiple channels with the same source [225].

Suggestions for future work on complimentary silicon photonic components:

• Building block circuits with ”no change” MESFETs including low pass feedback

for self tuning modulator bias circuit

• Ring-based MUX/Demux with monolithically integrated feedback control cir-

cuits using no-change transistors.

• Flip-chip laser with active isolator for improved back-reﬂection tolerance.

• Coherent laser with high temperature range using quantum dot gain media.

• Four-channel 50 Gbps/channel using a single multi-wavelength source.

Future Silicon Photonic Systems

The demonstration in Chapter 7 was limited in that it didn’t show a complete module, but instead showed the main building blocks of such a module working together.

Future work could complete this integration: the laser, transmitter and receiver all

109 integrated in the same compact assembly.

Further area for significant work is in the datacenter space which is growing at an even faster pace that telecommunications. Packaging and integration challenges continue to be at the forefront of new system design. Techniques such as passive fiber alignment, high volume bonding, non-hermetic packaging and chip-on-chip assembly will be of great interest in the effort to reduce cost and footprint while increasing aggregate bandwidth.

The challenge will then be to address additional application spaces. These new areas will open up as performance increases. Constraints on memory bandwidth will push innovation into optically interconnected memory [226]. Requirements for supercomputers will encourage development in optics for high performance computing

[227]. The final frontier of inter-chip optical communication [228] needs significant work to see commercial applications, although the first optically-enabled CPUs have already been demonstrated [229].

Speciﬁc recommendations for follow-up work:

• Integration of Tx, Rx and Laser into a single compact optical engine package

for coherent optics.

• Flip chip laser array for dense optically connected memory demonstration

• Compact optical interface for a CPU, built with ﬂip chip lasers onto a silicon

photonics interposer.

110 8.3 Final Remarks

Silicon photonics has come a long way in a few short years. The standard devices: passives, photodetectors and modulators are no longer in a mode of being improved in a vacuum. Instead it is the integration of these components with electronics and optical gain in new ways that provides a path forward in terms of increased performance. As costs decrease, silicon photonics will become competitive as a technology for shorter optical links with larger manufacturing volumes. These new use cases will open the door for more opportunities for innovation in silicon photonic optical links.

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