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Chapter 8 Instruction Set
Chapter 8 Instruction Set 80 80 This chapter lists the PowerPC instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level(s) of the PowerPC architecture in which the instruction may be found—user instruction set architecture (UISA), virtual environment architecture U (VEA), and operating environment architecture (OEA); and the privilege level of the V instruction—user- or supervisor-level (an instruction is assumed to be user-level unless the O legend specifies that it is supervisor-level); and the instruction formats. The format diagrams show, horizontally, all valid combinations of instruction fields; for a graphical representation of these instruction formats, see Appendix A, “PowerPC Instruction Set Listings.” The legend also indicates if the instruction is 64-bit, , 64-bit bridge, and/or optional. A description of the instruction fields and pseudocode conventions are also provided. For more information on the PowerPC instruction set, refer to Chapter 4, “Addressing Modes and Instruction Set Summary.” Note that the architecture specification refers to user-level and supervisor-level as problem state and privileged state, respectively. 8.1 Instruction Formats Instructions are four bytes long and word-aligned, so when instruction addresses are U presented to the processor (as in branch instructions) the two low-order bits are ignored. Similarly, whenever the processor develops an instruction address, its two low-order bits are zero. Bits 0–5 always specify the primary opcode. Many instructions also have an extended opcode. The remaining bits of the instruction contain one or more fields for the different instruction formats. -
Fill Your Boots: Enhanced Embedded Bootloader Exploits Via Fault Injection and Binary Analysis
IACR Transactions on Cryptographic Hardware and Embedded Systems ISSN 2569-2925, Vol. 2021, No. 1, pp. 56–81. DOI:10.46586/tches.v2021.i1.56-81 Fill your Boots: Enhanced Embedded Bootloader Exploits via Fault Injection and Binary Analysis Jan Van den Herrewegen1, David Oswald1, Flavio D. Garcia1 and Qais Temeiza2 1 School of Computer Science, University of Birmingham, UK, {jxv572,d.f.oswald,f.garcia}@cs.bham.ac.uk 2 Independent Researcher, [email protected] Abstract. The bootloader of an embedded microcontroller is responsible for guarding the device’s internal (flash) memory, enforcing read/write protection mechanisms. Fault injection techniques such as voltage or clock glitching have been proven successful in bypassing such protection for specific microcontrollers, but this often requires expensive equipment and/or exhaustive search of the fault parameters. When multiple glitches are required (e.g., when countermeasures are in place) this search becomes of exponential complexity and thus infeasible. Another challenge which makes embedded bootloaders notoriously hard to analyse is their lack of debugging capabilities. This paper proposes a grey-box approach that leverages binary analysis and advanced software exploitation techniques combined with voltage glitching to develop a powerful attack methodology against embedded bootloaders. We showcase our techniques with three real-world microcontrollers as case studies: 1) we combine static and on-chip dynamic analysis to enable a Return-Oriented Programming exploit on the bootloader of the NXP LPC microcontrollers; 2) we leverage on-chip dynamic analysis on the bootloader of the popular STM8 microcontrollers to constrain the glitch parameter search, achieving the first fully-documented multi-glitch attack on a real-world target; 3) we apply symbolic execution to precisely aim voltage glitches at target instructions based on the execution path in the bootloader of the Renesas 78K0 automotive microcontroller. -
Book E: Enhanced Powerpc™ Architecture
Book E: Enhanced PowerPC Architecture Version 1.0 May 7, 2002 Third Edition (Dec 2001) The following paragraph does not apply to the United Kingdom or any country where such provisions are inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS DOCUMENT “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied warranties in certain transactions; therefore, this statement may not apply to you. IBM does not warrant that the use of the information herein shall be free from third party intellectual property claims. IBM does not warrant that the contents of this document will meet your requirements or that the document is error-free. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the document. IBM may make improvements and or changes in the product(s) and/or program(s) described in this document at any time. This document does not imply a commitment by IBM to supply or make generally available the product(s) described herein. No part of this document may be reproduced or distributed in any form or by any means, or stored in a data base or retrieval system, without the written permission of IBM. Address comments about this document to: IBM Corporation Department B5H / Building 667 3039 Cornwallis Road P.O. Box 12195 Research Triangle Park, NC 27709 Portions of the information in this document may have been published previously in the following related documents: The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition (1994) The IBM PowerPC Embedded Environment: Architectural Specifications for IBM PowerPC Embedded Controllers, Second Edition (1998) IBM may have patents or pending patent applications covering the subject matter in this document. -
AVR32 EVK1105 Evaluation Kit
Your Electronic Engineering Resource ATMEL - ATEVK1105 - AVR32 EVK1105 Evaluation Kit Product Overview: The AVR32 EVK1105 is an evaluation kit for the AT32UC3A3256 which combines Atmel’s state of art AVR32 microcontroller with an unrivalled selection of communication interface like USB device including On-The-Go functionality, SDcard, NAND flash with ECC and stereo 16-bit DAC. The AVR32 EVK1105 is an evaluation kit for the AT32UC3A0512 which demonstrates Atmel’s state-of-the-art AVR32 microcontroller in Hi-Fi audio decoding and streaming applications. Kit Contents: The kit contains reference hardware and software for generic MP3 player docking stations. Key Features: High Performance, Low Power AVR®32 UC 32-Bit Microcontroller Multi-Layer Bus System Internal High-Speed Flash Internal High-Speed SRAM Interrupt Controller Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), Watchdog Timer, Real-Time Clock Timer External Memories MultiMediaCard (MMC), Secure-Digital (SD), SDIO V1.1 CE-ATA, FastSD, SmartMedia, Compact Flash Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S and AT32UC3A364S Universal Serial Bus (USB) One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Legal Disclaimer: The content of the pages of this website is for your general information and use only. It is subject to change without notice. From time to time, this website may also include links to other websites. These links are provided for your convenience to provide further information. They do not signify that we endorse the website(s). -
Schedule 14A Employee Slides Supertex Sunnyvale
UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 SCHEDULE 14A Proxy Statement Pursuant to Section 14(a) of the Securities Exchange Act of 1934 Filed by the Registrant Filed by a Party other than the Registrant Check the appropriate box: Preliminary Proxy Statement Confidential, for Use of the Commission Only (as permitted by Rule 14a-6(e)(2)) Definitive Proxy Statement Definitive Additional Materials Soliciting Material Pursuant to §240.14a-12 Supertex, Inc. (Name of Registrant as Specified In Its Charter) Microchip Technology Incorporated (Name of Person(s) Filing Proxy Statement, if other than the Registrant) Payment of Filing Fee (Check the appropriate box): No fee required. Fee computed on table below per Exchange Act Rules 14a-6(i)(1) and 0-11. (1) Title of each class of securities to which transaction applies: (2) Aggregate number of securities to which transaction applies: (3) Per unit price or other underlying value of transaction computed pursuant to Exchange Act Rule 0-11 (set forth the amount on which the filing fee is calculated and state how it was determined): (4) Proposed maximum aggregate value of transaction: (5) Total fee paid: Fee paid previously with preliminary materials. Check box if any part of the fee is offset as provided by Exchange Act Rule 0-11(a)(2) and identify the filing for which the offsetting fee was paid previously. Identify the previous filing by registration statement number, or the Form or Schedule and the date of its filing. (1) Amount Previously Paid: (2) Form, Schedule or Registration Statement No.: (3) Filing Party: (4) Date Filed: Filed by Microchip Technology Incorporated Pursuant to Rule 14a-12 of the Securities Exchange Act of 1934 Subject Company: Supertex, Inc. -
Corecommander for Microprocessors and Microcontrollers
CORECOMMANDER FOR MICROPROCESSORS AND MICROCONTROLLERS Factsheet Direct access to memory and peripheral devices (I/O) for testing, debugging and in-system programming • Direct access to memory and peripheral (I/O) devices of a micro- processor through its (JTAG) debug interface • Read data from, write data to memory and peripherals without software programming • At-speed execution of read and write cycles • Testing and debugging of the connectivity of processor memory and peripherals with at-speed bus cycles without software programming • Easy programming of processor flash memory without software programming Corecommander provides high-level functions to write data to and read data from microprocessor memory Order information CoreComm Micro (core) and I/O addresses without software programming. (core) = ARM 7, ARM 9, ARM 11, Cortex-A, Cortex-R, CoreCommander functions are applied via the JTAG Cortex-M, Blackfin, PXA2xx, PXA3xx, IXP4xx, PowerPC- interface. MPC500 family, PowerPC-MPC5500 family, PowerPC- MPC5600 family, C28x, XC166, Tricore, PIC32 Applications CoreCommander is used in design debug, manufactu- ring test and (field) service for many different applica- [1] if the uProcessor also contains a boundary-scan register then teh tests and in-system tions such as: programming operations can also be done using the boundary-scan register instead of the CoreCommander. Whether in that case the CoreCommander or the boundary-scan register is used depends on preference or performance. • Diagnosing “dead-kernel” boards; no embedded code is required to perform memory reads and Background writes. A uP performs read and write operations on its bus to ac- cess memory and I/O locations. The read and write cycles • Determining the right settings for the peripheral normally result when the uP executes a program that is controller (DDR controller, flash memory controller, stored in memory. -
Implementing Powerpc Linux on System I Platform
Front cover Implementing POWER Linux on IBM System i Platform Planning and configuring Linux servers on IBM System i platform Linux distribution on IBM System i Platform installation guide Tips to run Linux servers on IBM System i platform Yessong Johng Erwin Earley Rico Franke Vlatko Kosturjak ibm.com/redbooks International Technical Support Organization Implementing POWER Linux on IBM System i Platform February 2007 SG24-6388-01 Note: Before using this information and the product it supports, read the information in “Notices” on page vii. Second Edition (February 2007) This edition applies to i5/OS V5R4, SLES10 and RHEL4. © Copyright International Business Machines Corporation 2005, 2007. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . vii Trademarks . viii Preface . ix The team that wrote this redbook. ix Become a published author . xi Comments welcome. xi Chapter 1. Introduction to Linux on System i platform . 1 1.1 Concepts and terminology . 2 1.1.1 System i platform . 2 1.1.2 Hardware management console . 4 1.1.3 Virtual Partition Manager (VPM) . 10 1.2 Brief introduction to Linux and Linux on System i platform . 12 1.2.1 Linux on System i platform . 12 1.3 Differences between existing Power5-based System i and previous System i models 13 1.3.1 Linux enhancements on Power5 / Power5+ . 14 1.4 Where to go for more information . 15 Chapter 2. Configuration planning . 17 2.1 Concepts and terminology . 18 2.1.1 Processor concepts . -
A Developer's Guide to the POWER Architecture
http://www.ibm.com/developerworks/linux/library/l-powarch/ 7/26/2011 10:53 AM English Sign in (or register) Technical topics Evaluation software Community Events A developer's guide to the POWER architecture POWER programming by the book Brett Olsson , Processor architect, IBM Anthony Marsala , Software engineer, IBM Summary: POWER® processors are found in everything from supercomputers to game consoles and from servers to cell phones -- and they all share a common architecture. This introduction to the PowerPC application-level programming model will give you an overview of the instruction set, important registers, and other details necessary for developing reliable, high performing POWER applications and maintaining code compatibility among processors. Date: 30 Mar 2004 Level: Intermediate Also available in: Japanese Activity: 22383 views Comments: The POWER architecture and the application-level programming model are common across all branches of the POWER architecture family tree. For detailed information, see the product user's manuals available in the IBM® POWER Web site technical library (see Resources for a link). The POWER architecture is a Reduced Instruction Set Computer (RISC) architecture, with over two hundred defined instructions. POWER is RISC in that most instructions execute in a single cycle and typically perform a single operation (such as loading storage to a register, or storing a register to memory). The POWER architecture is broken up into three levels, or "books." By segmenting the architecture in this way, code compatibility can be maintained across implementations while leaving room for implementations to choose levels of complexity for price/performances trade-offs. The levels are: Book I. -
PDF 19308 Kb ADSP-Bf50x Blackfin ® Processor Hardware Reference
ADSP-BF50x Blackfin® Processor Hardware Reference Revision 1.2, February 2013 Part Number 82-100101-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu- ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual .................................................................. li Intended Audience .......................................................................... li Manual Contents ........................................................................... lii What’s New in This Manual ........................................................... lv Technical Support ......................................................................... -
Getting the Most out of Your Professional RISC-V Compiler and Debugger
Getting the most out of your professional RISC-V compiler and debugger Ryan Sheng / 盛磊, [email protected], 021-63758658 IAR Systems (China) 2019.11.13 Highlight . Meet the demand of quality & time-to-market for your RISC-V project . Easy code reuse and widest customers base from IAR Embedded Workbench, the complete IDE toolchain . Fit the needs of both memory size and necessary performance by the outstanding C/C++ compiler . Improve the code quality and find potential issues earlier by the integrated C-STAT analysis . Identify low level bugs and provide graphical visibility to all SoC resource by the powerful debugger IAR Embedded Workbench Complete C/C++ compiler and debugger toolchain Most widely used development tools for embedded applications User-friendly IDE features and broad ecosystem integration Industry leading code optimization technology Comprehensive debugger Integrated code analysis tools ISO/ANSI C/C++ compliance with C18 and C++17 Support for 12,000+ devices Different architecture, One solution All available 8-,16- and 32-bit MCUs Cortex-M0 Cortex-R8 AVR H8 Cortex-M0+ Cortex-A5 AVR32 STM8 Cortex-M1 Cortex-A7 RX ColdFire Cortex-M3 Cortex-A8 RL78 HCS12 Cortex-M4 Cortex-A9 RH850 S08 Cortex-M7 Cortex-A15 78K MAXQ Cortex-M23 ARM11 SuperH CR16C Cortex-M33 ARM9 V850 SAM8 Cortex-R4 ARM7 R32C RISC-V Cortex-R5 SecurCore M32C Cortex-R52 8051 M16C Cortex-R7 MSP430 R8C Compiler optimizations x = y - 15; Function C Source inlining Dead code elimination Parser Compiler Loop = unrolling Intermediate Code High-Level Optimizer x – Scheduling y 15 Code Generator Low-Level Peephole Target Code Optimizer c.mv a3, sp Crosscall c.li a1, 1 Assembler lui a0, 0x80002 Link time optimizations 01001000111001101001 Object Code Linker Controlling optimizations Multi-file compilation allows Language standards the optimizer to operate on . -
V850 Series Development Environment Pamphlet
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. -
Palmice3 V850 Apr
Product Summary PALMiCE3 V850 Apr. 1, 2014 (1/1) JTAG emulator PALMiCE3 V850 PALMiCE3 V850 is a JTAG emulator that incorporates on-chip debugging function in Renesas Electronics-made V850. It supports USB2.0 (High-speed) as the host interface, and the Vbus which requires no power supply. Furthermore, PALMiCE3 V850 has a palm-sized, light and compact body, providing excellent portability to support you with debugging. As for the debugger, it surely incorporates CSIDE, which provides a user-friendly debugging environment. CSIDE supports not only high-level language debugging of a range of C languages but also a wide range of debugging environments by optional debug libraries. Support for SuperH family and H8S/H8SX family are also available with optional CSIDEs. ■ Supports V850 ■ Real-time watcher feature (Optional) ■ Supports USB2.0(High-speed), allowing high-speed ■ Simulated I/O feature processing ■ Allows access to memory and I/O during break ■ A palm-sized, compact body ■ Supports debugging on on-chip/external flash memories ■ Requires no power supply with Vbus support Main Specifications Supporting model HUDI141(JTAG) model Supported CPUs *1 V850E2/MN4, V850E2/ML4 JTAG clock Can be set freely in 1MHz increments between 1MHz and 25MHz. Voltage 1.65V - 5.5V (Follows target) Measures by sampling and shows the results with accuracy of 50mV Target I/F Voltage measurement and precision showing 2 decimal places. Connector 14-pin MIL connector Supports referencing/editing of register and downloading to memory during break. Register, memory, I/O operation It supports referencing/editing of memory and I/O even during execution of the user program.