Ltc1929/Lt1929-Pg

LTC1929/LTC1929-PG 2-Phase, High Efficiency, Synchronous Step-Down Switching Regulators

FEATURES DESCRIPTIO U ■ 2-Phase Single Output Controller The LTC®1929/LTC1929-PG are 2-phase, single output, ■ Reduces Required Input Capacitance and Power synchronous step-down current mode switching regula- Supply Induced Noise tor controllers that drive N-channel external power MOSFET ■ Current Mode Control Ensures Current Sharing stages in a phase-lockable fixed frequency architecture. ■ Phase-Lockable Fixed Frequency: 150kHz to 300kHz The 2-phase controllers drive their two output stages out ■ True Remote Sensing Differential Amplifier of phase at frequencies up to 300kHz to minimize the RMS ■ OPTI-LOOPTM Compensation Improves Transient ripple currents in both input and output capacitors. The Response 2-phase technique effectively multiplies the fundamental ■ ±1% Output Voltage Accuracy frequency by two, improving transient response while ■ Power Good Output Voltage Monitor (LTC1929-PG) operating each channel at an optimum frequency for ■ Wide VIN Range: 4V to 36V Operation efficiency. Thermal design is also simplified. ■ Very Low Dropout Operation: 99% Duty Cycle An internal differential amplifier provides true remote ■ Adjustable Soft-Start Current Ramping sensing of the regulated supply’s positive and negative ■ Internal Current Foldback output terminals as required by high current applications. ■ Short-Circuit Shutdown Timer with Defeat Option ■ Overvoltage Soft-Latch Eliminates Nuisance Trips The RUN/SS pin provides soft-start and a defeatable,

■ Available in 28-Lead SSOP Package timed, latched short-circuit shutdown to shut down both U channels. Internal foldback current limit provides protec- APPLICATIO S tion for the external synchronous MOSFETs in the event of an output fault. OPTI-LOOP compensation allows the ■ Desktop Computers transient response to be optimized over a wide range of ■ Internet/Network Servers output capacitance and ESR values. ■ Large Memory Arrays , LTC and LT are registered trademarks of Linear Technology Corporation. ■ DC Power Distribution Systems OPTI-LOOP is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO U 10Ω VIN µ 5V TO 28V µ 10 F 0.1 F 35V CERAMIC V TG1 IN ×4 BOOST1 0.1µF 0.47µF LTC1929 SW1 L1 0.002Ω RUN/SS 1µH BG1 D1 1000pF PGND SENSE1+ I TH SENSE1– 10k 100pF TG2 SGND BOOST2 0.47µF VOUT 1.6V/40A 16k SW2 L2 0.002Ω 1µH VDIFFOUT BG2 D2 EAIN INTVCC µ + 10 F C – + + OUT 16k VOS SENSE2 1000µF + – 4V VOS SENSE2 ×2

C : T510E108K004AS L1, L2: CEPH149-1ROMC OUT 1929 F01 Figure 1. High Current 2-Phase Step-Down Converter 1

LTC1929/LTC1929-PG

WW U W W

ABSOLUTE AXI U RATI GS PACKAGE/ORDER IUU FOR ATIO (Note 1) TOP VIEW ORDER PART Input Supply Voltage (VIN)...... 36V to –0.3V Topside Driver Voltages (BOOST1,2)...... 42V to –0.3V RUN/SS 1 28 NC NUMBER Switch Voltage (SW1, 2) ...... 36V to –5 V SENSE1+ 2 27 TG1 – LTC1929CG SENSE1+, SENSE2 +, SENSE1–, SENSE1 3 26 SW1 – EAIN 4 25 BOOST1 LTC1929CG-PG SENSE2 Voltages...... (1.1)INTVCC to –0.3V + – PLLFLTR 5 24 VIN LTC1929IG EAIN, VOS , VOS , EXTVCC, INTVCC, PLLIN 6 23 BG1 LTC1929IG-PG RUN/SS, AMPMD Voltages...... 7V to –0.3V NC 7 22 EXTV Boosted Driver Voltage (BOOST-SW) ...... 7V to –0.3V CC ITH 8 21 INTVCC PLLFLTR, PLLIN, VDIFFOUT Voltages .... INTVCC to –0.3V SGND 9 20 PGND ITH Voltage ...... 2.7V to –0.3V V 10 19 BG2 µ DIFFOUT Peak Output Current <1 s(TGL1,2, BG1,2)...... 3A VOS– 11 18 BOOST2

INTVCC RMS Output Current...... 50mA VOS+ 12 17 SW2 Operating Ambient Temperature Range SENSE2– 13 16 TG2 LTC1929C ...... 0°C to 85°C SENSE2+ 14 15 AMPMD* ° ° LTC1929I ...... –40 C to 85 C G PACKAGE Junction Temperature (Note 2)...... 125°C 28-LEAD PLASTIC SSOP Storage Temperature Range ...... –65°C to 150°C *PGOOD ON LTC1929-PG ° θ ° Lead Temperature (Soldering, 10 sec)...... 300°C TJMAX = 125 C, JA = 95 C/W Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop

VEAIN Regulated Feedback Voltage (Note 3); ITH Voltage = 1.2V ● 0.792 0.800 0.808 V – VSENSEMAX Maximum Current Sense Threshold VSENSE = 5V ● 62 75 88 mV VSENSE1, 2 = 5V, LTC1929 Only 65 75 85 mV

IINEAIN Feedback Current (Note 3) –5 – 50 nA

VLOADREG Output Voltage Load Regulation (Note 3) Measured in Servo Loop; ITH Voltage = 0.7V ● 0.05 0.5 % Measured in Servo Loop; ITH Voltage = 2V ● –0.1 –0.5 %

VREFLNREG Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.002 0.02 %/V

VOVL Output Overvoltage Threshold Measured at VEAIN 0.84 0.86 0.88 V

UVLO Undervoltage Lockout VIN Ramping Down 3 3.5 4 V gm Transconductance Amplifier gm ITH = 1.2V; Sink/Source 5µA; (Note 3) 3 mmho gmOL Transconductance Amplifier Gain ITH = 1.2V; (gmxZL; No Ext Load); (Note 3) 1.5 V/mV

IQ Input DC Supply Current (Note 4) Normal Mode EXTVCC Tied to VOUT; VOUT = 5V 470 µA Shutdown VRUN/SS = 0V 20 40 µA

IRUN/SS Soft-Start Charge Current VRUN/SS = 1.9V –0.5 –1.2 µA

VRUN/SS RUN/SS Pin ON Threshold VRUN/SS Rising 1.0 1.5 1.9 V

VRUN/SSLO RUN/SS Pin Latchoff Arming VRUN/SS Rising from 3V 4.1 4.5 V

2 LTC1929/LTC1929-PG

ISCL RUN/SS Discharge Current Soft Short Condition VEAIN = 0.5V; 0.5 2.0 4.0 µA VRUN/SS = 4.5V

ISDLHO Shutdown Latch Disable Current VEAIN = 0.5V 1.6 5 µA

ISENSE Total Sense Pins Source Current Each Channel: VSENSE1–, 2 – = VSENSE1+, 2+ = 0V – 85 – 60 µA

DFMAX Maximum Duty Factor In Dropout 98 99.5 % Top Gate Transition Time: TG1, 2 tr Rise Time CLOAD = 3300pF 30 90 ns TG1, 2 tf Fall Time CLOAD = 3300pF 40 90 ns Bottom Gate Transition Time: BG1, 2 tr Rise Time CLOAD = 3300pF 30 90 ns BG1, 2 tf Fall Time CLOAD = 3300pF 20 90 ns

TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 90 ns

BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver 90 ns tON(MIN) Minimum On-Time Tested with a Square Wave (Note 6) 180 ns

Internal VCC Regulator

VINTVCC Internal VCC Voltage 6V < VIN < 30V; VEXTVCC = 4V 4.8 5.0 5.2 V

VLDO INT INTVCC Load Regulation ICC = 0 to 20mA; VEXTVCC = 4V 0.2 1.0 %

VLDO EXT EXTVCC Voltage Drop ICC = 20mA; VEXTVCC = 5V 120 240 mV VLDO EXT-PG EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V, LTC1929-PG 80 160 mV

VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive ● 4.5 4.7 V

VLDOHYS EXTVCC Switchover Hysteresis ICC = 20mA, EXTVCC Ramping Negative 0.2 V Oscillator and Phase-Locked Loop fNOM Nominal Frequency VPLLFLTR = 1.2V 190 220 250 kHz fLOW Lowest Frequency VPLLFLTR = 0V 120 140 160 kHz fHIGH Highest Frequency VPLLFLTR ≥ 2.4V 280 310 360 kHz

RPLLIN PLLIN Input Resistance 50 kΩ

IPLLFLTR Phase Detector Output Current Sinking Capability fPLLIN < fOSC –15 µA Sourcing Capability fPLLIN > fOSC 15 µA

RRELPHS Controller 2-Controller 1 Phase 180 Deg PGOOD Output (LTC1929-PG Only)

VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA VPG PGOOD Trip Level VEAIN with Respect to Set Output Voltage VEAIN Ramping Negative –6 –7.5 –9.5 % VEAIN Ramping Positive 6 7.5 9.5 % Differential Amplifier/Op Amp Gain Block (Note 5)

ADA Gain Differential Amp Mode 0.995 1 1.005 V/V

CMRRDA Common Mode Rejection Ratio Differential Amp Mode; 0V < VCM < 5V 46 55 dB

RIN Input Resistance Differential Amp Mode; Measured at VOS+ Input 80 kΩ

VOS Input Offset Voltage Op Amp Mode; VCM = 2.5V; VDIFFOUT = 5V; 6 mV IDIFFOUT = 1mA (LTC1929 Only) 3 LTC1929/LTC1929-PG

IB Input Bias Current Op Amp Mode (LTC1929 Only) 30 200 nA

AOL Open Loop DC Gain Op Amp Mode; 0.7V ≤ VDIFFOUT < 10V 5000 V/mV (LTC1929 Only)

VCM Common Mode Input Voltage Range Op Amp Mode (LTC1929 Only) 0 3 V

CMRROA Common Mode Rejection Ratio Op Amp Mode; 0V < VCM < 3V (LTC1929 Only) 70 90 dB

PSRROA Power Supply Rejection Ratio Op Amp Mode; 6V < VIN < 30V (LTC1929 Only) 70 90 dB

ICL Maximum Output Current Op Amp Mode; VDIFFOUT = 0V (LTC1929 Only) 10 35 mA

VO(MAX) Maximum Output Voltage Op Amp Mode; IDIFFOUT = 1mA (LTC1929 Only) 10 11 V

GBW Gain-Bandwidth Product Op Amp Mode; IDIFFOUT = 1mA (LTC1929 Only) 2 MHz

SR Slew Rate Op Amp Mode; RL = 2k (LTC1929 Only) 5 V/µs

Note 1: Absolute Maximum Ratings are those values beyond which the Note 5: When the AMPMD pin is high (default for the LTC1929-PG), the life of a device may be impaired. LTC1929 IC pins are connected directly to the internal op amp inputs.

Note 2: TJ is calculated from the ambient temperature TA and power When the AMPMD pin is low, internal MOSFET switches connect four dissipation PD according to the following formulas: 40k resistors around the op amp to create a standard unity-gain differential amp. LTC1929CG: TJ = TA + (PD • 95°C/W) Note 6: Minimum on-time condition corresponds to the on inductor Note 3: The LTC1929 is tested in a feedback loop that servos VITH to a peak-to-peak ripple current ≥40% of IMAX (see minimum on-time specified voltage and measures the resultant VEAIN. considerations in the Applications Information section). Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information.

TYPICAL PERFOR A CEUW CHARACTERISTICS

Efficiency vs Output Current Efficiency vs Output Current Efficiency vs VIN (Figure 13) (Figure 13) (Figure 13) 100 100 100 VEXTVCC = 5V IOUT = 20A VEXTVCC = 5V 80 90 80 VOUT = 2V VIN = 5V VEXTVCC = 0V VIN = 8V V = 1.6V 60 60 80 OUT VIN = 12V VIN = 20V 40 40 70 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)

20 20 60 VOUT = 2V VIN = 12V VEXTVCC = 0V VOUT = 2V FREQ = 200kHz FREQ = 200kHz 0 0 50 0.1 1 10 100 0.1 110 100 5 10 15 20 OUTPUT CURRENT (A) OUTPUT CURRENT (A) VIN (V)

1929 G01 1929 G02 1929 G03

4 LTC1929/LTC1929-PG

TYPICAL PERFOR A CEUW CHARACTERISTICS

Supply Current vs Input Voltage INTVCC and EXTVCC Switch and Mode EXTVCC Voltage Drop Voltage vs Temperature 1000 250 5.05 VOUT = 5V V = V INTVCC VOLTAGE EXTVCC OUT 5.00 800 200

A) 4.95 µ LTC1929 600 150 4.90

ON LTC1929-PG SWITCH VOLTAGE (V) CC 4.85 400 100 VOLTAGE DROP (mV)

CC 4.80 SUPPLY CURRENT ( AND EXTV 200 EXTV 50 EXTVCC SWITCHOVER THRESHOLD CC 4.75

SHUTDOWN INTV 0 0 4.70 0510 15 20 25 30 35 0 10 20 30 40 50 –50 –25 0 2550 75 100 125 INPUT VOLTAGE (V) CURRENT (mA) TEMPERATURE (°C)

1929 G04 1929 G05 1929 G06

Maximum Current Sense Threshold Maximum Current Sense Threshold vs Percent on Nominal Output Internal 5V LDO Line Reg vs Duty Factor Voltage (Foldback) 5.1 75 80 ILOAD = 1mA 5.0 70

60 4.9 50 50 4.8 (mV) (mV) 40 VOLTAGE (V) SENSE 4.7 SENSE CC V V 30 25

INTV 4.6 20

4.5 10

4.4 0 0 0 5101520 25 30 35 0 20 40 60 80 100 0 25 50 75 100 INPUT VOLTAGE (V) DUTY FACTOR (%) PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

1929 G07 1929 G08 1929 G09

Maximum Current Sense Threshold Maximum Current Sense Threshold Current Sense Threshold vs VRUN/SS (Soft-Start) vs Sense Common Mode Voltage vs ITH Voltage 80 80 90 V = 1.6V SENSE(CM) 80 70 76 60 60 50 72 40 (mV) (mV) (mV) 40 30 SENSE SENSE SENSE 68 20 V V V 10 20 0 64 –10 –20 0 60 –30 0 123456 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 VRUN/SS (V) COMMON MODE VOLTAGE (V) VITH (V)

1929 G10 1929 G11 1929 G12 5 LTC1929/LTC1929-PG

TYPICAL PERFOR A CEUW CHARACTERISTICS

Load Regulation VITH vs VRUN/SS SENSE Pins Total Source Current 0.0 2.5 100 VIN = 15V VOSENSE = 0.7V FIGURE 1 2.0 –0.1 50 (%) OUT 1.5 A) µ ( –0.2 (V) 0 ITH V SENSE 1.0 I

NORMALIZED V –0.3 –50 0.5

–0.4 0 –100 0 1 2 3 4 5 0 1 23456 0 246 LOAD CURRENT (A) VRUN/SS (V) VSENSE COMMON MODE VOLTAGE (V)

1629 G13 1629 G14 1629 G15

Maximum Current Sense Threshold vs Temperature RUN/SS Current vs Temperature 80 1.8 – VSENSE = 5V 1.6

78 1.4 A) µ 1.2 76 1.0 (mV) 0.8

SENSE 74 V 0.6 RUN/SS CURRENT ( 72 0.4 0.2

70 0 –50 –25 0 25 50 75 100 125 –50 –25 0 2550 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C)

1929 G16 1929 G17

Soft-Start (Figure 13) Load Step (Figure 13)

VITH 1V/DIV VOUT 50mV/DIV

VOUT 2V/DIV 20A VRUN/SS IOUT 2V/DIV 10A/DIV 0A

100ms/DIV 1929 G18 20µs/DIV 1929 G19

6 LTC1929/LTC1929-PG

TYPICAL PERFOR A CEUW CHARACTERISTICS

Current SENSE Pin Input Current EXTVCC Switch Resistance Oscillator Frequency vs Temperature vs Temperature vs Temperature 35 10 350 VOUT = 5V VFREQSET = 5V A) ) µ 300 33 Ω 8 250 VFREQSET = OPEN 31 6 200

V = 0V 29 4 150 FREQSET FREQUENCY (kHz) SWITCH RESISTANCE ( 100 CC 27 2

EXTV 50 CURRENT SENSE INPUT ( 25 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 2550 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

1929 G20 1929 G21 1929 G22

Undervoltage Lockout VRUN/SS Shutdown Latch vs Temperature Thresholds vs Temperature 3.50 4.5

4.0 LATCH ARMING 3.45 3.5

3.40 3.0 LATCHOFF THRESHOLD 2.5 3.35 2.0

3.30 1.5 1.0 UNDERVOLTAGE LOCKOUT (V) 3.25

SHUTDOWN LATCH THRESHOLDS (V) 0.5

3.20 0 –50 –25 0 2550 75 100 125 –50 –25 0 2550 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C)

1929 G23 1929 G24

7 LTC1929/LTC1929-PG

PI FU CTIO SUUU RUN/SS (Pin 1): Combination of Soft-Start, Run Control differential amplifier (default for the LTC1929-PG) or an Input and Short-Circuit Detection Timer. A capacitor to uncommitted Op Amp. ground at this pin sets the ramp time to full current output. AMPMD (Pin 15): (LTC1929 Only) This Logic Input pin Forcing this pin below 0.8V causes the IC to shut down all controls the connections of internal precision resistors internal circuitry. All functions are disabled in shutdown. that configure the operational amplifier as a unity-gain SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to the differential amplifier. Differential Current Comparators. The ITH pin voltage and – + PGOOD (Pin 15): (LTC1929-PG Only) Open-Drain Logic built-in offsets between SENSE and SENSE pins in Output. PGOOD is pulled to ground when the voltage on conjunction with RSENSE set the current trip threshold. the EAIN pin is not within ±7.5% of its set point. – – SENSE1 , SENSE2 (Pins 3, 13): The (–) Input to the TG2, TG1 (Pins 16, 27): High Current Gate Drives for Top Differential Current Comparators. N-Channel MOSFETS. These are the outputs of floating EAIN (Pin 4): Input to the Error Amplifier that compares drivers with a voltage swing equal to INTVCC superim- the feedback voltage to the internal 0.8V reference voltage. posed on the switch node voltage SW. This pin is normally connected to a resistive divider from SW2, SW1 (Pins 17, 26): Switch Node Connections to the output of the differential amplifier (DIFFOUT). Inductors. Voltage swing at these pins is from a Schottky PLLFLTR (Pin 5): The Phase-Locked Loop’s Low Pass diode (external) voltage drop below ground to VIN. Filter is tied to this pin. Alternatively, this pin can be driven BOOST2, BOOST1 (Pins 18, 25): Bootstrapped Supplies with an AC or DC voltage source to vary the frequency of to the Topside Floating Drivers. Capacitors are connected the internal oscillator. between the Boost and Switch pins, and Schottky diodes PLLIN (Pin 6): External Synchronization Input to Phase are tied between the Boost and INTVCC pins. Detector. This pin is internally terminated to SGND with BG2, BG1 (Pins 19, 23): Voltage Swing High Current Gate Ω 50k . The phase-locked loop will force the rising top gate Drives for Bottom Synchronous N-Channel MOSFETS. signal of controller 1 to be synchronized with the rising Voltage swing at these pins is from ground to INTV . edge of the PLLIN signal. CC PGND (Pin 20): Driver Power Ground. Connects to sources NC (Pins 7, 28): Not connected. of bottom N-channel MOSFETS and the (–) terminals of ITH (Pin 8): Error Amplifier Output and Switching Regula- CIN. tor Compensation Point. Both current comparator’s thresh- INTV (Pin 21): Output of the Internal 5V Linear Low olds increase with this control voltage. The normal voltage CC Dropout Regulator and the EXTVCC Switch. The driver and range of this pin is from 0V to 2.4V control circuits are powered from this voltage source. SGND (Pin 9): Signal Ground, common to both control- Decouple to power ground with a 1µF ceramic capacitor lers, must be routed separately from the input switched placed directly adjacent to the IC and minimum of 4.7µF current ground path to the common (–) terminal(s) of the additional tantalum or other low ESR capacitor. COUT capacitor(s). EXTVCC (Pin 22): External Power Input to an Internal VDIFFOUT (Pin 10): Output of a Differential Amplifier that Switch . This switch closes and supplies INTVCC, bypass- provides true remote output voltage sensing. This pin ing the internal low dropout regulator whenever EXTVCC is normally drives an external resistive divider that sets the higher than 4.7V. See EXTVCC Connection in the Applica- output voltage. tions Information section. Do not exceed 7V on this pin – + and ensure VEXTVCC ≤ VIN. VOS , VOS (Pins 11, 12): Inputs to an Operational Amplifier. Internal precision resistors capable of being VIN (Pin 24): Main Supply Pin. Should be closely decoupled electronically switched in or out can configure it as a to the IC’s signal ground pin. 8

LTC1929/LTC1929-PG W

FU CTIO ALUU DIAGRA

LTC1929-PG OPTIONAL PGOOD HOOKUP DIFFOUT PGOOD – 0.86V + V – OS EAIN A1 – – V + + 0.74V OS +

PLLIN INTVCC VIN F PHASE DET IN DUPLICATE FOR SECOND D BOOST B 50k CONTROLLER CHANNEL

PLLFLTR R LP TG CB CLK1 DROP TOP + OUT C OSCILLATOR IN CLK2 DET CLP BOT FORCE BOT SW S Q SWITCH INTVCC R Q LOGIC BG BOT

PGND

LTC1929 ONLY – VOS SHDN A1 V + – OS INTV I1 CC + – – + L + + 30k SENSE

4(V ) FB SENSE– R COUT AMPMD 30k SENSE

0V POSITION SLOPE + COMP 45k 45k DIFFOUT VOUT 2.4V

EAIN R1 VFB – EA 0.8V VREF VIN + 0.80V R2 V OV IN + 4.7V + 5V V – 0.86V C IN ITH C EXTVCC – LDO REG 1.2µA SHDN RUN RC INTVCC SOFT- 5V 4(V ) START + 6V FB

SGND INTERNAL RUN/SS SUPPLY

CSS

1929 FBD

9 LTC1929/LTC1929-PG

OPERATIOU (Refer to Functional Diagram) Main Control Loop Low Current Operation The LTC1929 uses a constant frequency, current mode The LTC1929 operates in a continuous, PWM control step-down architecture with inherent current sharing. mode. The resulting operation at low output currents During normal operation, the top MOSFET is turned on optimizes transient response at the expense of substantial each cycle when the oscillator sets the RS latch, and negative inductor current during the latter part of the turned off when the main current comparator, I1, resets period. The level of ripple current is determined by the the RS latch. The peak inductor current at which I1 resets inductor value, input voltage, output voltage, and fre- the RS latch is controlled by the voltage on the ITH pin, quency of operation. which is the output of the error amplifier EA. The differential amplifier, A1, produces a signal equal to the differential Frequency Synchronization voltage sensed across the output capacitor but re-refer- The phase-locked loop allows the internal oscillator to be ences it to the internal signal ground (SGND) reference. synchronized to an external source via the PLLIN pin. The The EAIN pin receives a portion of this voltage feedback output of the phase detector at the PLLFLTR pin is also the signal at the DIFFOUT pin which is compared to the DC frequency control input of the oscillator that operates internal reference voltage by the EA. When the load current over a 140kHz to 310kHz range corresponding to a DC increases, it causes a slight decrease in the EAIN pin voltage input from 0V to 2.4V. When locked, the PLL aligns voltage relative to the 0.8V reference, which in turn causes the turn on of the top MOSFET to the rising edge of the the ITH voltage to increase until the average inductor synchronizing signal. When PLLIN is left open, the PLLFLTR current matches the new load current. After the top pin goes low, forcing the oscillator to minimum frequency. MOSFET has turned off, the bottom MOSFET is turned on for the rest of the period. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn The top MOSFET drivers are biased from floating boot- from the input capacitor is effectively divided by two and strap capacitor CB, which normally is recharged during power loss is proportional to the RMS current squared. A each off cycle through an external Schottky diode. When two stage, single output voltage implementation can re- VIN decreases to a voltage close to VOUT, however, the loop duce input path power loss by 75% and radically reduce may enter dropout and attempt to turn on the top MOSFET the required RMS current rating of the input capacitor(s). continuously. A dropout detector detects this condition and forces the top MOSFET to turn off for about 400ns INTVCC/EXTVCC Power every 10th cycle to recharge the bootstrap capacitor. Power for the top and bottom MOSFET drivers and most The main control loop is shut down by pulling Pin 1 (RUN/ of the IC circuitry is derived from INTVCC. When the µ SS) low. Releasing RUN/SS allows an internal 1.2 A EXTVCC pin is left open, an internal 5V low dropout current source to charge soft-start capacitor CSS. When regulator supplies INTVCC power. If the EXTVCC pin is CSS reaches 1.5V, the main control loop is enabled with the taken above 4.7V, the 5V regulator is turned off and an ITH voltage clamped at approximately 30% of its maximum internal switch is turned on connecting EXTVCC to INTVCC. value. As CSS continues to charge, ITH is gradually re- This allows the INTVCC power to be derived from a high leased allowing normal operation to resume. When the efficiency external source such as the output of the regu- RUN/SS pin is low, all LTC1929 functions are shut down. lator itself or a secondary winding, as described in the If VOUT has not reached 70% of its nominal value when CSS Applications Information section. An external Schottky has charged to 4.1V, an overcurrent latchoff can be diode can be used to minimize the voltage drop from invoked as described in the Applications Information EXTVCC to INTVCC in applications requiring greater than section. the specified INTVCC current. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability.

10 LTC1929/LTC1929-PG

OPERATIOU (Refer to Functional Diagram) Differential Amplifier output meets the ±7.5% requirement, the MOSFET is turned off within 10µs and the pin is allowed to be pulled This amplifier provides true differential output voltage + – up by an external source. sensing. Sensing both VOUT and VOUT benefits regulation in high current applications and/or applications hav- Short-Circuit Detection ing electrical interconnection losses. The AMPMD pin (LTC1929 only) allows selection of internal, precision feed- The RUN/SS capacitor is used initially to limit the inrush back resistors for high common mode rejection differencing current from the input power source. Once the controllers applications, or direct access to the actual amplifier inputs have been given time, as determined by the capacitor on without these internal feedback resistors for other applica- the RUN/SS pin, to charge up the output capacitors and tions. The AMPMD pin is grounded to connect the internal provide full load current, the RUN/SS capacitor is then precision resistors in a unity-gain differencing application used as a short-circuit timeout circuit. If the output voltage (default for the LTC1929-PG), or tied to the INTVCC pin to falls to less than 70% of its nominal output voltage the bypass the internal resistors and make the amplifier inputs RUN/SS capacitor begins discharging assuming that the directly available. The amplifier is a unity-gain stable, 2MHz output is in a severe overcurrent and/or short-circuit gain-bandwidth, >120dB open-loop gain design. The am- condition. If the condition lasts for a long enough period plifier has an output slew rate of 5V/µs and is capable of as determined by the size of the RUN/SS capacitor, the driving capacitive loads with an output RMS current typi- controller will be shut down until the RUN/SS pin voltage cally up to 25mA. The amplifier is not capable of sinking is recycled. This built-in latchoff can be overidden by current and therefore must be resistively loaded to do so. providing a current >5µA at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period Power Good (PGOOD) Pin (LTC1929-PG Only) but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condi- The PGOOD pin is connected to an open drain of a tion. Foldback current limiting is activated when the output MOSFET. The MOSFET turns on and pulls the pin low when voltage falls below 70% of its nominal level whether or not the output is not within ±7.5% of its nominal output level

the short-circuit latchoff circuit is enabled. as determined by its resistive feedback divider. When the

U U

APPLICATIO S I FOR ATIOWU

The basic LTC1929 application circuit is shown in Figure␣ 1 RSENSE Selection For Output Current on the first page. External component selection is driven R are chosen based on the required output by the load requirement, and begins with the selection of SENSE1, 2 current. The LTC1929 current comparator has a maxi- R SENSE1, 2. Once RSENSE1, 2 are known, L1 and L2 can be mum threshold of 75mV/R and an input common chosen. Next, the power MOSFETs and D1 and D2 are SENSE mode range of SGND to 1.1( INTV ). The current com- selected. The operating frequency and the inductor are CC parator threshold sets the peak inductor current, yielding chosen based mainly on the amount of ripple current. a maximum average output current I equal to the peak Finally, C MAX IN is selected for its ability to handle the input value less half the peak-to-peak ripple current, ∆I . ripple current (that PolyPhaseTM operation minimizes) and L COUT is chosen with low enough ESR to meet the output Allowing a margin for variations in the LTC1929 and ripple voltage and load step specifications (also minimized external component values yields: with PolyPhase). Current mode architecture provides in- RSENSE = 2(50mV/IMAX) herent current sharing between output stages. The circuit shown in Figure␣ 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). PolyPhase is a trademark of Linear Technology Corporation. 11

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIOWU When using the controller in very low dropout conditions, MOSFET gate charge and transition losses. In addition to the maximum output current level will be reduced due to this basic tradeoff, the effect of inductor value on ripple internal compensation required to meet stability criterion current and low current operation must also be considered. for buck regulators operating at greater than 50% duty The PolyPhase approach reduces both input and output factor. A curve is provided to estimate this reduction in ripple currents while optimizing individual output stages to peak output current level depending upon the operating run at a lower fundamental frequency, enhancing efficiency. duty factor. The inductor value has a direct effect on ripple current. The inductor ripple current ∆I Operating Frequency L per individual section, N, decreases with higher inductance or frequency and in- The LTC1929 uses a constant frequency, phase-lockable creases with higher VIN or VOUT: architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus   ∆ =−VOUTV OUT an additional current which is proportional to the voltage IL 1  fL  V  applied to the PLLFLTR pin. Refer to Phase-Locked Loop IN and Frequency Synchronization in the Applications Infor- where f is the individual output stage operating frequency. mation section for additional information. In a 2-phase converter, the net ripple current seen by the A graph for the voltage applied to the PLLFLTR pin vs output capacitor is much smaller than the individual frequency is given in Figure␣ 2. As the operating frequency inductor ripple currents due to the ripple cancellation. The is increased the gate charge losses will be higher, reducing details on how to calculate the net output ripple current efficiency (see Efficiency Considerations). The maximum can be found in Application Note 77. switching frequency is approximately 310kHz. Figure 3 shows the net ripple current seen by the output 2.5 capacitors for the 1- and 2-phase configurations. The output ripple current is plotted for a fixed output voltage as 2.0 the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the 1.5 inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations, simplifying the 1.0 design process.

PLLFLTR PIN VOLTAGE (V) 0.5 1.0 0.9 1-PHASE 2-PHASE 0 120 170 220 270 320 0.8 OPERATING FREQUENCY (kHz) 0.7

1929 F02 0.6 /fL

O 0.5 O(P-P) I Figure 2. Operating Frequency vs V V PLLFLTR ∆ 0.4 0.3 Inductor Value Calculation and Output Ripple Current 0.2 The operating frequency and inductor selection are inter- 0.1 0 related in that higher operating frequencies allow the use 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 of smaller inductor and capacitor values. So why would DUTY FACTOR (VOUT/VIN) anyone ever choose to operate at lower frequencies with 1929 F03 larger components? The answer is efficiency. A higher Figure 3. Normalized Output Ripple Current frequency generally results in lower efficiency because of vs Duty Factor [IRMS ≈ 0.3 (∆IO(P–P))] 12

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Accepting larger values of ∆IL allows the use of low EXTVCC Pin Connection). Consequently, logic-level thresh- inductances, but can result in higher output voltage ripple. old MOSFETs must be used in most applications. The only A reasonable starting point for setting ripple current is ∆IL exception is if low input voltage is expected (VIN < 5V); = 0.4(IOUT)/2, where IOUT is the total load current. Remem- then, sublogic-level threshold MOSFETs (VGS(TH) < 3V) ber, the maximum ∆IL occurs at the maximum input should be used. Pay close attention to the BVDSS specifi- voltage. The individual inductor ripple currents are deter- cation for the MOSFETs as well; most of the logic-level mined by the inductor, input and output voltages. MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” Inductor Core Selection resistance RDS(ON), reverse transfer capacitance CRSS, Once the values for L1 and L2 are known, the type of input voltage, and maximum output current. When the inductor must be selected. High efficiency converters LTC1929 is operating in continuous mode the duty factors generally cannot afford the core loss found in low cost for the top and bottom MOSFETs of each output stage are powdered iron cores, forcing the use of more expensive given by: ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, V Main SwitchDuty Cycle = OUT but it is very dependent on inductance selected. As induc- VIN tance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and  VVIN– OUT  therefore copper losses will increase. Synchronous SwitchDuty Cycle =    VIN  Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- The MOSFET power dissipations at maximum output centrate on copper loss and preventing saturation. Ferrite current are given by: core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is   2 VOUT IMAX exceeded. This results in an abrupt increase in inductor PMAIN =   ()1+ δ RDS() ON + ripple current and consequent output voltage ripple. Do VIN  2    not allow the core to saturate! 2 IMAX kV()IN   ()()CfRSS Molypermalloy (from Magnetics, Inc.) is a very good, low  2  loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manu-   2 facturer is Kool Mµ. Toroids are very space efficient, VVIN– OUT IMAX PSYNC =   ()1+ δ RDS() ON especially when you can use several layers of wire. Be- VIN  2  cause they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which where δ is the temperature dependency of RDS(ON) and k do not increase the height significantly. is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses but the topside N-channel Power MOSFET, D1 and D2 Selection equation includes an additional term for transition losses, Two external power MOSFETs must be selected for each which peak at the highest input voltage. For VIN < 20V the output stage with the LTC1929: One N-channel MOSFET high current efficiency generally improves with larger for the top (main) switch, and one N-channel MOSFET for MOSFETs, while for VIN > 20V the transition losses rapidly the bottom (synchronous) switch. increase to the point that the use of a higher RDS(ON) device with lower CRSS actual provides higher efficiency. The The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see Kool Mµ is a registered trademark of Magnetics, Inc. 13

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APPLICATIO S I FOR ATIOWU synchronous MOSFET losses are greatest at high input 0.6 voltage when the top switch duty factor is low or during a 0.5 short-circuit when the synchronous switch is on close to 100% of the period. 0.4 1-PHASE 2-PHASE The term (1 + δ) is generally given for a MOSFET in the 0.3 form of a normalized RDS(ON) vs. Temperature curve, but 0.2 δ = 0.005/°C can be used as an approximation for low DC LOAD CURRENT voltage MOSFETs. CRSS is usually specified in the MOS- RMS INPUT RIPPLE CURRNET 0.1 FET characteristics. The constant k = 1.7 can be used to 0 estimate the contributions of the two terms in the main 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 switch dissipation equation. DUTY FACTOR (VOUT/VIN) 1929 F04 The Schottky diodes, D1 and D2 shown in Figure 1 conduct during the dead-time between the conduction of the two Figure 4. Normalized RMS Input Ripple Current vs Duty Factor for 1 and 2 Output Stages large power MOSFETs. This helps prevent the body diode of the bottom MOSFET from turning on, storing charge during the dead-time, and requiring a reverse recovery These worst-case conditions are commonly used for de- period which would reduce efficiency. A 1A to 3A (depend- sign because even significant deviations do not offer much ing on output current) Schottky diode is generally a good relief. Note that capacitor manufacturer’s ripple current compromise for both regions of operation due to the ratings are often based on only 2000 hours of life. This relatively small average current. Larger diodes result in makes it advisable to further derate the capacitor, or to additional transition losses due to their larger junction choose a capacitor rated at a higher temperature than capacitance. required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult CIN and COUT Selection the capacitor manufacturer if there is any question. In continuous mode, the source current of each top It is important to note that the efficiency loss is propor- N-channel MOSFET is a square wave of duty cycle VOUT/ tional to the input RMS current squared and therefore a VIN. A low ESR input capacitor sized for the maximum 2-stage implementation results in 75% less power loss RMS current must be used. The details of a close form when compared to a single phase design. Battery/input equation can be found in Application Note 77. Figure 4 protection fuse resistance (if used), PC board trace and shows the input capacitor ripple current for a 2-phase connector resistance losses are also reduced by the re- configuration with the output voltage fixed and input duction of the input ripple current in a 2-phase system. The voltage varied. The input ripple current is normalized required amount of input capacitance is further reduced by against the DC output current. The graph can be used in the factor, 2, due to the effective increase in the frequency place of tedious calculations. The minimum input ripple of the current pulses. current can be achieved when the input voltage is twice the The selection of COUT is driven by the required effective output voltage. The minimum is not quite zero due to series resistance (ESR). Typically once the ESR require- inductor ripple current. ment has been met, the RMS current rating generally far In the graph of Figure 4, the local maximum input RMS exceeds the IRIPPLE(P-P) requirements. The steady state capacitor currents are reached when: output ripple (∆VOUT) is determined by:   VOUT 21k − 1 = where k = 1, 2. ∆∆VOUT≈+ I RIPPLE ESR  VIN 4  16fCOUT  14

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Where f = operating frequency of each stage, COUT = series. Consult the manufacturer for other specific recom- output capacitance and ∆IRIPPLE = combined inductor mendations. A combination of capacitors will often result ripple currents. in maximizing performance and minimizing overall cost and size. The output ripple varies with input voltage since ∆IL is a function of input voltage. The output ripple will be less than INTVCC Regulator 50mV at max VIN with ∆IL = 0.4IOUT(MAX)/2 assuming: An internal P-channel low dropout regulator produces 5V COUT required ESR < 4(RSENSE) and at the INTVCC pin from the VIN supply pin. The INTVCC COUT > 1/(16f)(RSENSE) regulator powers the drivers and internal circuitry of the The emergence of very low ESR capacitors in small, LTC1929. The INTVCC pin regulator can supply up to 50mA peak and must be bypassed to power ground with a surface mount packages makes very physically small µ implementations possible. The ability to externally com- minimum of 4.7 F tantalum or electrolytic capacitor. An additional 1µF ceramic capacitor placed very close to the pensate the switching regulator loop using the I pin TH IC is recommended due to the extremely high instanta- (OPTI-LOOP compensation) allows a much wider selec- neous currents required by the MOSFET gate drivers. tion of output capacitor types. OPTI-LOOP compensation effectively removes constraints on output capacitor ESR. High input voltage applications in which large MOSFETs The impedance characteristics of each capacitor type are are being driven at high frequencies may cause the maxi- significantly different than an ideal capacitor and therefore mum junction temperature rating for the LTC1929 to be require accurate modeling or bench evaluation during exceeded. The supply current is dominated by the gate design. charge supply current, in addition to the current drawn from the differential amplifier output. The gate charge is Manufacturers such as Nichicon, United Chemicon and dependent on operating frequency as discussed in the Sanyo should be considered for high performance through- Efficiency Considerations section. The supply current can hole capacitors. The OS-CON semiconductor dielectric either be supplied by the internal 5V regulator or via the capacitor available from Sanyo and the Panasonic SP EXTV surface mount types have the lowest (ESR)(size) product CC pin. When the voltage applied to the EXTVCC pin of any aluminum electrolytic at a somewhat higher price. is less than 4.7V, all of the INTVCC load current is supplied An additional ceramic capacitor in parallel with OS-CON by the internal 5V linear regulator. Power dissipation for type capacitors is recommended to reduce the inductance the IC is higher in this case by (IIN)(VIN – INTVCC) and effects. efficiency is lowered. The junction temperature can be estimated by using the equations given in Note 1 of the In surface mount applications, multiple capacitors may Electrical Characteristics. For example, the LTC1929 VIN have to be paralleled to meet the ESR or RMS current current is limited to less than 24mA from a 24V supply: handling requirements of the application. Aluminum elec- ° ° ° trolytic and dry tantalum capacitors are both available in TJ = 70 C + (24mA)(24V)(95 C/W) = 125 C surface mount configurations. New special polymer sur- Use of the EXTVCC pin reduces the junction temperature face mount capacitors offer very low ESR also but have to: much lower capacitive density per unit volume. In the case T = 70°C + (24mA)(5V)(95°C/W) = 81.4°C of tantalum, it is critical that the capacitors are surge tested J for use in switching power supplies. Several excellent The input supply current should be measured while the choices are the AVX TPS, AVX TPSV or the KEMET T510 controller is operating in continuous mode at maximum series of surface mount tantalums, available in case heights VIN and the power dissipation calculated in order to pre- ranging from 2mm to 4mm. Other capacitor types include vent the maximum junction temperature from being Sanyo OS-CON, Nichicon PL series and Sprague 595D exceeded.

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EXTVCC Connection 1. EXTVCC left open (or grounded). This will cause INTVCC The LTC1929 contains an internal P-channel MOSFET to be powered from the internal 5V regulator resulting in a significant efficiency penalty at high input voltages. switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V, the 2. EXTVCC connected directly to VOUT. This is the normal internal regulator is turned off and the switch closes, connection for a 5V regulator and provides the highest connecting the EXTVCC pin to the INTVCC pin thereby efficiency. supplying internal and MOSFET gate driving power. The 3. EXTV connected to an external supply. If an external switch remains closed as long as the voltage applied to CC supply is available in the 5V to 7V range, it may be used to EXTVCC remains above 4.5V. This allows the MOSFET power EXTVCC providing it is compatible with the MOSFET driver and control power to be derived from the output gate drive requirements. during normal operation (4.7V < VEXTVCC < 7V) and from the internal regulator when the output is out of regulation 4. EXTVCC connected to an output-derived boost network. (start-up, short-circuit). Do not apply greater than 7V to For 3.3V and other low voltage regulators, efficiency gains the EXTVCC pin and ensure that EXTVCC < VIN + 0.3V when can still be realized by connecting EXTVCC to an output- using the application circuits shown. If an external voltage derived voltage which has been boosted to greater than source is applied to the EXTVCC pin when the VIN supply is 4.7V but less than 7V. This can be done with either the not present, a diode can be placed in series with the inductive boost winding as shown in Figure 5a or the LTC1929’s VIN pin and a Schottky diode between the capacitive charge pump shown in Figure 5b. The charge EXTVCC and the VIN pin, to prevent current from backfeeding pump has the advantage of simple magnetics. VIN. Topside MOSFET Driver Supply (CB,DB) (Refer to Significant efficiency gains can be realized by powering Functional Diagram) INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by the External bootstrap capacitors CB1 and CB2 connected to ratio: (Duty Factor)/(Efficiency). For 5V regulators this the BOOST1 and BOOST2 pins supply the gate drive voltages for the topside MOSFETs. Capacitor C in the means connecting the EXTVCC pin directly to VOUT. How- B ever, for 3.3V and other lower voltage regulators, addi- Functional Diagram is charged though diode DB from INTV when the SW pin is low. When the topside MOSFET tional circuitry is required to derive INTVCC power from the CC output. turns on, the driver places the CB voltage across the gate- source of the desired MOSFET. This enhances the MOSFET The following list summarizes the four possible connec- and turns on the topside switch. The switch node voltage, tions for EXTVCC:

+ OPTIONAL EXTVCC CONNECTION + VIN 5V < VSEC < 7V + VIN CIN CIN V IN BAT85 0.22µF BAT85 VIN 1N4148 VSEC TG1 TG1 + N-CH VN2222LL BAT85 1µF LTC1929 LTC1929 N-CH R RSENSE SENSE EXTV SW1 V EXTVCC SW1 VOUT CC OUT T1 L1 + + C BG1 COUT BG1 OUT

N-CH N-CH PGND PGND 1929 F05b 1929 F05a

Figure 5a. Secondary Output Loop with EXTVCC Connection Figure 5b. Capacitive Charge Pump for EXTVCC 16

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SW, rises to VIN and the BOOST pin rises to VIN + VINTVCC. currents by gradually increasing the controller’s current The value of the boost capacitor CB needs to be 30 to 100 limit ITH(MAX). The latchoff timer prevents very short, times that of the total input capacitance of the topside extreme load transients from tripping the overcurrent MOSFET(s). The reverse breakdown of DB must be greater latch. A small pull-up current (>5µA) supplied to the RUN/ than VIN(MAX). SS pin will prevent the overcurrent latch from operating. The following explanation describes how the functions The final arbiter when defining the best gate drive ampli- operate. tude level will be the input supply current. If a change is made that decreases input current, the efficiency has An internal 1.2µA current source charges up the CSS improved. If the input current does not change then the capacitor. When the voltage on RUN/SS reaches 1.5V, the efficiency has not changed either. controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current Output Voltage limit is increased from 25mV/RSENSE to 75mV/RSENSE. The LTC1929 has a true remote voltage sense capability. The output current limit ramps up slowly, taking an µ The sensing connections should be returned from the load additional 1.4s/ F to reach full current. The output current back to the differential amplifier’s inputs through a com- thus ramps up slowly, reducing the starting surge current mon, tightly coupled pair of PC traces. The differential required from the input power supply. If RUN/SS has been amplifier rejects common mode signals capacitively or pulled all the way to ground there is a delay before starting inductively radiated into the feedback PC traces as well as of approximately: ground loop disturbances. The differential amplifier output signal is divided down and compared with the internal 15. V tDELAY= CsFC SS=µ()125./ SS precision 0.8V voltage reference by the error amplifier. 12. µA The differential amplifier can be used in either of two The time for the output current to ramp up is then: configurations according to the voltage applied to the AMPMD pin (LTC1929 only). The first configuration, with 315VV− . tIRAMP= CsFC SS=µ()125./ SS the connections illustrated in the Functional Diagram, 12. µA utilizes a set of internal precision resistors to enable precision instrumentation-type measurement of the out- By pulling both RUN/SS controller pins below 0.8V the put voltage. This configuration is activated when the LTC1929 is put into low current shutdown (IQ < 40µA). The AMPMD pin is tied to ground and is the default for the RUN/SS pins can be driven directly from logic as shown in LTC1929-PG. When the AMPMD pin is tied to INTVCC, the Figure 6. Diode D1 in Figure 6 reduces the start delay but resistors are disconnected and the amplifier inputs are allows CSS to ramp up slowly providing the soft-start made directly available. The amplifier can then be used as function. The RUN/SS pin has an internal 6V zener clamp a general purpose op amp. The amplifier has a 0V to 3V (see Functional Diagram). common mode input range limitation due to the internal switching of its inputs. The output is an NPN emitter Fault Conditions: Overcurrent Latchoff follower without any internal pull-down current. A DC The RUN/SS pin also provides the ability to latch off the resistive load to ground is required in order to sink current. controllers when an overcurrent condition is detected. The output will swing from 0V to 10V (V ≥ V + 2V). IN DIFFOUT The RUN/SS capacitor, CSS, is used initially to limit the inrush current of both controllers. After the controllers Soft-Start/Run Function have been started and been given adequate time to charge The RUN/SS pin provides three functions: 1) Run/Shut- up the output capacitors and provide full load current, the down, 2) soft-start and 3) a defeatable short-circuit latchoff RUN/SS capacitor is used for a short-circuit timer. If the timer. Soft-start reduces the input power sources’ surge output voltage falls to less than 70% of its nominal value, 17

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APPLICATIO S I FOR ATIOWU after CSS reaches 4.1V, CSS begins discharging on the The value of the soft-start capacitor CSS may need to be assumption that the output is in an overcurrent condition. scaled with output voltage, output capacitance and load If the condition lasts for a long enough period as deter- current characteristics. The minimum soft-start capaci- mined by the size of CSS, the controller will be shut down tance is given by: until the RUN/SS pin voltage is recycled. If the overload C > (C )(V )(10-4)(R ) occurs during start-up, the time can be approximated by: SS OUT OUT SENSE The minimum recommended soft-start capacitor of C = t ≈ µ 5 SS LO1 (CSS • 0.6V)/(1.2 A) = 5 • 10 (CSS) 0.1µF will be sufficient for most applications. If the overload occurs after start-up the voltage on the RUN/SS capacitor will continue charging and will provide Phase-Locked Loop and Frequency Synchronization additional time before latching off: The LTC1929 has a phase-locked loop comprised of an 6 tLO2 ≈ (CSS • 3V)/(1.2µA) = 2.5 • 10 (CSS) internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the This built-in overcurrent latchoff can be overridden by rising edge of an external source. The frequency range of providing a pull-up resistor, RSS, to the RUN/SS pin as the voltage controlled oscillator is ±50% around the shown in Figure 6. This resistance shortens the soft-start center frequency f . A voltage applied to the PLLFLTR pin period and prevents the discharge of the RUN/SS capaci- O of 1.2V corresponds to a frequency of approximately tor during a severe overcurrent and/or short-circuit con- 220kHz. The nominal operating frequency range of the dition. When deriving the 5µA current from V IN as in the LTC1929 is 140kHz to 310kHz. figure, current latchoff is always defeated. The diode connecting of this pull-up resistor to INTVCC, as in The phase detector used is an edge sensitive digital type Figure␣ 6, eliminates any extra supply current during shut- which provides zero degrees phase shift between the down while eliminating the INTVCC loading from prevent- external and internal oscillators. This type of phase detec- ing controller start-up. tor will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in Why should you defeat current latchoff? During the range, ∆f , is equal to the capture range, ∆f prototyping stage of a design, there may be a problem with H C: noise pickup or poor layout causing the protection circuit ∆fH = ∆fC = ±0.5 fO (150kHz-300kHz) to latch off the controller. Defeating this feature allows The output of the phase detector is a complementary pair troubleshooting of the circuit and PC layout. The internal of current sources charging or discharging the external short-circuit and foldback current limiting still remains filter network on the PLLFLTR pin. A simplified block active, thereby protecting the power supply system from diagram is shown in Figure 7. failure. A decision can be made after the design is com- plete whether to rely solely on foldback current limiting or 2.4V RLP to enable the latchoff feature by removing the pull-up 10k PHASE DETECTOR resistor. EXTERNAL CLP OSC VIN INTVCC 3.3V OR 5V RUN/SS PLLFLTR RSS* RSS* PLLIN D1 DIGITAL RUN/SS PHASE/ OSC D1* FREQUENCY C SS 50k DETECTOR

CSS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF 1929 F06 1929 F07

Figure 6. RUN/SS Pin Interfacing Figure 7. Phase-Locked Loop Block Diagram 18

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If the external frequency (fPLLIN) is greater than the oscil- significant amount of cycle skipping can occur with corre- lator frequency f0SC, current is sourced continuously, spondingly larger current and voltage ripple. pulling up the PLLFLTR pin. When the external frequency If an application can operate close to the minimum on- is less than f0SC, current is sunk continuously, pulling time limit, an inductor must be chosen that has a low down the PLLFLTR pin. If the external and internal fre- enough inductance to provide sufficient ripple amplitude quencies are the same but exhibit a phase difference, the to meet the minimum on-time requirement. As a general current sources turn on for an amount of time correspond- rule, keep the inductor ripple current of each phase equal ing to the phase difference. Thus the voltage on the to or greater than 15% of I at V . PLLFLTR pin is adjusted until the phase and frequency of OUT(MAX) IN(MAX) the external and internal oscillators are identical. At this Efficiency Considerations stable operating point the phase comparator output is The percent efficiency of a switching regulator is equal to open and the filter capacitor CLP holds the voltage. The LTC1929 PLLIN pin must be driven from a low impedance the output power divided by the input power times 100%. source such as a logic gate located close to the pin. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would The loop filter components (CLP, RLP) smooth out the produce the most improvement. Percent efficiency can be current pulses from the phase detector and provide a expressed as: stable input to the voltage controlled oscillator. The filter %Efficiency = 100% – (L1 + L2 + L3 + ...) components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to where L1, L2, etc. are the individual losses as a percentage 0.1µF. of input power.

Minimum On-Time Considerations Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the Minimum on-time t is the smallest time duration ON(MIN) losses in LTC1929 circuits: 1) LTC1929 VIN current (in- that the LTC1929 is capable of turning on the top MOSFET. cluding loading on the differential amplifier output), It is determined by internal timing delays and the gate 2 2) INTVCC regulator current, 3) I R losses and 4) Topside charge required to turn on the top MOSFET. Low duty cycle MOSFET transition losses. applications may approach this minimum on-time limit and care should be taken to ensure that 1) The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control cur- < VOUT tON() MIN rents; the second is the current drawn from the differential VfIN() amplifier output. VIN current typically results in a small (<0.1%) loss. If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1929 will begin to skip 2) INTVCC current is the sum of the MOSFET driver and cycles resulting in nonconstant frequency operation. The control currents. The MOSFET driver current results from output voltage will continue to be regulated, but the ripple switching the gate capacitance of the power MOSFETs. current and ripple voltage will increase. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTV to The minimum on-time for the LTC1929 is generally less CC ground. The resulting dQ/dt is a current out of INTV that than 200ns. However, as the peak sense voltage decreases CC is typically much larger than the control circuit current. In the minimum on-time gradually increases. This is of continuous mode, I = (Q + Q ), where Q and Q particular concern in forced continuous applications with GATECHG T B T B are the gate charges of the topside and bottom side low ripple current at light loads. If the duty cycle drops MOSFETs. below the minimum on-time limit in this situation, a 19

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Supplying INTVCC power through the EXTVCC switch input minimum of 200µF to 300µF of output capacitance having from an output-derived source will scale the VIN current a maximum of 10mΩ to 20mΩ of ESR. The LTC1929 required for the driver and control circuits by the ratio 2-phase architecture typically halves the input and output (Duty Factor)/(Efficiency). For example, in a 20V to 5V capacitance requirements over competing solutions. Other application, 10mA of INTVCC current results in approxi- losses including Schottky conduction losses during dead- mately 3mA of VIN current. This reduces the mid-current time and inductor core losses generally account for less loss from 10% or more (if the driver was powered directly than 2% total additional loss. from VIN) to only a few percent. Checking Transient Response 3) I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, The regulator loop response can be checked by looking at and input and output capacitor ESR. In continuous mode the load transient response. Switching regulators take the average output current flows through L and RSENSE, several cycles to respond to a step in DC (resistive) load but is “chopped” between the topside MOSFET and the current. When a load step occurs, VOUT shifts by an synchronous MOSFET. If the two MOSFETs have approxi- amount equal to ∆ILOAD(ESR), where ESR is the effective ∆ mately the same RDS(ON), then the resistance of one series resistance of COUT( ILOAD) also begins to charge or MOSFET can simply be summed with the resistances of L, discharge COUT generating the feedback error signal that 2 RSENSE and ESR to obtain I R losses. For example, if each forces the regulator to adapt to the current change and RDS(ON)=10mΩ, RL=10mΩ, and RSENSE=5mΩ, then the return VOUT to its steady-state value. During this recovery total resistance is 25mΩ. This results in losses ranging time VOUT can be monitored for excessive overshoot or from 2% to 8% as the output current increases from 3A to ringing, which would indicate a stability problem. The 15A per output stage for a 5V output, or a 3% to 12% loss availability of the ITH pin not only allows optimization of per output stage for a 3.3V output. Efficiency varies as the control loop behavior but also provides a DC coupled and inverse square of VOUT for the same external components AC filtered closed loop response test point. The DC step, and output power level. The combined effects of increas- rise time, and settling at this test point truly reflects the ingly lower output voltages and higher currents required closed loop response. Assuming a predominantly second by high performance digital systems is not doubling but order system, phase margin and/or damping factor can be quadrupling the importance of loss terms in the switching estimated using the percentage of overshoot seen at this regulator system! pin. The bandwidth can also be estimated by examining the rise time at the pin. The I external components 4) Transition losses apply only to the topside MOSFET(s), TH shown in the Figure 1 circuit will provide an adequate and only when operating at high input voltages (typically starting point for most applications. 20V or greater). Transition losses can be estimated from: The I series R -C filter sets the dominant pole-zero Transition Loss = (1.7) V 2 TH C C IN IO(MAX) CRSS f loop compensation. The values can be modified slightly Other “hidden” losses such as copper trace and internal (from 0.2 to 5 times their suggested values) to maximize battery resistances can account for an additional 5% to transient response once the final PC layout is done and the 10% efficiency degradation in portable systems. It is very particular output capacitor type and value have been important to include these “system” level losses in the determined. The output capacitors need to be decided design of a system. The internal battery and input fuse upon because the various types and values determine the resistance losses can be minimized by making sure that loop feedback factor gain and phase. An output current CIN has adequate charge storage and a very low ESR at the pulse of 20% to 80% of full-load current having a rise time switching frequency. A 50W supply will typically require a of <2µs will produce output voltage and ITH pin waveforms

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIOWU that will give a sense of the overall loop stability without Automotive Considerations: Plugging into the breaking the feedback loop. The initial output voltage step Cigarette Lighter resulting from the step change in output current may not As battery-powered devices go mobile, there is a natural be within the bandwidth of the feedback loop, so this signal interest in plugging into the cigarette lighter in order to cannot be used to determine phase margin. This is why it conserve or even recharge battery packs during operation. is better to look at the Ith pin signal which is in the feedback But before you connect, be advised: you are plugging into loop and is the filtered and compensated control loop the supply from hell. The main battery line in an automo- response. The gain of the loop will be increased by bile is the source of a number of nasty potential transients, increasing RC and the bandwidth of the loop will be including load-dump, reverse-battery, and double-bat- increased by decreasing CC. If RC is increased by the same tery. factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most Load-dump is the result of a loose battery cable. When the critical frequency range of the feedback loop. The output cable breaks connection, the field collapse in the alternator voltage settling behavior is related to the stability of the can cause a positive spike as high as 60V which takes closed-loop system and will demonstrate the actual over- several hundred milliseconds to decay. Reverse-battery is all supply performance. just what it says, while double-battery is a consequence of tow truck operators finding that a 24V jump start cranks A second, more severe transient is caused by switching in cold engines faster than 12V. loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel The network shown in Figure 8 is the most straightforward with COUT, causing a rapid drop in VOUT. No regulator can approach to protect a DC/DC converter from the ravages alter its delivery of current quickly enough to prevent this of an automotive battery line. The series diode prevents sudden step change in output voltage if the load switch current from flowing during reverse-battery, while the resistance is low and it is driven quickly. If the ratio of transient suppressor clamps the input voltage during CLOAD to COUT is greater than 1:50, the switch rise time load-dump. Note that the transient suppressor should not should be controlled so that the load rise time is limited to conduct during double-battery operation, but must still approximately 25 • CLOAD. Thus a 10µF capacitor would clamp the input voltage below breakdown of the converter. require a 250µs rise time, limiting the charging current to Although the LT1929 has a maximum input voltage of 36V, about 200mA. most applications will be limited to 30V by the MOSFET BVDSS.

50A IPK RATING VIN 12V

TRANSIENT VOLTAGE LTC1929 SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A

1929 F08

Figure 8. Automotive Application Protection

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIOWU Design Example The worst-case power disipated by the synchronous MOSFET under normal operating conditions at elevated As a design example, assume V = 5V (nominal), V ␣ =␣ 5.5V IN IN ambient temperature and estimated 50°C junction tem- (max), V = 1.8V, I = 20A, T = 70°C and f␣ =␣ 300kHz. OUT MAX A perature rise is: The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current − 2 = 55..VV 18 Ω occurs at the maximum input voltage. Tie the FREQSET pin PSYNC ()()10A 1.. 48() 0 013 55. V to the INTV pin for 300kHz operation. The minimum CC = 129. W inductance for 30% ripple current is: A short-circuit to ground will result in a folded back current   of about: VOUTV OUT L ≥ 1−  fI()∆  V  IN 200ns() 5. 5 V  25mV 1     ISC = + = 66. A ≥ 18. V − 18. V Ω  µ  1  0. 004 2  15. H  ()()()300kHz 30% 10 A  55. V ≥µ135. H The worst-case power disipated by the synchronous MOSFET under short-circuit conditions at elevated ambient temperature and estimated 50°C junction temperature A 1.5µH inductor will produce 27% ripple current. The rise is: peak inductor current will be the maximum DC value plus one half the ripple current, or 11.4A. The minimum on- 55..VV− 18 2 time occurs at maximum VIN: PSYNC = ()()66...A 148() 0013Ω 55. V V 18. V = t ()==OUT =µ11. s 564mW ON MIN Vf ()()5. 5V 300 kHz IN which is less than half of the normal, full-load dissipation. Incidentally, since the load no longer dissipates power in The RSENSE resistors value can be calculated by using the maximum current sense voltage specification with some the shorted condition, total system power dissipation is accomodation for tolerances: decreased by over 99%. The duty factor for this application is: 50mV RSENSE =≈Ω0. 004 11. 4A V 18. V DF ==O =036. The power dissipation on the topside MOSFET can be VIN 5V easily estimated. Using a Siliconix Si4420DY for example; Using Figure 4, the RMS ripple current will be: RDS(ON) = 0.013Ω, CRSS = 300pF. At maximum input voltage with TJ (estimated) = 110°C at an elevated ambient IINRMS = (20A)(0.23) = 4.6ARMS temperature: An input capacitor(s) with a 4.6ARMS ripple current rating is required. 18. V 2 PMAIN = ()10[] 1+ () 0. 005() 110°−CC 25 ° The output capacitor ripple current is calculated by using 55. V the inductor ripple already calculated for each inductor 2 0... 013Ω + 1 7()()() 5 5VApF 10 300 and multiplying by the factor obtained from Figure␣ 3 along with the calculated duty factor. The output ripple in ()300kHz= 0. 65 W 22

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIOWU continuous mode will be highest at the maximum input provides the AC current to the MOSFETs. Keep the input voltage since the duty factor is <50%. The maximum current path formed by the input capacitor, top and bottom output current ripple is: MOSFETs, and the Schottky diode on the same side of the PC board in a tight loop to minimize conducted and radiated EMI. ∆ = VOUT ICOUT ()03.%at 33 DF µ fL 5) Is the INTVCC 1 F ceramic decoupling capacitor con- 18. V nected closely between INTVCC and the power ground pin? ∆ICOUTMAX = 03. This capacitor carries the MOSFET driver peak currents. A µ ()300kHz() 1. 5 H small value is used to allow placement immediately adja- = 12. ARMS cent to the IC. VmAmVOUTRIPPLE=Ω20() 1. 2 RMS= 24 RMS 6) Keep the switching nodes, SW1 (SW2), away from sensitive small-signal nodes. Ideally the switch nodes should be placed at the furthest point from the LTC1929. PC Board Layout Checklist 7) Use a low impedance source such as a logic gate to drive When laying out the printed circuit board, the following the PLLIN pin and keep the lead as short as possible. checklist should be used to ensure proper operation of the LTC1929. These items are also illustrated graphically in The diagram in Figure 9 illustrates all branch currents in the layout diagram of Figure␣ 11. Check the following in a 2-phase switching regulator. It becomes very clear after your layout: studying the current waveforms why it is critical to keep the high-switching-current paths to a small physical size. 1) Are the signal and power grounds segregated? The High electric and magnetic fields will radiate from these LTC1929 signal ground pin should return to the (–) plate “loops” just as radio stations transmit signals. The out- of C separately. The power ground returns to the OUT put capacitor ground should return to the negative termi- sources of the bottom N-channel MOSFETs, anodes of the nal of the input capacitor and not share a common Schottky diodes, and (–) plates of C , which should have IN ground path with any switched current paths. The left half as short lead lengths as possible. of the circuit gives rise to the “noise” generated by a + 2) Does the LTC1929 VOS pin connect to the (+) plate(s) switching regulator. The ground terminations of the – of COUT? Does the LTC1929 VOS pin connect to the (–) synchronous MOSFETs and Schottky diodes should re- plate(s) of COUT? The resistive divider R1, R2 must be turn to the bottom plate(s) of the input capacitor(s) with connected between the VDIFFOUT and signal ground and a short isolated PC trace since very high switched cur- any feedforward capacitor across R1 should be as close as rents are present. A separate isolated path from the possible to the LTC1929. bottom plate(s) of the input capacitor(s) should be used 3) Are the SENSE – and SENSE + leads routed together with to tie in the IC power ground pin (PGND) and the signal minimum PC trace spacing? The filter capacitors between ground pin (SGND). This technique keeps inherent sig- SENSE + and SENSE– pin pairs should be as close as nals generated by high current pulses from taking alter- possible to the LTC1929. Ensure accurate current sensing nate current paths that have finite impedances during the with Kelvin connections. total period of the switching regulator. External OPTI- LOOP compensation allows overcompensation for PC 4) Do the (+) plates of CIN connect to the drains of the layouts which are not optimized but this is not the topside MOSFETs as closely as possible? This capacitor recommended design procedure.

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIOWU Simplified Visual Explanation of How a 2-Phase Figure 4 illustrates the RMS input current drawn from the Controller Reduces Both Input and Output RMS Ripple input capacitance vs the duty cycle as determined by the Current ratio of input and output voltage. The peak input RMS A multiphase power supply significantly reduces the current level of the single phase system is reduced by 50% amount of ripple current in both the input and output in a 2-phase solution due to the current splitting between capacitors. The RMS input ripple current is divided by, and the two stages. the effective ripple frequency is multiplied up by the An interesting result of the 2-phase solution is that the VIN number of phases used (assuming that the input voltage which produces worst-case ripple current for the input is greater than the number of phases used times the output capacitor, VOUT = VIN/2, in the single phase design pro- voltage). The output ripple amplitude is also reduced by, duces zero input current ripple in the 2-phase design. and the effective ripple frequency is increased by the The output ripple current is reduced significantly when number of phases used. Figure 10 graphically illustrates compared to the single phase solution using the same the principle. inductance value because the VOUT/L discharge current The worst-case RMS ripple current for a single stage term from the stage that has its bottom MOSFET on design peaks at twice the value of the output voltage . The subtracts current from the (VIN - VOUT)/L charging current worst-case RMS ripple current for a two stage design resulting from the stage which has its top MOSFET on. The results in peaks at 1/4 and 3/4 of input voltage. When the output ripple current is: RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as   2V 12−−DD() 1 the currents in each stage are balanced. Refer to Applica- ∆I = OUT   RIPPLE  −+ tion Note 19 for a detailed description of how to calculate fL  12D 1 RMS current for the single stage switching regulator. Figures 3 and 4 illustrate how the input and output where D is duty factor. currents are reduced by using an additional phase. The The input and output ripple frequency is increased by the input current peaks drop in half and the frequency is number of stages used, reducing the output capacity doubled for this 2-phase converter. The input capacity requirements. When VIN is approximately equal to 2(VOUT) requirement is thus reduced theoretically by a factor of as illustrated in Figures 3 and 4, very low input and output four! Ceramic input capacitors with their unbeatably low ripple currents result. ESR characteristics can be used.

LTC1929/LTC1929-PG

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APPLICATIO S I FOR ATIOWU

SW1 L1 RSENSE1

VIN VOUT

R IN + COUT CIN + RL

SW2 L2 RSENSE2

BOLD LINES INDICATE D2 HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH.

1929 F09

Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

SINGLE PHASE DUAL PHASE

SW V SW1 V

SW2 V ICIN

IL1

ICOUT

IL2

ICIN

ICOUT

RIPPLE

1929 F10

Figure 10. Single and 2-Phase Current Waveforms 25 LTC1929/LTC1929-PG

TYPICAL APPLICATIOU S + – – + IN IN V 5V V + – Ω Ω OUT OUT OSENSE OSENSE R4 1.6V/40A REMOTE SENSE V V V V R8 C4 0.002 0.002 F 1929 F11 + µ C24 10 H C3 µ L1 1 H µ L2 1 + Q2 Q4 F C21 µ C23 1 Q6 Q8 Ω + R10 50 F µ C20 C22 1 Q1 Q3 + Q5 Q7 C19 Ω + R9 50 F µ C18 C16 0.47 D1 BAT54A + 3 F 12 µ C14 10 F µ F µ C13 2.2 C8 0.47 Ω R1 10 F µ C12 1 C3, C4: OS-CON 6SP680M C18–C21: T510E108M004 L1, L2: SUMIDA CEP149-1R0MC Q1–Q8: FDS6670A OR FDS7760A F 28 27 26 25 24 23 22 21 20 19 18 17 16 15 µ C2 1 IN CC CC NC V TG1 TG2 BG1 BG2 SW1 SW2 PGND INTV EXTV AMPMD BOOST1 BOOST2 U1 + – – + LTC1929 Figure 11. 5V Input, 1.6V/40A CPU Power Supply – + DIFFOUT OS OS TH RUN/SS SENSE1 SENSE1 EAIN PLLFLTR PLLIN NC I SGND V V V SENSE2 SENSE2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C17 1000pF C1 1000pF R7 8.06k R3 10k C15 R6 470pF 8.06k R5 10k R2 2.7k C10 100pF F C11 1nF µ F µ C7 0.1 C9 0.01 26 LTC1929/LTC1929-PG

TYPICAL APPLICATIOU S

100

70 EFFICIENCY (%)

60 VIN = 5V VOUT = 1.6V 50 0 5 10 15 20 25 30 35 40 LOAD CURRENT (A)

1929 F12

Figure 12. Efficiency Plot for Circuit of Figure 11

PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted.

G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640)

10.07 – 10.33* (0.397 – 0.407) 28 27 2625 24 23 22 21 20 19 18 17 16 15

7.65 – 7.90 (0.301 – 0.311)

12345 6 7 8 9 10 11 1213 14 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078)

0° – 8°

0.65 0.13 – 0.22 0.55 – 0.95 (0.0256) (0.005 – 0.009) (0.022 – 0.037) BSC 0.05 – 0.21 0.25 – 0.38 (0.002 – 0.008) NOTE: DIMENSIONS ARE IN MILLIMETERS (0.010 – 0.015) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE G28 SSOP 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC1929/LTC1929-PG

TYPICAL APPLICATIO U

LTC1929-PG 1 28 RUN/SS NC L1 2 27 0.1µF SENSE1+ TG1 1000pF 3 26 0.004Ω SENSE1– SW1 2.7k 4 25 0.22µF EAIN BOOST1 M1 M2 10k 5 24 INTV PLLFLTR V D1 CC IN MBRS140T3 51k 6 23 15k PLLIN BG1 7 22 Ω CIN 10 µ NC EXTVCC 5V (OPT) 47 F 35V

47k 8 21 + I INTV + TH CC µ 3.3nF 100pF 9 20 10µF 0.1 F C SGND PGND OUT VIN 10 19 5V TO 28V 470pF VDIFFOUT BG2 D2 11 18 MBRS140T3 V – BOOST2 M3 M4 10k 15k OS 12 17 0.22µF VOS+ SW2 13 16 0.004Ω VOUT SENSE2– TG2 2V 1000pF 14 15 100k 20A SENSE2+ PGOOD L2 SWITCHING FREQUENCY = 200kHz PGOOD CIN: 5A RIPPLE CURRENT RATING REQUIRED COUT: 4 × 180µF/4V PANASONIC SP L1 TO L2: 1.5µH SUMIDA CEP125-1R5MC 1929 F13 M1 TO M4: FAIRCHILD FDS7760A

Figure 13. 2V/20A CPU Power Supply with Active Voltage Positioning

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Linear Technology Corporation 1929f LT/TP 0500 4K • PRINTED IN USA 28 1630 McCarthy Blvd., Milpitas, CA 95035-7417  (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1999