Multimodal Implantable Neural Interfacing Microsystem

Thèse

Masoud Rezaei

Doctorat en génie électrique Philosophiæ doctor (Ph. D.)

Québec, Canada

© Masoud Rezaei, 2019

Résumé

Afin d’étudier le cerveau humain dans le but d’aider les patients souffrant de maladies neurologiques, on a besoin d’une interface cérébrale entièrement implantable pour permettre l’accès direct aux neu- rones et enregistrer et analyser l’activité neuronale. Dans cette thèse, des interfaces cerveau-machine implantables (IMC) à très faible puissance basées sur plusieurs circuits et innovations de systèmes ont été étudiées pour être utilisées comme analyseur neuronal. Un tel système est destiné à recueillir l’activité neuronale émise par centaines de neurones tout en les activant à la demande en utilisant des moyens d’actionnement tels que l’électro- et / ou la photo-stimulation. Un tel système doit fournir plusieurs canaux d’enregistrement, tout en consommant très peu d’énergie, et présente une taille extrêmement réduite pour la sécurité et la biocompatibilité. Typiquement, un microsystème d’interfaçage avec le cerveau comprend plusieurs blocs, tels qu’un bloc analogique d’acquisition (AFE), un convertisseur analogique-numérique (ADC), des modules de traitement de signal numé- rique et un émetteur-récepteur de données sans fil. Un IMC extrait les signaux neuronaux du bruit, les numérise et les transmet à une station de base sans interférer avec le comportement naturel du sujet. Cette thèse se concentre sur les blocs analogiques d’acquisition à très faible consommation à utiliser dans l’IMC. Cette thèse présente des frontaux avec plusieurs stratégies innovantes pour consommer moins d’énergie tout en permettant des données de haute résolution et de haute qualité.

Premièrement, nous présentons une nouvelle structure frontale utilisant un schéma de réutilisation du courant. Cette structure est extensible à un très grand nombre de canaux d’enregistrement, grâce à sa petite taille de silicium et à sa faible consommation d’énergie. L’AFE à réutilisation de courant proposée, qui comprend un amplificateur à faible bruit (LNA) et un amplificateur à gain programmable (PGA), utilise une nouvelle topologie de miroir de courant entièrement différentielle utilisant moins de transistors et améliorant plusieurs paramètres de conception, tels que la consommation d’énergie et du bruit, par rapport aux mises en œuvre de circuit d’amplificateur de réutilisation de courant précédentes.

Ensuite, dans la deuxième partie de cette thèse, nous proposons un nouveau convertisseur sigma- delta multicanal qui convertit plusieurs canaux indépendamment en utilisant un seul amplificateur et plusieurs condensateurs de stockage de charge. Par rapport aux techniques conventionnelles, cette méthode applique un nouveau schéma de multiplexage entrelacé, qui ne nécessite aucune phase de réinitialisation pour l’intégrateur lors du passage à un nouveau canal, ce qui améliore sa résolution.

iii Lorsque la taille des puces n’est pas une priorité, d’autres approches peuvent être plus attrayantes, et nous proposons une nouvelle stratégie d’économie d’énergie basée sur un nouveau convertisseur sigma-delta à très basse consommation conçu pour réduire la consommation d’énergie. Ce nouveau convertisseur utilise une architecture basse tension basée sur une topologie prédictive innovante qui minimise la non-linéarité associée à l’alimentation basse tension.

iv Abstract

Studying brain functionality to help patients suffering from neurological diseases needs fully im- plantable brain interface to enable access to neural activities as well as read and analyze them. In this thesis, ultra-low power implantable brain-machine-interfaces (BMIs) that are based on several inno- vations on circuits and systems are studied for use in neural recording applications. Such a system is intended to collect information on neural activity emitted by several hundreds of neurons, while acti- vating them on demand using actuating means like electro- and/or photo-stimulation. Such a system must provide several recording channels, while consuming very low energy, and have an extremely small size for safety and biocompatibility. Typically, a brain interfacing microsystem includes several building blocks, such as an analog front-end (AFE), an analog-to-digital converter (ADC), digital sig- nal processing modules, and a wireless data transceiver. A BMI extracts neural signals from noise, digitizes them, and transmits them to a base station without interfering with the natural behavior of the subject. This thesis focuses on ultra-low power front-ends to be utilized in a BMI, and presents front-ends with several innovative strategies to consume less power, while enabling high-resolution and high-quality of data.

First, we present a new front-end structure using a current-reuse scheme. This structure is scalable to huge numbers of recording channels, owing to its small implementation silicon area and its low power consumption. The proposed current-reuse AFE, which includes a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), employs a new fully differential current-mirror topology using fewer transistors. This is an improvement over several design parameters, in terms of power consumption and noise, over previous current-reuse amplifier circuit implementations.

In the second part of this thesis, we propose a new multi-channel sigma-delta converter that converts several channels independently using a single op-amp and several charge storage capacitors. Com- pared to conventional techniques, this method applies a new interleaved multiplexing scheme, which does not need any reset phase for the integrator while it switches to a new channel; this enhances its resolution.

When the chip area is not a priority, other approaches can be more attractive, and we propose a new power-efficient strategy based on a new in-channel ultra-low power sigma-delta converter designed to decrease further power consumption. This new converter uses a low-voltage architecture based on an innovative feed-forward topology that minimizes the nonlinearity associated with low-voltage supply.

v Table des matières

Résumé iii

Table des matières vi

Liste des tableaux viii

Liste des figures ix

List of Symbols xii

Introduction 1 1.1 Presentation of the project ...... 2 1.2 Literature Review : Low-noise Amplifier Design ...... 3 1.3 Literature Review : Filter Stage and Second-gain Stage...... 7 1.4 Literature Review : Analog to Digital Converters...... 8 1.4.1 Successive Approximation Register ADC (SAR)...... 10 1.4.2 Sigma Delta Converter...... 11 1.5 Literature Review : Optimizing Brain Machine Interface...... 13 1.6 Thesis Outline and Summary of the Contributions...... 14

2 A Low-Power Current-Reuse Analog Front-End for High-Density Neural Recor- ding Implants 16 Résumé...... 16 Abstract...... 17 2.1 Introduction...... 17 2.2 CURRENT REUSE ANALOG FRONT END OVERVIEW...... 18 2.2.1 Principle of Current-Reuse Amplifier...... 19 2.2.2 Noise Analysis...... 20 2.2.3 Proposed Current-Reuse Amplifier Design ...... 21 2.2.4 Current-Reuse AFE Design ...... 22 2.2.5 Parasitic Input Capacitors Analysis ...... 24 2.2.6 Implementation of Current-Reuse PGA...... 26 2.2.7 Noise and Power Efficiency Factors Analysis...... 27 2.3 Measurement Results...... 29 2.3.1 Measured Performances...... 29 2.3.2 In-Vivo Recording Results...... 31 2.4 Conclusion ...... 33

vi 3 A TDM-Σ∆ Converter with Time-Interleaved Oversampling for High-Density Neu- ral Implants 34 Résumé...... 34 Abstract...... 35 3.1 Introduction...... 35 3.2 System Overview...... 37 3.2.1 Conventional TDM Σ∆ Converter...... 37 3.2.2 Time-Interleaved Oversampling TDM Σ∆ Converter...... 39 3.3 Time-Interleaved Oversampling Σ∆ System Design...... 40 3.3.1 Switched-Capacitor Op-amp Sharing ...... 41 3.3.2 Dynamic Comparator and Switches...... 42 3.3.3 Clock Sequence Generator...... 42 3.4 Measurement Results...... 43

4 A 110-nW in-Channel Sigma-Delta Converter for Large-Scale Neural Recording Implants 46 Résumé...... 46 Abstract...... 46 4.1 Introduction...... 47 4.2 Circuit Design...... 50 4.3 Simulation and Implementation Results...... 52 4.4 Conclusion ...... 54

Conclusion 56

Publication List 58

Bibliographie 60

vii Liste des tableaux

2.1 Summarized performance of the LNA and comparison ...... 32

4.1 Summary of performance of the proposed circuit against technology corners. . . . . 54 4.2 Performance summary and comparison with sate of the art...... 55

viii Liste des figures

1.1 Two different types of neural signals. a) Local field potential neural signals. b) Action potential neural signals...... 1 1.2 An implantable brain computer interface...... 2 1.3 Block diagram of the conventional AFE...... 3 1.4 Neural amplifier structure...... 4 1.5 Current mirror low noise OTA...... 4 1.6 Telescopic cascode low noise OTA...... 5 1.7 Folded cascode low noise OTA...... 6 1.8 Complementary differential low noise OTA...... 6 1.9 The partial OTA sharing...... 7 1.10 High pass filter using programmable pseudo resistors...... 8 1.11 A 3rd order GM-C low-pass filter using LC structure...... 9 1.12 A simple description to ADC functionality...... 9 1.13 Comparison to the discrete voltage levels ...... 10 1.14 Successive approximation ADC ...... 10 1.15 Comparison between linear ADC and logarithmic ADC [1]...... 11 1.16 Block diagram of a first order sigma-delta converter...... 11 1.17 The modified model of the first order sigma-delta converter containing quantization noise...... 12 1.18 The noise shaping benefit of using a sigma-delta converter...... 13 1.19 The parasitic input capacitor effect removal...... 14

2.1 Conceptual representation of a four-channel stacked current-reuse amplifier. The input differential pairs share the same supply currents and the recombination and output blocks provide an output signal that is related to each corresponding input...... 19 2.2 A conventional two-stage folded-cascode current reused amplifier. Two stacked input differential pairs share a same bias current source and each recombination output stage consumes B times the Ibias where B should be made smaller than 1. The common mode feedback circuits are also depicted...... 20 2.3 The proposed optimized current reused amplifier circuit. A two-stage current mirror- based current-reuse amplifier topology uses less transistors than previous topologies. The current mirrors at the input of the recombination output stages scale the output current of the stacked input pairs by a factor of B...... 22 2.4 Schematic of the implemented four stacked-input stage using the proposed optimized current reused amplifier circuit. In this design, Wp = 1000 µm, Lp = 0.8 µm, Wn = 80 µm, Ln = 4 µm, Ibias = 2.5 µA...... 22

ix 2.5 The recombination output stage for one of the outputs related to the four-stacked input LNA (Fig. 2.4). In this design, Wp = 80 µm, Lp = 4 µm, Wn = 80 µm, Ln = 4 µm, L = 1 µm, B = 1/8...... 23 2.6 The noise simulation of the proposed LNA...... 24 2.7 Block diagram of the proposed analog front-end, which includes four stacked current- reuse low-noise amplifiers (LNA) and programmable gain amplifiers (PGA). The ana- log multiplexer and outputs analog buffers are also shown...... 25 2.8 a) The proposed LNA design with the implemented T-network. b) The equivalent cir- cuit. The parasitic capacitor from input transistors are shown as CP...... 26 2.9 The minimum NEF versus the number of stacked differential inputs for different B factors. With B= 1/8 and N=4, this design achieves a theorical NEF of 1.237. . . . . 27 2.10 Die photograph of the 4-channel analog front-end fabricated in a TSMC CMOS 180- nm process...... 28 2.11 Frequency responses (gain and phase) of the AFE for the 4 channels...... 29 2.12 The different measured gain values for one channel in the AFE...... 30 2.13 Measured AFE input referred noise when the input of the AFE is shorted...... 31 2.14 The in-vivo test setup is performed at the (CRIUSQ) on an anesthetized 23 g mouse. 32 2.15 (a) Recorded neural activity of each AFE channel from the hippocampus of a mouse. (b) 135 similar action potentials isolated from the recorded waveform and aligned (waveforms are referred to the amplifier input)...... 33

3.1 (a) Block diagram of a four-channel first order incremental Σ∆ converter (IΣ∆), where Nch is the number of multiplexed input channels and FNyq is the Nyquist sampling frequency. (b) Block diagram of the proposed four-channel multiplexed Σ∆ converter with Interleaved Oversampling (MIOΣ∆), where ts is the oversampling interval. . . . 36 3.2 Timing diagram of the output data stream and output spectrum of one channel with oversampling in of the IΣ∆ (a) and in the MIOΣ∆ (b), respectively...... 37 3.3 Comparison between two TDM Σ∆ schemes. Performance comparison of the propo- sed TDM Σ∆ scheme with interleaved oversampling intervals depicted in Fig. 3.1-b (solid), and the conventional IΣ∆ scheme presented in Fig. 3.1-a (dashed), for a 100 Hz input sine wave for a bandwidth of 10 kHz and an OSR of 50. Both schemes are tested for second-order Σ∆ topologies. The conventional IΣ∆ scheme generates several harmonics within the bandwidth of interest, while the proposed scheme does not. The proposed scheme provides a 33 dB SNDR improvement compared to the conventional scheme, respectively...... 38 3.4 (a) Schematic of the proposed multiplexing interleaved oversampling Σ∆ converter in the evaluation phase. Each input has its own integration capacitor. (b) The proposed circuit in the reset phase performed before each evaluation phase, and (c) the imple- mented switch circuit...... 39 3.5 Schematic of the clock sequence generator and associated timing diagram...... 40 3.6 Die photograph of the proposed multiplexing interleaved oversampling Σ∆ converter along with its clock sequence generator circuit. The circuit occupies a silicon area of 150 µm × 135 µm...... 41 3.7 Measured PSD from input Channel 2 and measured inter-channel crosstalk. Channels 1 and 2 are given input sine waves of 1 kHz and 2 kHz, respectively...... 42 3.8 Synthetic neural signal digitized with the fabricated Σ∆ converter after offline decima- tion in MATLAB...... 43

x 4.1 An implantable brain computer interface...... 47 4.2 Block diagram of the first order sigma-delta converter...... 48 4.3 The error signal at the input of the comparator. a) Sigma-delta converter. b) Feed- forward sigma-delta converter...... 49 4.4 The power spectral density of the output signal. a) Sigma-delta converter. b) Feed- forward sigma-delta converter...... 49 4.5 Proposed circuit implementation of the sigma-delta converter depicted in Fig. 4.2. . . 50 4.6 (a) Implementation of the subtractor and integrator. (b) Implementation of switches with dummy transistors for minimizing charge injection...... 50 4.7 Schematic of the proposed multi-input comparator circuit...... 51 4.8 Die photograph of the proposed sigma delta converter...... 51 4.9 (a) Output power spectrum density obtained from a transient post layout simulation for an input sine wave. (b) Post-layout transient simulation for a pre-recorded in-vivo neural signal...... 53

xi List of Symbols

4KT Temperature coefitient in Kelvin AP Action Potentials ADC Analog to digital converter AFE Analog front end BMI Brain machine interface BW Bandwidth C Capacitor

CI Integrating capacitor CMFB Common mode feedback CMOS Complementary metal oxide semiconductor

Cox Gate oxide capacitor

CS Sampling capacitor DAC Digital to analog converter dB Decibel DC Direct current DFF D flip flop E Error signal ENOB Effective number of bits f Frequency f J Femtojoule f F Femto farad FOM Figure of merrit f w Feed-forward signal

gm Transconductance Hz Hertz I Current

Ibias Bias current ICRR Inter-channel rejection ratio

Id Drain current

Itotal Total current

xii IΣ∆ Incremental sigma delta kHz Kilo hertz L Length LFP Local Field Potentials LNA Low noise amplifier MOSFET Metal oxide semiconductor field effect transistor mm Milli meter mV Milli volt mW Milli watt N Noise signal NEF Noise efficiency factor NMOS N type metal oxide semiconductor transistor nV Nano volt nW Nano watt OSR Over sampling ratio OTA Operational transconductance amplifier PEF Power efficiency factor pF Pico farad PGA Programmable gain amplifier PMOS P type metal oxide semiconductor transistor PWM Pulse width modulation R Resistor RMS Root mean square SAH Sample and hold SAR Successive approximation register SC Switched capacitor SFDR Spurious free dynamic range SNR Signal to noise ratio SNDR Signal to noise and distortion ratio TDM Time domain multiplexing THD Total harmonic distortion TSMC Taiwan semiconductor manufacturing company

UT Thermal voltage equal to 25 mV V Voltage

Vi Voltage of node i

Vd Drain voltage

VDD Supply voltage

Vgs Gate-source voltage

Vout Output voltage

Vth Threshold voltage

xiii VGA Variable gain amplifier W Width X Input signal Y Output signal z variable in z domain µ Mobility µm Micro meter µV Micro volt Σ∆ Sigma Delta °C Degree centigrade

xiv To my wife Fatemeh

xv Remerciements

First and foremost, I would like to thank Professor Benoit Gosselin for guiding my research, allowing me to discover several topics, and providing me the resources to carry it out. He encouraged me to perform to the best of my abilities and gave me opportunities to learn different topics. I would also like to thank Professor Mohamad Sawan for his advice and great support. I had this opportunity to work under his supervision and take advantage of his knowledge in my project. I would also like to thank my team member, Esmaeel Maghsoudloo for his cooperation, help and support through the research. Finally, I am deeply grateful to my wife and my family for their endless encouragement. This work could not have been accomplished without their dedicated support, trust and love throughout my life.

xvi Avant-propos

Three chapters of this thesis are composed of material that is already published or under review in technical Transactions journal papers and a conference article. In the thesis, the text and figures have been modified to be consistent with the remainder of the document. The introduction sections have been most heavily modified. Here, I detail my contributions to two Transactions papers and the confe- rence article.

Paper 1 : M. Rezaei, E. Maghsoudloo, C. Bories, Y. De Koninck, B. Gosselin, "A Low-Power Current- Reuse Analog Front-End for High-Density Neural Recording Implants," IEEE Transactions on Bio- medical Circuits and Systems, vol. 12, no. 2, pp. 271-280, April 2018. This Transactions paper pro- vides mathematical analysis on noise calculation and introduces a novel current reuse structure AFE configuration that features smaller power consumption and less noise contribution. The original idea is proposed by me, and the experiments were conducted at the Biomedical Microsystem Lab at Laval University and research center CERVO. The manuscript was prepared by me and revised by the other authors before submission.

Paper 2 : M. Rezaei, E. Maghsoudloo, M. Sawan, B. Gosselin, "A Multiplexed Sigma-Delta Converter with Ultra Low- Crosstalk for High-Density Neural Implants," IEEE Transactions on Sensors (sub- mitted). This Transactions paper reviews the problems in the conventional multiplexing method in sigma-delta converters; I have proposed another multiplexing scheme to improve the performance of the converter. The original idea was proposed by me, and the experiments were conducted at the Bio- medical Microsystem La at Laval University. The manuscript was prepared by me and revised by the other authors before submission.

Paper 3 : M. Rezaei, E. Maghsoudloo, M. Sawan and B. Gosselin, "A 110-nW In-channel Sigma-delta Converter for Large-scale Neural Recording Implants," IEEE International Conference on Enginee- ring in Medicine and Biology Society (EMBC), pp. 5741-5744, 2016. This article is devoted to present an in-channel ultra-low power sigma-delta ADC to be used in neural recording applications. The ori- ginal idea was proposed by me, and the experiments were conducted at the Biomedical Microsystem La at Laval University. The manuscript was prepared by me and revised by the other authors before submission.

xvii Introduction

A Brain Machine Interface (BMI) represents the first step toward the development of chronically implantable devices for patients suffering from neurological diseases. A practical BMI must be fully implantable, provide several hundred recording channels, consume very low energy, and present an extremely small size. Such neural interfacing microsystems have greatly enhanced our understanding of brain functions and play a key role in the development of new prostheses for treating various chronic neural diseases. A variety of neural signals have captured the interest of biologists. These signals have different amplitudes and bandwidths. A multimodal neural recording system is a machine that is able to record these different types of neural signals. Local Field Potential (LFP) signals and Action Potential (AP) or spikes are some of these neural signals. Figure 1.1 shows these two different types of neural signals.

1mV

5 mV 100 μV

LFP AP

(a) (b)

Figure 1.1 – Two different types of neural signals. a) Local field potential neural signals. b) Action potential neural signals.

The LFP signal has maximum amplitude of 5mVp−p and the BW of 1 ∼ 100Hz, while AP signal has maximum amplitude of 1mVp−p and the BW of 300 ∼ 5KHz [2]. Typically, in a neural interfacing microsystem [3,4], an analog-to-digital converter (ADC) is included in the analog front-end (AFE) building block in order to digitize neural signals prior to a digital signal processing module and/or a data transmitter. An AFE comprises several cascaded stages, such as a low-noise amplifier, one or several analog filters, a second-gain stage, and a sample-and-hold circuit (SAH). Thus, the signal passes through several signal processing stages before being buffered and multiplexed towards an SAH circuit. Then, the sampled signal can be digitized using a low-power, medium resolution ADC [5]. Fig. 1.2 shows a representation of an implantable brain computer interface. As shown, the implanted device

1 can be powered up wirelessly using an inductive link [6,7], and communicates using both implanted and external antennas.

Wireless Power Power Transmitter Micro Analog Wireless Data Controller TX Front Communication RX Data End Out Data In Power Coil Flexible Stimulator Power 1 cm Antenna Real Time User Interface System on Chip Implantable Flexible Electrode Board Arrays Utah Electrode Arrays

Figure 1.2 – An implantable brain computer interface.

1.1 Presentation of the project

There are several challenges in designing such a precise BMI machine. These challenges are in delive- ring a certain amount of power that is needed by the system. Increasing the electromagnetic fields of power or transferring more power than several milliwatts (mW) will damage or heat up and burn the tissue of the brain. Thus, the power budget of the system is limited to several mW. Consequently, all the blocks within the system must be designed to consume as little power as possible, while meeting the needs of the system. In order to minimize the power consumption of the AFE, there is a need to design a precise low-power, low-noise amplifier. Moreover, the ADC block needs to be designed to be ultra-low power, providing a resolution of eight bits or more. Several ADC topologies have been introduced to be used in this application, such as successive approximation register ADC, sigma delta converter, and amplitude-to-time converters like PWM generators. Finally, the transceiver block needs to be designed to consume as less power as possible while having the capacity to transmit a huge vo- lume of data at a high absorption rate in biological tissues. Another challenge in this application is the size of the entire design, since an increase in the area leads to a wider opening window and complicates brain surgery. Further, an increase in the area makes the system more expensive.

Recently, many BMIs have been published, such as [8] in which there are 64 neural recording channels and it consumes 330 µW of power. This system occupies an area of 4.6 mm x 4 mm, including the transmitter and AFE. Further, another paper has been published in [9], which presents another 128-channel neural recording and electrical stimulating interface. Each electrode can be used as a recording or stimulating channel. This system is also designed to be modular with eight channels in

2 each module; it occupies a space of 3.5 mm x 2.5 mm without a transmitter block, and consumes 9.3 mW of power. In 2010, a paper was published in [10], which provides 64 recording channels with a custom probe and an integrated front end. In [6], an inductively powered 32-channel wireless neural recording system was presented, whose the front end is based on a PWM converter.

Figure 1.3 – Block diagram of the conventional AFE.

In 2012, a 96-channel neural interface which consumes 68 µW per channel was published in [11]. In 2013, a 100-channel wireless neural recording interface was demonstrated in [12]. Another neural interface was created in 2013, with 100 channels consuming a total of only 1 mW [13]. Recently, in 2014, two articles were published on neural recording, one with 455 probes and 52 active channels and another with 26,400 recording probes and 1024 active recording channels in [14,15], respectively.

Apparently, the number of recording channels is being increased; consequently, the analog front end of each channel must be designed efficiently. It must occupy an area as small as possible and consume as little power as possible. To understand a BMI and to be able to optimize it, all the blocks within an AFE must be partially studiedy. A block diagram of the AFE is illustrated in Fig. 1.3.

1.2 Literature Review : Low-noise Amplifier Design

In this section, we discuss low-noise amplifiers. To improve noise performance of an LNA, first, noise sources in an amplifier must be introduced. The main sources of noise in an amplifier are flicker noise and thermal noise. Thermal noise is generated in all types of real resistors, and since transistors produce an internal resistance which is related to gm, they provide thermal noise as well. The point is that in order to calculate the input referred noise, the output noise power must be divided by the 2 gain of the transistor powered by two (i.e., gm)[16]. Thus, every parameter that increases the gm will decrease the thermal noise, such as W/L, and drain current and mobility (µ). Since the mobility of electrons is approximately three times the mobility of holes, NMOS transistors are less noisy than PMOS transistors in the same size and drain current.The other important source of noise in amplifiers is called flicker noise. This type of noise is inversely proportional to frequency (1/f). This noise could be a considerable problem in very low frequencies because of its inverse proportionality to frequency. Moreover, this noise is inversely related to the size of the transistor, and PMOS transistors inherently provide less flicker noise than NMOS transistors.

Since working bandwidth in neural activity recording begins from 1 Hz or even less [17], the main problem in LNA design is flicker noise. Consequently, all the designs in this area are made by large

3 PMOS input differential pairs. The principle of a neural LNA with a high-pass filter and capacitive feedback is depicted in Fig. 1.4. In this figure, to provide a very low cut-off frequency, pseudo resistors are used [17]. Pseudo resistors yield a huge resistor value, but they are nonlinear. For small input signals, they are approximately linear [17]. Using pseudo resistors causes very low cut-off frequency to be achievable using small capacitors in the range of a few pF. Thus, it becomes possible to implement in-chip capacitors. In [17], a current mirror op-amp topology with cascode output stage was used as

CF Vin CI + Ref _ CI

CL CF

Figure 1.4 – Neural amplifier structure. the LNA core. This OTA structure is illustrated in Fig. 1.5. However, the current mirror op-amp has a

Vdd

Bias -

In- In+ +

Out Out

Figure 1.5 – Current mirror low noise OTA.

4 good frequency response and slew rate, but it is not the best topology considering noise performance.

As its input stage is biased at a lower portion of the total bias current, a relatively smaller gm has the same power consumption [16]. One of the other op-amp topologies which has been used frequently thus far and has better noise performance is the cascode circuit. There are two different cascode topologies : telescopic cascode [9, 18, 19] and folded cascode [11, 20–23]. The telescopic cascode circuitry is simpler than the folded one, since the number of transistors is smaller. It is shown in Fig. 1.6. In the telescopic cascode, if the input signal has the same DC level as the output node, it makes

VDD

V Bias

In+ In- Vbp

Vbn Out

Figure 1.6 – Telescopic cascode low noise OTA. the output swing highly limited. This happens because, normally, the output node DC level is at the middle supply voltage. Thus, if the input DC level is in the middle of the supply voltage, it implies that either the gate-source voltage of the input transistors is high, or the drain-source voltage of the tail current provider transistor is high. Both these voltages increase the overdrive voltage (Ve f f ) of the transistors at the input node or the tail. The better topology is to use the folded cascode. The folded cascode topology circuit diagram is illustrated in Fig. 1.7. When it comes to comparing the performances of different topologies, design architectures, and trade-offs, the figure of merit factors are useful. In this case, the figure of merit introduced in [24] is termed Noise Efficiency Factor (NEF). It is presented in the following manner : r 2 · Itotal NEF = Vrms,in (1.1) UT · π · 4KT · BW

, where Vrms,in is the input referred noise, Itotal is the total current of the OTA, UT is approximately 25 mV, 4KT is the temperature factor in Kelvin, and BW is the bandwidth. Considering the NEF factor,

5 VDD VDD

V Bias Vbp In+ In-

Out Vbn2

Vbn1

Figure 1.7 – Folded cascode low noise OTA the best topology that can provide better noise performance with the same area is the complementary differential amplifier. The self-biased complementary differential amplifier is depicted in Fig. 1.8. This

VDD

V Bias

In+ In- Out+ Out_

Figure 1.8 – Complementary differential low noise OTA. topology has been used in [25–28]. This design doubles the SNR ratio, utilizing the same transistor sizes and power consumption; this is possible because the gm from the NMOS transistor is added to

6 the gm of the PMOS transistor in each leg of the differential pair.

There are some innovative ideas, like sharing some parts of the LNA [29], which could be common to all the other input channels. In [19], a shared reference node leg telescopic cascode LNA has been used. This is illustrated in Fig. 1.9. in this figure, In+ path has X times wider transistors comparing to the other paths (i.e. Inx-). The disadvantage of this design is its common mode gain which leads to inter-channel cross-talk.

VDD

V Bias

In+ In1- In2- Inx- Vbp

Vbn Out1 Out2 Outx

Figure 1.9 – The partial OTA sharing.

The most important source of the noise in neural activity recording applications is flicker noise. Conse- quently, since PMOS transistors produce less flicker noise, they are preferred as the input stage tran- sistors. Also, larger transistors contribute less flicker noise [16]. Moreover, there are several different topologies that could be used as the LNA topology, and each one has its advantages and disadvan- tages. It is even possible to combine certain topologies with certain innovative ideas to improve their performance.

1.3 Literature Review : Filter Stage and Second-gain Stage

The next stages are the filter and gain stages to meet the input requirements of the ADC block. In this section, the filter and gain stages are studied. As different signals and features can be targeted to be monitored in a brain-machine, different filter bandwidths and gains are needed. Generally, there is a need for a high-pass filter to eliminate the DC offset and input low-frequency changes caused by electrochemical reactions between the probe and the body. Since there are certain signals from the

7 brain that are categorized in frequencies as low as 1 Hz or even lower, the high-pass filter has a very low cut-off frequency. This implies that there is a need for a significant RC ratio. In the neural activity recording application, the suitable probe is a very high impedance probe. Therefore, the high-pass filter, which is normally placed at the input and directly connected to the probe, may affect the probe characterizations. Thus, it is preferable that the input resistor be as big as possible. Moreover, it also helps to have a smaller capacitor to provide a low cut-off frequency. The idea of having a very high resistor value is to use pseudo resistors. This concept has been introduced in [17]. The LNA, with its high-pass filter, has been shown in Fig. 1.4. An example of using pseudo resistors is shown in Fig. 1.10. One advantage of using pseudo resistors is that it makes the cut-off frequency achievable by

VTune

CF Vin CI + Ref _ CI

CF VTune

Figure 1.10 – High pass filter using programmable pseudo resistors. capacitors as small as a few pico farads. It also provides the possibility of tuning the resistance by varying a control voltage. Pseudo resistors have the disadvantage of nonlinearity, but since the neural activity signals are so small, they are approximately linear in that range. The low-pass filter is the other part of the filtering process in this application. Several different ideas on low-pass filter design have been introduced. One is to use a big capacitor at the end of the LNA [30–33]. The other approach is to use more complex circuits like high-order GM-C filters [21, 23]. A sample of GM-C filters used in a neural activity recording is illustrated in the high-pass filter Fig. 1.11. After filtering, the input signal must be sufficiently amplified to be used as the ADC’s input. This gain stage is usually programmable to be suitable for a wide range of applications [34].

1.4 Literature Review : Analog to Digital Converters

When the signal is sufficiently amplified, and is also filtered, the next step is to digitize the recorded signal. In this section, the analog-to-digital converter block is described. The analog signal has to

8 _ + _ + _ _ Gm + _ Gm _ + _ _ + + + + Gm _ _ + _ Gm C1 Gm _ Gm CL C2 Gm Inductor

Figure 1.11 – A 3rd order GM-C low-pass filter using LC structure

be sampled before being digitized. Then, the sampled signal is compared to the reference levels and yields the digital number corresponding to the input analog value. A simple description of an ADC is presented in Fig. 1.12. Depending on the number of bits on the digital side, the number of voltage

- Continuous Time - Digital Time CLK CLK - Digital - Continuous Amplitude - Continuous Amplitude - Analog - Analog

Vin OUT

Sampler Quantizer 0100010011

Figure 1.12 – A simple description to ADC functionality

levels to be compared to the sampled input are provided. These voltage levels determine the resolution of the represented signal on the digital side. The more the comparison levels, the more accurate the conversion will be. The concept of comparison to the discrete voltage levels is presented in Fig. 1.13. These discrete voltage levels are created using a digital-to-analog converter (DAC). The accuracy of the ADC is directly dependent on the accuracy of this DAC. There are several errors that may be found at the converted digital signal, whose references are the errors in the DAC. These errors are due to the input voltage offset, nonlinearity, and the quantization noise. The offset is that the converter does not provide the digital value of zero when the input analog signal is at the zero level. The nonlinearity error is caused by a nonlinear relation between the converter’s output and its input analog signal. Finally, the quantization noise is the difference between the demonstrated signal output of the converted digital signal and the input analog signal.

9 V12 V11 V10 V9 V8 V7 V6 V5 Amplitude V4 V3 V2

V1 ` Time

Figure 1.13 – Comparison to the discrete voltage levels

1.4.1 Successive Approximation Register ADC (SAR)

Depending on the applications and number of effective digital levels, there are numerous types of ADCs. Here, only those ADCs that have been used in neural recording applications are studied here. The most used ADC in neural recording applications is the successive approximation ADC (SAR) [1,23,32,35]. The SAR ADC comprises a comparator, a DAC, and a digital control block. An example of SAR ADC is presented in Fig. 1.14. In [35], an SAR converter with an internal gain is introduced.

CLK SAR Control Vin + Register

_

Output Digital Word Output Register D0 Output D1 DAC Dn

Figure 1.14 – Successive approximation ADC

This converter amplifies the input signal with a programmable gain controller. In [1] and [32], a logarithmic SAR converter has been proposed, with a logarithmic relationship between the digital output value and its analog input. In a logarithmic converter, the small input values are considered as the less critical signal, and the larger amplitudes are magnified. In a neural recording application, it is useful to detect impulses. A comparison between a linear ADC converter with logarithmic converters is provided in Fig. 1.15.

10 Figure 1.15 – Comparison between linear ADC and logarithmic ADC [1]

1.4.2 Sigma Delta Converter

The other most frequently used ADC in neural recording applications is the sigma-delta converter [36–40]. A sigma-delta converter is composed of a closed loop system. In this converter, the output digital signal is converted to an analog representation by a DAC, which is located in its feedback. The recreated analog signal is subtracted from the input signal to evaluate the error. The error is integrated at the forward path, and this integration will cause a decrease in the error in the low frequencies. A block diagram of the sigma-delta converter is depicted in Fig. 1.16. This block diagram can be

Integrator CMP X(z) E(z) z-1 Y(z) +_ -1 1 - z

DAC

Figure 1.16 – Block diagram of a first order sigma-delta converter modified as the one shown in Fig. 1.17, which shows the quantization noise source. Consequently, the error signal E(z) can be calculated in the following manner :

E(z) = X(z) −Y(z) (1.2)

11 Integrator N(z) -1 Y(z) X(z) E(z) z + +_ -1 + 1 - z

DAC

Figure 1.17 – The modified model of the first order sigma-delta converter containing quantization noise.

Therefore, the output signal Y(z) can be calculated using the following equation :

E(z) · z−1 Y(z) = + N(z) (1.3) 1 − z−1 Now, it is possible to rewrite (1.3) in the following manner :

X(z) · z−1 Y(z) · z−1 Y(z) = − + N(z) (1.4) 1 − z−1 1 − z−1 z−1 X(z) · z−1 Y(z)(1 + ) = + N(z) (1.5) 1 − z−1 1 − z−1 1 − z−1 + z−1 X(z) · z−1 Y(z)( ) = + N(z) (1.6) 1 − z−1 1 − z−1 1 X(z) · z−1 Y(z)( ) = + N(z) (1.7) 1 − z−1 1 − z−1 Y(z) = X(z) · z−1 + (1 − z−1)N(z) (1.8)

Considering m integrators in the forward path, (1.8) can be transformed to

Y(Z) = X(z) · z−m + (1 − z−1)mN(z) (1.9)

( Y(z) −m STF (Z) = = z X(z) (1.10) Y(z) −1 m NTF (Z) = N(z) = (1 − z ) This implies that the system transfer function is a delay by length of m, and there will be a noise shaping of the order of m as well. The quantization noise spectrum is more like white noise in the bandwidth of the input signal. However, when a sigma-delta converter noise shaping is applied to it, this noise is shaped as illustrated in Fig. 1.18. Sigma-delta converters are known as oversampling rate converters. Compared to the SAR converter, which is a Nyquist rate converter, the number of samples per cycle is much more than that for the SAR converter. On the other hand, compared to SAR converters, in the sigma-delta structure, there is no need for digital control logic. Moreover,

12 Figure 1.18 – The noise shaping benefit of using a sigma-delta converter. if the sigma-delta converter is made as a one-bit converter, the DAC circuit in the feedback loop is merely a straight wire. Generally, the complexity of the one-bit sigma-delta converter is less than the SAR converter. In [36], the sigma-delta loop is created in the current domain. Consequently, a single capacitor plays the role of the integrator. In addition, it plays the role of the anti-aliasing filter as well. Further, in [41], the impact of using passive integrator on the behavior of the sigma-delta converter was studied. It was revealed that it is possible to implement the integrator circuit by a passive integrator to minimize power consumption.

1.5 Literature Review : Optimizing Brain Machine Interface

In this section, we explain how to optimize the design. These techniques are extracted from different resources. First, there is an explanation in [17] that considers the parasitic input capacitor, which affects the signal-to-noise ratio at the input of the LNA. Since there is a DC coupling capacitor (that is, high-pass filter) at the input nodes of LNA, there will be a capacitive voltage divider that considers the parasitic input capacitors of the LNA.

Chigh−pass VLNA,in = VProbe (1.11) Cparasitic,LNA +Chigh−pass This problem becomes worse when there is a need to minimize the noise level of the LNA. In this case, the size of the input transistors of the LNA must be enlarged. Enlarging the input transistor size leads to increasing the parasitic capacitance at the input node. In [11], there is a technique to decrease the effect of the parasitic capacitor at the input node of the LNA. The technique is to add two capacitive positive feedback from the output of the LNA to its inputs. This technique is presented in Fig. 1.19 as MOS-capacitors M3 and M4.

In [42], the authors discuss how to optimize the ADC block. There are several considerations from [42], which are summarized here. The first one is regarding the effective number of bits that could be achieved from an ADC in a neural recording application. In this application, the high impedance probe is a must. For an electrode with a resistance of 1 M ohm operating at 27 degree centigrade

13 Ibias M1 M2 Vin+ Vin-

M3 M4 i1 i2

Figure 1.19 – The parasitic input capacitor effect removal

with a 10 kHz recording bandwidth, the RMS noise voltage is 12.6 µV. Moreover, there is as much background noise, which is a sum of many smaller spikes, as thermal noise [16]. In general, the maximum amplitude of extracellular spike potentials is smaller than 1 mV, and the noise is around

20 µVrms for a probe resistance of 1 M ohm. Therefore, the SNR of the input signal is approximately 34 dB. This implies that regardless of how large the number of bits of the ADC is and how small the amplifier noise is, the system’s effective number of bits cannot exceed six bits. Therefore, it is reasonable to make the ADC’s SNR the same as that of the input signal, and make the amplifier’s input equivalent noise negligible, to achieve as large an SNR as possible (in this case, six bits).

Optimizing the number of ADCs per channel to minimize the power consumption of the system re- quires one ADC per channel. However, if the goal is to reduce the power consumption and area of the system simultaneously, the optimized number of ADCs per channel is one ADC for 16 recording channels [42].

1.6 Thesis Outline and Summary of the Contributions

In the following chapters of this thesis, we provide a deep analysis and optimization of the front-end building blocks, and we propose new structures with better performances.

Chapter 2 is devoted to a novel current reuse front-end. The following are our main contributions :

- Noise analysis of the conventional structure.

- Proposing the new current reuse structure with less noise contribution and less power consumption.

- Verifying the proposed architecture using the measurement results from the chip implemented in CMOS 180-nm technology.

14 - Performing an in−vivo experiment to show the performance of the structure.

In chapter 3, we introduce a new multiplexed Sigma-Delta converter. Our main contributions in this regard are listed below :

- Presenting the analysis on the conventional incremental Sigma-Delta structure.

- Simulating the power spectral density using the conventional structure.

- Proposing a new multiplexing scheme.

- Presenting the advantages of the proposed architecture with simulation results.

- Providing measurement results obtained from the chip implemented in CMOS 180-nm technology.

Chapter 4 presents the ultra-low power Sigma-Delta converter, which consumes only 110 nW. Our contributions in this regard are listed below :

- Analyzing the Sigma-Delta structure.

- Proposing a new circuit using a 0.6 V power supply working in the subthreshold region.

- Providing the post-layout simulation results with corner analysis.

15 Chapitre 2

A Low-Power Current-Reuse Analog Front-End for High-Density Neural Recording Implants

Résumé

L’étude de l’activité cérébrale in vivo nécessite la collecte simultanée de signaux bioélectriques pro- venant de plusieurs microélectrodes afin de capturer les interactions neuronales. Dans ce chapitre, nous présentons un nouveau frontal analogique (AFE), qui peut être étendu à un très grand nombre de canaux d’enregistrement, grâce à sa petite taille faite sur silicium et à sa faible consommation d’éner- gie. Cette AFE à réutilisation de courant, qui comprend un amplificateur à faible bruit (LNA) et un amplificateur à gain programmable (PGA), utilise une nouvelle topologie de miroir de courant entière- ment différentielle utilisant moins de transistors et améliorant plusieurs paramètres de conception, tels que la consommation d’énergie et le bruit, par rapport aux implémentations de circuit d’amplificateur de réutilisation de courant précédentes. Nous montrons que l’amplificateur de réutilisation de courant proposé peut fournir un facteur d’efficacité de bruit théorique (NEF) aussi bas que 1,01, qui est le NEF théorique le plus bas fourni par une topologie LNA. Un AFE à réutilisation de courant à 4 canaux mis en œuvre dans une technologie CMOS de 0,18 µm est présenté comme une preuve de concept. Les circuits capacitifs du réseau en T sont utilisés pour diminuer la taille des condensateurs d’entrée et augmenter la précision du gain dans l’AFE. La performance mesurée de l’ensemble du système est présentée. La consommation totale par canal, y compris le LNA et le PGA, est de 9 µW (4,5 µW pour LNA et 4,5 µW pour PGA), pour un bruit d’entrée de 3,2 µV rms, atteignant une NEF mesurée de 1,94. L’AFE entière présente trois gains sélectionnables à 35,04 dB, 43,1 dB et 49,5 dB, et occupe une surface de 0,072 mm2 par canal. Le circuit mis en œuvre a un taux de réjection inter-canaux mesuré à 54 dB. Les résultats d’enregistrement in vivo obtenus avec l’AFE proposée sont rapportés. Il permet de recueillir avec succès des signaux de potentiel d’action extracellulaire de faible amplitude à partir d’une microélectrode à fil de tungstène implantée dans l’hippocampe d’une souris de laboratoire.

16 Abstract

Studying brain activity in-vivo requires to collect bioelectrical signals from several microelectrodes simultaneously in order to capture neuron interactions. In this chapter, we present a new current-reuse analog front-end (AFE), which is scalable to very large numbers of recording channels, thanks to its small implementation silicon area and its low-power consumption. This current-reuse AFE, which is including a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), employs a new fully differential current-mirror topology using fewer transistors, and improving several design parameters, such as power consumption and noise, over previous current-reuse amplifier circuit implementations. We show that the proposed current reuse amplifier can provide a theoretical noise efficiency factor (NEF) as low as 1.01, which is the lowest reported theoretical NEF provided by an LNA topology. A 4-channel current-reuse AFE implemented in a CMOS 0.18-µm technology is presented as a proof-of- concept. T-network capacitive circuits are used to decrease the size of input capacitors and to increase the gain accuracy in the AFE. The measured performance of the whole AFE is presented. The total power consumption per channel, including the LNA and the PGA stage, is of 9 µW (4.5 µW for LNA and 4.5 µW for PGA), for an input referred noise of 3.2 µVrms , achieving a measured NEF of 1.94. The entire AFE presents three selectable gains of 35.04 dB, 43.1 dB and 49.5 dB, and occupies a die area of 0.072 mm2 per channel. The implemented circuit has a measured inter-channel rejection ratio of 54 dB. In-vivo recording results obtained with the proposed AFE are reported. It successfully allows to collect low-amplitude extracellular action potential signals from a tungsten wire microelectrode implanted in the hippocampus of a laboratory mouse.

2.1 Introduction

Neural recording systems featuring several parallel readout channels enable neuroscientists to study brain neurodynamics in-vivo. Such invaluable information is critical to study and to understand the functions of biological neural networks. Moreover, such devices open up opportunities for building feedback systems to help patients with spinal cord injuries, Parkinson’s disease and other chronic neurological diseases. State-of-the-art neural recording systems consists of two main parts : 1) an implantable device typically including a data acquisition unit, a power management unit (using either a wireless power transmission link [43] or a small battery as power source [44]), as well as a wireless transmitter, and 2) an external base station made of a wireless receiver connected to a host PC [3]. Thus, the design of a suitable multichannel neural recording system must address several critical challenges. Among others, it must handle a large number of low-noise amplifiers (LNA) (typically one per channel) under stringent power budget [17]. As it must interface with implanted microelectrode arrays presenting several recording sites, the small pitch of the microelectrode arrays (a few hundred micrometers typically) usually determines the circuit density and overall system area. Heat dissipation, which needs to be kept as small as possible not to harm tissues, also puts limits on power consumption. For instance, it has been shown that a local temperature rise of only a few °C can harm adjacent tissues [45]. Power is often provided to the recording system by a small battery or by a wireless

17 power transmission scheme [44], which also contributes to power limitation. Additionally, the LNA circuits must present very low-noise, so the weak neural signals can be properly collected, and they must suppress the microelectrode potentials to avoid large offset voltage at the input of the LNA [17]. The LNA usually determines the overall signal-to-noise ratio of a given neural signal recording device. Therefore, the design of a suitable LNA is critical for this application as it must present low-input noise and low-power, while being scalable to very large numbers of recording channels (typically hundreds [15]). Several analog front-end (AFE) topologies were proposed to address these requirements and challenges. A robust approach consists of using an ac-coupled capacitive feedback topology consisting of feedback capacitors implemented around an operational transconductance amplifier (OTA) [17], as a first stage LNA. Such feedback topology, the goal of which is to properly amplify the neural signal while removing the electrode potentials, often uses very large resistive elements known as pseudo- resistors [17], in parallel with feedback capacitors to bias the amplifier and to create a very large-time constant high-pass filter for suppressing the dc offset voltage of the electrodes, the low-frequency noise and the drift.

In this chapter, we first review the principle of current reusing amplifiers (Fig. 2.1) which prompt for very low power consumption designs. We then provide a noise analysis of this circuit topology detailed in Section 2.2.2, and we propose a new current-reuse AFE circuit, including an LNA and a programmable gain amplifier (PGA), which is improving previous implementations, in Section 2.2.3 and Section 2.2.4. Additionally, we discuss the utilization of a capacitive T- network in the imple- mentation of the LNA (Section 2.2.5 and 2.2.6) to implement small capacitors values with very high accuracy for decreasing the size of the input capacitors of the LNA. Then, in Section 2.2.7 we ana- lyze the noise performance of this new current reuse circuit and we show that it can reach the lowest reported theoretical noise efficiency factor (NEF). The measured performance, as well as in-vivo re- sults obtained with this front-end design fabricated in a CMOS process, are presented in section 2.3. Finally, conclusions are drawn.

2.2 CURRENT REUSE ANALOG FRONT END OVERVIEW

Previously, several efforts have been devoted to improve the size, the precision and the NEF of biome- dical signal recording LNAs [46]. Several energy-efficient circuit topologies were introduced for that purpose, like the component sharing arrays [20], or the self-biased fully-differential structure [19]. Furthermore, specific circuit techniques have been proposed to improve further the noise vs power tradeoff, such as folded cascodes with low-current folds [20], reference electrode sharing [19], gm boosting via current-splitting [47], and complementary inputs devices [48] or back-gate driven de- vices [49]. Despite this progress that is improving current techniques, an integrated AFE design sca- lable to thousands of channels for collecting the signals of large groups of neurons at once is still mis- sing. Recently, an orthogonal current-reuse structure has been presented in [50] to improve previous techniques. Such an orthogonal current-reuse structure is attractive since it yields ultra-low power by properly operating under very low-voltage supplies, without affecting the noise performance. Further-

18 Stacked Input Recombination Differential Pairs I Output Stage Vin1+ + CH1 _ io1 I Vin1- v VOut1 I/2 I/2 Vin2+ Vin2+ + + CH2 CH2 io2 I _ _ VOut2 Vin2- Vin2- v I/4 I/4 Vin3+ Vin3+ i + + o3 I CH3 CH3 V _ _ v Out3 Vin3- Vin3- I/8 I/8 Vin4+ io4 + + I V Vin4+CH4 CH4 Out4 _ _ v Vin4- Vin4-

Figure 2.1 – Conceptual representation of a four-channel stacked current-reuse amplifier. The input differential pairs share the same supply currents and the recombination and output blocks provide an output signal that is related to each corresponding input. more, low-power consumption and robust crosstalk suppression between the stacked amplifier parts makes the orthogonal current-reuse structure (Fig. 2.1) a well-suited solution for the design of a high- performance neural recording AFE. As shown in Fig. 2.1, a current-reuse structure consists of stacked differential input pairs, which converts the input voltages into currents, a current recombination block, which separates the output currents assigned to each input signal, and an output stage, which uses the recombined currents to generate an output voltage that corresponds to a given low-amplitude input signal [50]. The voltage headroom required in each input differential pair is minimized by operating each input pair transistor in the sub-threshold region.

2.2.1 Principle of Current-Reuse Amplifier

The schematic of a stacked current-reuse amplifier previously presented in [51] is shown in Fig. 2.2. A two-stacked input topology is shown for simplicity. Such a current-reuse circuit topology presents several stacked input differential pairs separated across a binary tree structure in which each transistor of an input pair has at most one stacked children input pair [50].

1/2 1/2 Since gm = (2µCox(W/L)Id) and Vgs = Vth + (2Id/(µCox(W/L)) equivalent transconductances and gate-source voltages are maintained across all stacked input pair transistors by using half the transistor size in the children branches compared to the transistors of the parent branches, and by using half the current in the children branches compared to the current flowing into the parentbranches. Then, a single current source can be employed to bias all stacked differential input pairs at once,

19 Two stacked input-stage Recombination output stages

Ibias current-reuse structure Stage1 IRecomb IRecomb IRecomb IRecomb 2 2 2 2 M1 M2 W W M19 Vin1- Vin1+ V2 V3 V4 V1 V3 V2 V4 L L M20 M22 M24 M26 Stage2 V1 M21 M23 M25 M3 M4 Vin2- M5 M6 B W/2 W/2 W/2 W/2 : io1 io1 Vin2+ Vin2+ io2 io2 L L L L Vcas,P V 1 M27 M28 Vcas,P cas,P M29 M30 Vcas,P in_o1 in_o1 in_o2 in_o2 V3 V4 V2 V1 VOut1+ VOut1- VOut2+ V M15 M16 M17 M18 Out2- V i3 i4 Vbn i2 i1 cas,N Vcas,N Vcas,N Vcas,N V M11 M12 M13 M14 Vbn CMFB CMFB bn M31 M32 M33 M34

imirror M7 M8 imirror imirror M9 M10 imirror 4 4 4 4 M35 M36 M37 M38

Figure 2.2 – A conventional two-stage folded-cascode current reused amplifier. Two stacked input differential pairs share a same bias current source and each recombination output stage consumes B times the Ibias where B should be made smaller than 1. The common mode feedback circuits are also depicted. the tail currents of which are coming from the previous stages. Indeed, since the same total current

flows into Stage 1 and Stage 2 (Fig. 2.2), both stages have equal overall gm values. The small signal currents output i1,i2,i3,i4 are independent and linear combinations of the several output currents that are derived from one output branch which corresponds to a given stacked input pair. For instance, in Fig. 2.2, Stage 1 has a single input pair, while Stage 2 has two input pairs, having identical input voltages Vin2+ and Vin2− , in parallel. Then, in order to generate Vout1− and Vout1+ , the corresponding small signal output currents io1− and io1+ are re-constructed by summing output currents i1 , i2 and i3 , i4 (Fig. 2.2) respectively in the Recombination output stage 1. Similarly, Vout2+ and Vout2− are generated by summing i1 , i3, and i2 , i4 in the Recombination output stage 2. The small signal output currents are given by (2.1) to (2.4).

gm gm i = ( 1 .V ) + ( 2 .V ) (2.1) 1 4 in1+ 4 in2+ gm gm i = ( 1 .V ) + (− 2 .V ) (2.2) 2 4 in1+ 4 in2+ gm gm i = (− 1 .V ) + ( 2 .V ) (2.3) 3 4 in1− 4 in2− gm gm i = (− 1 .V ) + (− 2 .V ) (2.4) 4 4 in1− 4 in2−

2.2.2 Noise Analysis

2 The thermal noise density of a MOSFET can be approximated by (in = 4KTγgm) where K is the Boltzmanns constant (1.38 × 10−23J/K), T is the temperature in Kelvin, γ is a constant (which ap- proximately equal to 2/3 in long-channel transistor processes and 2∼3 in short-channel transistor pro- cesses [46]) and gm is the transconductance of the transistors. Considering a ratio B : 1 between M19∼26 and M15∼18 in the circuit shown in Fig. 2.2, the thermal noise current contribution of all transistors at the output nodes Vout1 and Vout2 are

2 2 2 2 in,o1 = 4KTγ(2B gm1 + 4B gm7 + 4B gm15 + 4gm19 + 2gm35) (2.5)

20 2 2 2 2 in,o2 = 4KTγ(4B gm3 + 4B gm7 + 4B gm15 + 4gm23 + 2gm37) (2.6)

As mentioned above, since the size of M3 is half of M1, and the drain current of M3 is half of M1, gm3 has half the value of gm1 (gm1 = 2gm3). Hence, the input-referred noise is obtained as follows :

2 8KTγ 2gm7 2gm15 2gm19 gm35 Vn,in1 = (1 + + + 2 + 2 ) (2.7) gm1 gm1 gm1 B gm1 B gm1

2 8KTγ 2gm7 2gm15 2gm23 gm37 Vn,in2 = (1 + + + 2 + 2 ) (2.8) 2gm3 2gm3 2gm3 2B gm3 2B gm3 2 2 It can be shown that Vn,in2 = Vn,in1 if (W/L)3 and (W/L)4 are equal to 1/2(W/L)1. In addition, it can be shown that the total supply current Itotal can be expressed by

Itotal = Ibias + Imirror + NIRecomb = Ibias + Imirror(1 + NB) (2.9) where Imirror and IRecomb are the currents flowing in the current mirror (Fig. 2.2) and the recombination output stage, respectively. The total current can be approximated to Itotal = Ibias +Imirror if B is chosen significantly small.

2.2.3 Proposed Current-Reuse Amplifier Design

We propose a new current-reuse structure based on a simplified current-mirror topology (shown in Fig. 2.3) which uses fewer transistors in the signal path compared to the conventional topology shown in Fig. 2.2. Indeed, the conventional circuit (Fig. 2.2) folds the currents i1, i2, i3, i4 through M11∼14, where the currents are being mirrored by M15∼18 towards the corresponding output recombination stages. In the proposed circuit (Fig. 2.3), the currents are mirrored directly by M7∼10, which avoids the utilization of M15∼18, compared to the conventional folded-cascode topology. Therefore, the Itotal of this new circuit is given by

Itotal = Ibias + NIRecomb = Ibias(1 + NB) (2.10) where N is the number of stacked inputs requiring as much recombination stages, NIRecomb is the total supply current of the recombination stages, and B = (IRecomb/Ibias). Thus, Itotal can approach Ibias if a sufficiently small ratio B is used. As for noise analysis of this new proposed circuit, we set a ratio of

B : 1 between M11∼18 and M7∼10 in Fig. 2.3 to find the output current noises of circuit branches 1 and 2 :

2 2 2 in,o1 = 4KTγ(2gm1 + 4gm7 + 4B gm11 + 2B gm27) (2.11)

2 2 2 in,o2 = 4KTγ(4gm3 + 4gm7 + 4B gm15 + 2B gm29) (2.12) Hence, dividing (2.11) and (2.12) by the gain of the LNA gives the input-referred noise :

2 8KTγ 2gm7 2gm11 gm27 Vn,in1 = (1 + + 2 + 2 ) (2.13) gm1 gm1 B gm1 B gm1

21 Recombination Recombination Two stacked input-stage IRecomb IRecomb IRecomb IRecomb I 2 Output Stage 1 2 2 Output Stage 2 2 bias current-reuse structure Stage1 M27 M28 M29 M30

M1 W W M2 M23 A1 M24 M25 A2 M26 Vin1+ L L Vin1- Vcas,P Vcas,P Vcas,P Vcas,P Stage2 VCM VCM Vin2- i i i i M3 W/2 W/2 M4 M5 W/2 W/2 M6 n_o1 n_o1 n_o2 n_o2 VOut1+ VOut1- VOut2+ VOut2- Vin2+ L L L L Vin2+ Vcas,N CMFB Vcas,N Vcas,N CMFB Vcas,N M19 M20 M21 M22 i io1 i i3 i4 i2 i1 o1 o2 io2 V3 V4 V2 V1 V1 V2 V3 V4 V1 V3 V2 V4 M7 M8 M9 M M M M10 1 : B M11 12 M13 M14 15 16 M17 M18

Figure 2.3 – The proposed optimized current reused amplifier circuit. A two-stage current mirror- based current-reuse amplifier topology uses less transistors than previous topologies. The current mir- rors at the input of the recombination output stages scale the output current of the stacked input pairs by a factor of B.

2 8KTγ 2gm7 2gm15 gm29 Vn,in2 = (1 + + 2 + 2 ) (2.14) 2gm3 2gm3 2B gm3 2B gm3 2 2 As for the conventional circuit, it can be shown that Vn,in2 = Vn,in1 if (W/L)3 and (W/L)4 are equal to 1/2(W/L)1. In these conditions, it can be seen that the proposed design has less input referred noise compared to the conventional circuit shown in Fig. 2.2, the noise of which is given by (2.7) and (2.8).

Additionally, its power consumption is reduced since the Imirror formed by transistors M15 18 in Fig. 2.2 are removed in this new design (Fig. 2.3).

Four stacked input-stage Ibias V ds_bias current-reuse structure Stage1 M M1 Wp Wp 2 Vin1+ Lp Lp Vin1+ Stage2

M M4 M M6 3 Wp/2 Wp/2 5 Wp/2 Wp/2 Vin2+ Lp Lp Vin2- Lp Lp Vin2+ Stage3 M4 Wp/4 Wp/4 Wp/4 Wp/4 Wp/4 Wp/4 Wp/4 Wp/4 Vin3+ Lp Lp Vin3- Lp Lp Vin3+ Lp Lp Vin3- Lp Lp Vin3+ Stage4

Vin4+ Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Wp/8 Lp Lp Vin4- Lp Lp Vin4+ Lp Lp Vin4- Lp Lp Vin4+ Lp Lp Vin4- Lp Lp Vin4+ Lp Lp Vin4- Lp Lp Vin4+ i i i i V1 i1 i2 V2 V3 i3 i4 V4 V5 i5 i6 V6 V7 i7 i8 V8 V9 i9 10 V10 V11 i11 12 V12 V13 i13 14 V14 V15 i15 16 V16

Wn Wn Wn Wn Wn Wn Wn Wn Wn Wn Wn Wn Wn Wn Wn Wn Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22

Figure 2.4 – Schematic of the implemented four stacked-input stage using the proposed optimized current reused amplifier circuit. In this design, Wp = 1000 µm, Lp = 0.8 µm, Wn = 80 µm, Ln = 4 µm, Ibias = 2.5 µA.

2.2.4 Current-Reuse AFE Design

We used this improved current-reused amplifier circuit to implement a new advanced neural recording AFE including a four-channel LNA and a four-channel PGA (Fig. 2.4 and Fig. 2.5). Increasing the number of stacked inputs by 2 compared to the circuits of Fig. 2.2 and 2.3 gives 4 times additional

22 output currents to be mirrored and recombined in the output stages. In fact, there are 2n output currents for n input stacked pairs (or stacked stages). Thus, this four-stacked input current-reuse structure has 16 individual currents that must be recombined (Fig. 2.5) in the output stages to provide appropriate output signal voltages.

Although the complexity of the current-reuse amplifier circuit schematic increases exponentially with the number of stacked inputs, it can be shown that the complexity of its physical layout implementa- tion is comparable to a regular LNA with matched transistors. Indeed, to decrease 1/f noise, LNA are typically using large input MOSFET (Fig. 2.6 shows the attenuation of the flicker noise using large transistors), the size of which typically dominates the overall chip area of the circuit. These input de- vices are typically split into several smaller matched devices (often using finger structures) connected in parallel to achieve better matching and better small signal performance. The proposed current-reuse LNA must use large input MOSFET equivalent-size as well to limit noise. These MOSFET are split into several devices across the tree structure, and connected together in a specific fashion, using metal layers, to reflect the given circuit schematic. Therefore, it can achieve equivalent chip area as a regular LNA with matched transistors. Of course, the proposed design has additional complexity at the level of the metal layer interconnections, but this represents minor overhead compared to a well-matched regular LNA design using split transistors in the differential pair. Besides, it should be noted that once

I IRecomb Recomb Vdd 2 2 Wp Wp Lp Lp M3 M4 out Wp/4 Wp/4 L L _ Vcas,P Vcas,P + M1 M2 VCM

VOut1+ VOut1- Vb M5 Vcas,N 2B.Wn CMFB 2B.Wn Vcas,N L L io1 io1

V1 V8 V9 V16 B.Wn B.Wn B.Wn B.Wn Ln Ln Ln Ln

Figure 2.5 – The recombination output stage for one of the outputs related to the four-stacked input LNA (Fig. 2.4). In this design, Wp = 80 µm, Lp = 4 µm, Wn = 80 µm, Ln = 4 µm, L = 1 µm, B = 1/8. the number of stacked inputs of the proposed amplifier have been determined, the number of channels of an AFE can be increased further simply by repeating the given current-reused tree structure, the complexity of which increases linearly with the number of inputs.

On the other hand, while the complexity of the physical implementation can be comparable to a regular LNA with matched input transistors, it can be seen that the power consumption of the tree structure

23 IRN=3 mV

IRN=2.7 mV

Figure 2.6 – The noise simulation of the proposed LNA. remains constant as the number of stacked input channel is increasing, which is a desirable feature for this application A common-mode feedback (CMFB) circuit must be used to stabilize the output common mode voltage of the fully differential output stage. Such a CMFB (Fig. 2.5) is sampling the output common mode voltage through two high-value resistors (implemented with pseudo-resistors [17]), and then compares the sampled voltages with VCM, the desired common mode voltage value, through a none-inverting single-ended differential pair which generates the required bias voltages for

M27 30.

The proposed 4-channel AFE using the new current-reuse structure is illustrated in Fig. 2.7. It uses two four-channel current-reuse structures for implementing four LNAs and four 2nd stage amplifiers at once. As shown in Fig. 2.7, these current–reuse structures allow reusing the same current sources to supply four LNAs at once with I1 and four PGAs at once with I2. In order to maintain identical gate-to-source voltages in all stacked input transistors, each stacked input differential pair is biased at a particular bias voltage, as shown in Fig. 2.7. Bias voltages Vbi are shown in Fig. 2.7, where i is a number between 1 to 4 representing the channel order in the stack. For example, the common mode DC st voltage at the input of the 1 stage Vb1 (Fig. 2.4), is set to Vgs1 +Vds,bias, while the common mode DC nd voltage at the input of the 2 stage Vb2 (Fig. 2.4), is set to Vgs2 +Vds1 +Vds,bias, and so on. To minimize the inter-channel cross talk in this design, it is critical to match all transistors in the differential pairs and in the current mirrors of the recombination circuits [50]. The common centroid technique was used in the physical implementation to improve matching. For common centroid symmetry, the B ratio is chosen equal to 1/8 so it allows putting most of the current in the input stacked differential pairs to improve noise performance.

2.2.5 Parasitic Input Capacitors Analysis

Due to the small amplitude and wide range of the different neural signal modalities (i.e. action poten- tials are between 50 µV and 500 µV, while the local field potentials can be as high as 5 mV [46]), this

24 I1 I2 Vb1 Vb1

Vb2 Vb2

MUX Output Vb3 Vb3 4:1 Buffers

Vb4 Vb4

S1 S0

Vb3 D1 D0 C Cu Cu f3 Cf2

MCu Cf1 C C IN CL C Vin+ + + Vout+ _ _ Vin- Vout- CIN CC MCu Cf1

Cf2 Cu Cu Cf3 D1 D0 Vb3

Figure 2.7 – Block diagram of the proposed analog front-end, which includes four stacked current- reuse low-noise amplifiers (LNA) and programmable gain amplifiers (PGA). The analog multiplexer and outputs analog buffers are also shown. application requires an AFE providing a wide input range and a programmable gain, ranging from se- veral hundred to a few hundreds of V/V. A capacitive feedback amplifier topology is employed in this

LNA design (Fig. 2.7). The gain of the LNA is set by the capacitor ratio CIN/Ceq f . Thus, achieving high gain with this topology requires either using large CIN, which can lead to large die area, or small

Ceq f , which can lead to high sensitivity to mismatch and process variations. Therefore, a T-network capacitive structure [52] is used in this design to provide small capacitors in the feedback network while using bigger capacitor values, which are less sensitive to mismatch. Such a T-network is shown in Fig. 2.8 along with the parasitic input capacitors of the AFE. The T-network equivalent feedback capacitor Ceq f is derived in [52]. For an accurate design, the effect of equivalent capacitors Ceqi and

Ceqo must be taken into account. Otherwise, it can degrade the gain and change the cut-off frequency of the low-pass filter. The equivalent capacitors of the T-network are given by

Cu Cu Ceq f = and Ceqi = Ceqo = (2.15) M + 2 2 1 + M where M is the number of unit capacitors used in the shunt capacitor (MCu). In this design, 7 pF is used for CIN and 0.5 pF is used for Cu with M = 4, which leads to a gain of approximately 38.5 dB in the LNA. However, there is an attenuation factor of 0.67 in this design due to the capacitive voltage divider formed by CIN and the input parasitic capacitance Cp resulting from the gate-to-source

25 Cu Cu Ceqf

Ceqi Ceqo MCu CIN CIN + Vin+ Vin+ + CL CL Cp _ _ CIN Vin- CIN Vin- Ceqf MCu (a) (b) Cp Ceqi Ceqo

Cu Cu

Figure 2.8 – a) The proposed LNA design with the implemented T-network. b) The equivalent circuit. The parasitic capacitor from input transistors are shown as CP.

capacitance of the huge input transistors employed in the differential pairs [17] and Ceqi of the T- network (shown in Fig. 2.8). Therefore, the total gain of the LNA, the value of which is 35 dB, is given by :

CIN CIN GainLNA = · (2.16) Ceq f CIN +Cp +Ceqi +Ceq f where, Cp is the parasitic capacitance of the input transistors M1∼6 in Fig.2.4, which forms a gain attenuation factor with CIN, Ceqi and Ceq f . In order to set the desired low pass cut-off frequency ( fH ),

CL is selected as follows :

gm1 ·Ceq f fH = (2.17) 2π · (2CL +Ceqo).CIN

2.2.6 Implementation of Current-Reuse PGA

The PGA shown in Fig. 2.7 is based on a capacitive feedback amplifier topology as well. The gain of the PGA is set by the capacitor ratio CC/Cfi, which is programmable by selecting different values for Cf through two transmission gate switches controlled by a 2-bit decoder and digital inputs D1, D0.

The selectable capacitor values for Cf (Cf 1,Cf 2,Cf 3) are shown in Fig. 2.7. Therefore, the total gain of the AFE, including the gains of the LNA and the PGA, is described in (2.18).

CIN Cc CIN GainAFE = · · (2.18) Ceq f Cfi CIN +Cp +Ceqi +Ceq f

26 3

B=1 2.5

) 2 B=1/2

min ( B=1/4

NEF 1.5 1.237 B=1/8 1 B=1/16

0.5 1 2 3 4 5 6 7 8 Number of stacked inputs (N)

Figure 2.9 – The minimum NEF versus the number of stacked differential inputs for different B factors. With B= 1/8 and N=4, this design achieves a theorical NEF of 1.237.

2.2.7 Noise and Power Efficiency Factors Analysis

The noise efficiency factor (NEF) [24] is a common figure of merit used to compare different LNA circuit topologies working in the baseband at low frequencies [17]. It is calculated as follows : r 2 · Itotal NEF = Vrms,in (2.19) UT · π · 4KT · BW where Vrms, in is the total input referred noise, UT is the thermal voltage, Itotal is total supply current of the LNA and BW is the desired bandwidth. If gm1 is made big enough in (2.13), such that gm7, gm11 and gm27 can be neglected, and gm is approximated to kId/UT for M1 and M2 biased in the subthreshold region for providing maximum gm/Id ratios [46], Vrms, in can be obtained by r 8 · KTγ ·UT π Vrms,in = · · BW (2.20) kId1 2 Then, using (2.10), the NEF is given by r 4γ(1 + N · B) NEF = (2.21) N · k

For sufficiently small B ratios, such that the supply current of the recombination stages IRecomb is much smaller than Ibias , Itotal in (2.19) can be approximated by Ibias divided by N, since Ibias is used to bias N differential input pairs at once. Under these conditions, the NEF of the proposed current-reuse LNA simplifies to r 4γ NEF = (2.22) N · k where k = 1/2γ = 0.7 in subthreshold regime [46]. Then, the minimum NEF that can be achieved with a 4-channel LNA (N = 4) based on the proposed current reuse circuit with four stacked input

27 Figure 2.10 – Die photograph of the 4-channel analog front-end fabricated in a TSMC CMOS 180-nm process. differential pairs, is found to be 1.01, for small B factors. The NEF is given in Fig. 2.9 for different values of B and N. As it can be seen in (2.21), for small B ratios, the NEF can be decreased further √ by increasing the number of stacked input pairs according to 2.02/ N. For instance, an LNA with 5 stacked inputs using a very small B ratio would allow for a minimum NEF of 0.9 with the proposed topology. A comparison with previously reported LNA topologies shows that the proposed current- reuse LNA circuit achieves the best minimum theoretical NEF compared with other circuits, like the folded cascode amplifier in [46], and the complimentary differential pair-amplifier in [53], which achieve minimum theoretical NEF of 2.02 and 1.41, respectively.

As seen above, an efficient design requires that the total current Itotal approaches Ibias as much as pos- sible, requiring a small B ratio, which imposes that the supply current flowing into the recombination output stages IRecomb, be kept negligible compared to Ibias, the current flowing in the stacked inputs. In this design, which has 4 recombination stages to accommodate 4 stacked input stages, the ratio

IRecomb/Ibias = B equals 1/8. The ratio of 1/8 is to make it possible for a common centroid matched transistors. Other possibilities are shown in Fig. 2.9. Hence, according to (2.10), the total current is

Itotal = Ibias(1+4·1/8) = 1.5Ibias , which is 1.5 times larger than the lowest Itotal considered in (2.22) for this circuit. In addition, the capacitive voltage divider in (2.16), which is due to the parasitic ca- pacitances at the input of the LNA, contributes to slightly degrading the theoretical NEF (see Section 2.2.5). As detailed in Section 2.2.5, the attenuation factor caused by the voltage divider in (2.16) equals 0.67 in this design. When including the gain attenuating factor (see Section 2.2.5), the input-referred becomes r CIN +Cp +Ceqi +Ceq f 8 · KTγ ·UT π Vrms,in = · · BW (2.23) CIN kId1 2 Considering all these practical factors, a NEF of 1.83 is forecasted for a practical circuit prototype. The power versus noise tradeoff achieved by this design can also be assessed using the Power Efficiency

28 Figure 2.11 – Frequency responses (gain and phase) of the AFE for the 4 channels.

Factor (PEF) [54], which is given by

2 2Vrms,in ·VDD · Itotal 2 PEF = = VDD · NEF (2.24) UT · π · 4KT · BW where VDD is the power supply voltage, which equals 1.8 V in this design. Therefore, the minimum theoretical PEF that can be achieved by this proposed design equals 1.83, when very small B ratios are used, and when the effect of parasitic input capacitors is neglected. With B = 1/8, N = 4, and an attenuation factor due to parasitic capacitors of 0.67, a practical PEF of 6.02 is expected for this design.

2.3 Measurement Results

The proposed 4-channel AFE was fabricated in a 180-nm CMOS process from TSMC through CMC Microsystems (Kingston, ON). A photograph of the fabricated chip is shown in Fig. 2.10. The dimen- sions of the whole AFE are 800 µm x 540 µm.

2.3.1 Measured Performances

The measured AFE frequency response is shown in Fig. 2.11. The AFE in-band differential gain can be changed between 35.04 dB, 43.1 dB and 49.5 dB through a selectable gain (as shown in Fig. 2.12), with a 0.7 Hz high-pass corner frequency and a 10 kHz low-pass corner frequency. The proposed AFE has an input range of 4.5 mV at maximum gain, while it has an input range of 24 mV at minimum gain. In Fig. 2.12 the measured gain variations across channels most likely come from the fact that the input and feedback capacitors of each channel were separately matched together to improve the CMRR of this fully differential circuit. Thus, capacitor matching inside each channel was favored in

29 49.5 dB

43.1 dB

35.04 dB

Figure 2.12 – The different measured gain values for one channel in the AFE. this design to the detriment of matching across channel. For improved gain matching across channels, it is recommended to provide capacitor matching across channels as well.

The measured AFE input-referred noise density is shown in Fig. 2.13. The thermal noise floor is 60 √ nV/ Hz from 1 kHz to 10 kHz. The flicker noise, which is minimized by using large input transistors in all stacked input pairs in the LNA, has a corner frequency located at 200 Hz. The input referred- noise integrated from 1 Hz to 10 kHz is 3.2 µV rms for a power consumption of 4.5 µW per channel in the LNA, corresponding to a NEF of 1.94, which is close to the expected value calculated in Section 2.2.7, while occupying a chip area of 0.072 mm2 . For a fair comparison with other designs, the NEF is provided with a gain attenuation of 0.67 included, which is produced by the parasitic capacitance at the input of the LNA. The proposed design achieves a NEF of 1.3 without considering the gain attenuation. Note that the total input- referred noise of the AFE is approximately equal to the input- referred noise of the LNA. To assess the crosstalk performance of the proposed AFE, we measured the Inter-Channel Rejection Ratio (ICRR), which equals 54 dB. The ICRR is defined as follows :

Vout,x,y ICRR = 20 · log10 (2.25) Gainx ·Vin,y where Vout,x,y is the signal measured at the output of a given channel (Channel x), while a signal is connected at the input of another channel (Channel y), and all other channels are grounded. Vin,y is the value in volts of the input signal connected to Channel y, and parameter Gainx is the gain value of Channel x. For this measurement, 1) we selected the maximum gain (i.e. 49.5 dB) of the LNA, 2) we gave an input sinewave Vin,y = 4 mV at 1 KHz to Channel y, 3) and we measured the output signal at the output of another channel (Vout,x,y). The implemented design has a THD of 0.07 percent for a

1 kHz single tone, 1 mVp−p input test signal. Additionally, the proposed design has a PEF of 6.77,

30 -4 10

-6 10 Input Referred Noise -8 10

-10 10 Instrumentation Noise

Amplitude (V/v Hz) (V/v Amplitude -12 10

-14 10 0 1 2 3 4 10 10 10 10 10 Frequency (Hz)

Figure 2.13 – Measured AFE input referred noise when the input of the AFE is shorted. which is close to the theoretical values calculated in Section 2.2.7. For convenience, the same bias current value was used for the LNA and for the PGA. Note that the bias current of the PGA could be decreased without significant impact on the input-referred noise, since it deals with amplified signals. Table 2.1 summarizes the measurement results from LNA and compares the proposed design with most recent reported works. It can be seen that [50] is benefiting from double MiM capacitor provided by 130 nm technology and according to 2.23 bigger input capacitor gives better performance. As it can be seen, its low-power and small size performance makes this proposed AFE scalable to very high channel counts for implementing high-density multichannel neural recording systems. For instance, a 1000 channel system using this proposed current-reuse AFE design would consume only 9 mW, and occupy 1.01 cm2 .

2.3.2 In-Vivo Recording Results

The fabricated AFE chip has been used to perform in-vivo recordings at the Quebec Mental Health Research Institute (CRIUSMQ). The in-vivo experimental setup is shown in Fig. 2.14. In this setup, the fabricated chip is used to collect neural signals from the brain of an anesthetized mouse weigh- ting 23 g. Ketamine and Xylazine with dosage of 100 mg/kg and 10 mg/kg, respectively are used to anesthetize the animal. A reference node is connected under the skin of the animal and four tungsten electrodes with diameter of 75 µm are located in the Hippocampus (2.5 mm depth) of the mouse. The electrodes have a tip resistance of approximately 8 MΩ. Fig. 2.15 shows examples of neural si- gnals recorded from the four implanted electrodes, and sampled at 20 ksps. The output spike signals have amplitudes as high as 300 µVp−p , which makes them easily detectable from the background

31 TABLE 2.1 – Summarized performance of the LNA and comparison

Parameter (LNA) [50][53][55][56][57] This Work Technology 130 nm 180 nm 130 nm 90 nm 65 nm 180 nm Topology Current Comp. Comp. Single- Bulk Current- reuse inputs inputs ended switching reuse VDD (V) 1.5 1.8 1.2 1 1.2 1.8 Power/ch. (µW) 0.80 2.5 1.92 2.85 3.96 4.5 Noise (µVrms) 3.6 2.85 3.8 3.04 2.64 3.2 BW (kHz) 19.9 10 7.2 10 6 9.3 Gain (dB) 36.1 34.1 46 58.7 39 35.04 PSRR (dB) 80 67 75 50 - 80 CMRR (dB) 78 80 85 45 88 76 THD @ 1mVp−p (%) 1.0* 0.07 0.08** 1.6 - 0.07 ICRR (dB) 40 - - - - 54 Area/ch. (mm2) 0.031 - - 0.137 0.053 0.072 NEF 1.64 1.58 2.16 1.93 2.4 1.94 PEF 4.03 4.49 5.59 3.7 6.91 6.77

*The THD is provided for a 16.5-mVp-p input. **The THD is provided for a 3 mVp-p input.

Fixture setup Anesthetized Mouse

Electrodes

Cable to the Computer

CHIP

Figure 2.14 – The in-vivo test setup is performed at the (CRIUSQ) on an anesthetized 23 g mouse.

noise. Fig. 2.15-b shows 135 spikes that have been isolated from one recorded signal with the AFE and aligned. All protocols were performed in accordance with the Canadian Council on Animal Care Guidelines.

32 150mV 450 50ms 150mV

CH1 300 )

V 150

m (

CH2 0 -150

Amplitude -300 CH3 -450

-600 CH4 0 0.5 1 1.5 2 2.5 Time (ms) (a) (b)

Figure 2.15 – (a) Recorded neural activity of each AFE channel from the hippocampus of a mouse. (b) 135 similar action potentials isolated from the recorded waveform and aligned (waveforms are referred to the amplifier input).

2.4 Conclusion

We presented a new current reuse structure which improves previous current reuse topologies with less input referred noise and less power consumption. A four-channel analog front-end has been im- plemented based on this proposed structure and fabricated in a CMOS 180 nm technology. Analysis show that this new four stacked current reuse structure can theoretically achieve a NEF as low as 1.01. In addition, the utilization of a capacitive T-network feedback circuit was discussed in detail to enhance the gain accuracy of the AFE. The total measured power consumption of the whole front-end including an LNA and a variable gain stage is 9 µW (4.5 µW for LNA and 4.5 µW for PGA), with an input referred noise of 3.2 µV rms , while occupying a die area of 0.072 mm2 per channel. The fa- bricated chip was verified in-vivo and succeeded to record spikes of amplitudes as low as 300 µVp−p from the hippocampus of a 23 g anesthetized mouse.

33 Chapitre 3

A TDM-Σ∆ Converter with Time-Interleaved Oversampling for High-Density Neural Implants

Résumé

Cet article présente un nouveau convertisseur Σ∆ multiplexé par répartition dans le temps (TDM) améliorant la précision et la diaphonie grâce à un nouveau schéma de suréchantillonnage entrelacé dans le temps. Au lieu de suréchantillonner successivement chaque canal dans de courts intervalles de temps multiplexés distincts, comme cela est habituellement fait, les intervalles de suréchantillon- nage de même rang sont entrelacés dans le temps afin de répartir le suréchantillonnage du signal de bande de base sur tout l’intervalle d’échantillonnage. Il est montré que le schéma de suréchantillon- nage entrelacé proposé peut améliorer les schémas conventionnels non entrelacés de plus de 33 dB pour des exigences matérielles similaires, ce qui rend le convertisseur proposé bien adapté à une uti- lisation dans des applications bio-implantables sensibles, tels que les implants de surveillance neurale à haute densité. Un prototype de convertisseur suréchantillonné entrelacé de multiplexage de premier ordre utilisant la technique proposée est démontré dans un procédé TSMC à 180 nm. Le convertisseur fabriqué utilise un seul amplificateur opérationnel qui est partagé sur plusieurs canaux pour intégrer séquentiellement des signaux d’entrée entrelacés séparément en utilisant un schéma d’intégrateur à capacités commutées (SC). La valeur intégrée de chaque canal est stockée à l’intérieur d’une batte- rie de condensateurs après chaque intervalle de temps multiplexé et récupérée pour effectuer le cycle

34 d’intégration suivant dans l’intervalle de suréchantillonnage imbriqué suivant. Des condensateurs as- sortis de même taille sont utilisés pour maintenir les valeurs de tension intégrées dans l’intégrateur SC partagé, ce qui fournit des caractéristiques équivalentes (fonction de transfert, gain, etc.) pour tous les canaux de cette conception. La puce fabriquée occupe une surface de 0,01 mm2 par canal, une consommation d’énergie de 5,5 µW /canal, un ENOB de 7,4 bits, une bande passante de 10 kHz et une diaphonie entre canaux de -83 dB.

Abstract

This chapter presents a new time-division multiplexed (TDM) Σ∆ converter that improves precision and crosstalk through a new time-interleaved oversampling scheme. Instead of successively oversam- pling each channel within short separate multiplexed time frames, as is conventionally done, same- rank oversampling intervals are time-interleaved in order to spread the oversampling of the baseband signal over the entire sampling interval. It is shown that the proposed interleaved oversampling scheme can improve conventional non-interleaved schemes by over 33 dB for similar hardware requirements, which renders the proposed converter well-suited for use in sensitive bio-implantable applications, such as high-density neural monitoring implants. A 1st order multiplexing interleaved oversampling Σ∆ converter prototype utilizing the proposed technique is demonstrated in a 180 nm TSMC process through CMC Microsystems (Kingston, ON). The fabricated converter uses a single op-amp that is shared across several channels to sequentially integrate interleaved input signals separately using a switched-capacitor (SC) integrator scheme. The integrated value of each channel is stored inside a ca- pacitor bank after each multiplexed time interval; it is retrieved to perform the next integrating cycle within the next interleaved oversampling interval. Matched capacitors of the same sizes are used for holding integrated voltage values in the shared SC integrator, which provides equivalent characteris- tics (transfer function, gain, etc.) for all channels in this design. The fabricated chip presents an area of 0.01 mm2 /ch, a power consumption of 5.5 µW/ch an ENOB of 7.4 bits, for a bandwidth of 10 kHz, and an inter channel crosstalk of -83 dB.

3.1 Introduction

Neural interfacing microsystems are enhancing our understanding of brain functions, and play a key role in the development of innovative neuroprostheses dedicated to the treatment of several chronic diseases, like epilepsy [58]. Typically, a neural interfacing microsystem includes a low-noise analog front-end (AFE) followed by a low-power analog-to-digital converter (ADC) to collect and digitize the neural signals followed by other building blocks, such as a digital signal processor and/or a data trans- mitter [11], [4]. A conventional AFE usually comprises several cascaded stages, such as a low-noise amplifier, one or several analog filters, a 2nd gain stage, a sample-and-hold circuit (S/H), and an ADC. The measured neural signal is passed through several signal processing stages before being digitized, which is typically performed using a low-power, medium resolution ADC [11], [5], [15]. However, as

35 CH1 MIOSD ADC LNA CH1 ISD ADC FTDM=1/ts LNA CH2 CH 2 Vo-mux LNA LNA Out Vo-mux CMP MUX Out MUX CH3 CH 3 LNA CMP LNA Ci CH4 F1 CH 4 CLK LNA CLK F1 F2 F3 F4 LNA Vf CLK F2 REF REF phase F3 C1 C2 C3 C4 FTDM=Nch. FNyq Gen. OSR F4 Vf Fs=1/ts Fs=1/ts (a) (b)

Figure 3.1 – (a) Block diagram of a four-channel first order incremental Σ∆ converter (IΣ∆), where Nch is the number of multiplexed input channels and FNyq is the Nyquist sampling frequency. (b) Block diagram of the proposed four-channel multiplexed Σ∆ converter with Interleaved Oversampling (MIOΣ∆), where ts is the oversampling interval. the number of neural recording channels is constantly growing [15], conventional multichannel neural implant designs have their limits in terms of power consumption and chip area. In particular, ADCs are amongst the most area-consuming and power-hungry building blocks in this application, as numerous channels must be sampled and converted within very short time intervals [11].

Several recently reported neural signal recording systems employ a successive approximation (SAR) ADC [11]. Such schemes either use one SAR ADC per channel or a single SAR ADC that is shared across several channels using time-division multiplexing (TDM) [11]. The digitized output of the ADC is often wirelessly transmitted to a host system using a specific digital communication scheme [59]. Recently, a TDM analog-to-time converter has been proposed to convert several neural signals into a pulse-width modulated (PWM) signal that can be further time-to-digital converted on the receiver side, where there are virtually no resource limitations [5]. Further, the weak input signals are encoded into a PWM signal using a dual-slope integrating ADC scheme. An efficient approach to convert an input signal to a digital output consists of using a Σ∆ converter. The advantage is that such a converter benefits from noise reduction through oversampling and noise shaping by sampling the input signal at a much higher rate than the Nyquist rate (FNyq), and by applying an error correction loop. The ratio between the sampling rate and Nyquist rate is called the over sampling ratio (OSR). Increasing the sampling rate, and hence the OSR, increases the signal-to-noise-ratio (SNR) and the effective number of bits (ENOB), for achieving a better digital output resolution. TDM Σ∆ converters have been demonstrated previously. In [60], an incremental Sigma-Delta (IΣ∆) converter is designed to handle 20 channels. Further, a pipelined IΣ∆ converter is proposed in [61] to increase the conversion rate, but at the cost of increased complexity and power consumption. However, as demonstrated in Fig. 3.1-a, the manner in which multiplexing and oversampling are performed in these converters can cause harmonic distortion in the output signal by repeating the spectrums of the multiplexed input signals at the Nyquist rate (Fig. 3.1-a), requiring high-order and sharp decimation filters to avoid excessive distortion.

36 ts

Fs Amplitude ISD Noise Shaping tframe=OSR.ts

A

CH CH

CH CH CH CH

1 1 2

1 1 2 3

1 1 F 3F 4F 5F Freq. data

data Nyq 2FNyq Nyq Nyq Nyq

data data data data

50 50

1 2 1 1 Frame1 Frame2 Frame3 (a) ts

Fs Amplitude Noise MIOSD tframe=Nch.ts Shaping

A

CH CH CH CH

CH CH

1 1 2 1 1 1

4 4 4

data data data data data

data FNyq Freq.

1 1 2 3 2 Frame1 1 Frame2 Frame3

(b)

Figure 3.2 – Timing diagram of the output data stream and output spectrum of one channel with oversampling in of the IΣ∆ (a) and in the MIOΣ∆ (b), respectively.

In this chapter, we present a new TDM Σ∆ converter circuit utilizing an interleaved oversampling scheme enabling higher precision than previous solutions (Fig. 3.1-a). This circuit can achieve ultra- low crosstalk between adjacent channels through the proposed scheme and the utilization of a matched capacitor bank. The remainder of the chapter is organized in the following manner. Section 3.2 pro- vides an overview of the proposed multiplexing interleaved oversampling Σ∆ converter, and Section 3.3 describes its design in detail. Section 3.4 presents the measurement results and the last section presents the conclusions.

3.2 System Overview

In this section, the working principle of the IΣ∆ converter is first summarized with respect to TDM and distortion. Then, the proposed TDM scheme and the associated implemented Σ∆ converter design with interleaved oversampling intervals are presented.

3.2.1 Conventional TDM Σ∆ Converter

Fig. 3.1-a depicts a block diagram of a Σ∆ converter with TDM. In this scheme, each channel is successively oversampled within a TDM time interval t f rame = ts · OSR (Fig. 3.2-a), where ts is the

37 Power Spectral Density 0 ISD

-50 MIOSD

) dB

( -100

-150 Power -200

-250 0 2 4 6 10 10 10 10 Frequency(Hz)

Figure 3.3 – Comparison between two TDM Σ∆ schemes. Performance comparison of the propo- sed TDM Σ∆ scheme with interleaved oversampling intervals depicted in Fig. 3.1-b (solid), and the conventional IΣ∆ scheme presented in Fig. 3.1-a (dashed), for a 100 Hz input sine wave for a band- width of 10 kHz and an OSR of 50. Both schemes are tested for second-order Σ∆ topologies. The conventional IΣ∆ scheme generates several harmonics within the bandwidth of interest, while the pro- posed scheme does not. The proposed scheme provides a 33 dB SNDR improvement compared to the conventional scheme, respectively.

system clock. Multiplexing N channels cause a delay between each sampling frame. This delay is equal to (NCH − 1)OSR ·ts , and is repeated at the Nyquist rate. Therefore, the presence of this delay at the Nyquist rate causes to repeat the spectrum of the input signal at the Nyquist rate [62] in the conventional multiplexed method (Fig. 3.2-a). The integrated value stored on capacitor CI is reset after each TDM interval to avoid crosstalk between channels. The outputs of the Σ∆ converter must be decimated afterward to obtain a digital sample representation over a given number of bits. The decimation filter can provide one output digital word per t f rame interval. Thus, for each channel, one digital word is provided at the decimation filter output for every frame (in Fig. 3.2-a). The TDM frames are repeated at the Nyquist rate. Consequently, oversampling is confined within each channel

TDM interval t f rame. This specific type of converter is called an Incremental Σ∆ converter (IΣ∆).

However, as shown in Fig. 3.2-a, confining the oversampling interval within t f rame only, and resetting the integrator of the IΣ∆ converter after each frame interval, cause harmonics and repeated baseband signal spectrums at multiples of the sampling frequency. Such distortion, which can be referred to as multiplexing distortion, can place severe design constraints on the decimation filter, and inevitably causes aliasing and additional distortion (Fig. 3.2-a).

38 Vdd Φ1,3 Converter in VF+ Φ Φ S15 CF Out- Out+ Evaluation phase Φ2,4 Φ3 Φ3 Φ2,4 S7 S13 S14 CI S16 - + IN2+ Φ3 Φ2,4 Φ1 Φ1 Φ1,3 Φ S1 S5 S9 CI S10 IN1+ Φ1 Out S2 Vo + mux CS CMP IN1- Φ1 Vomux- S3 CS Out IN2- Φ3 Φ2,4 Φ1 Φ1 Vdd S4 S6

S11 CI S12 Φ2,4 Out Φ2,4 Φ3 Φ3 Out

S18 + S8 S14 - - + S13 CI Φ1,3 VF- S17 Bias CF (a)

VF+ Φ1,3 Converter in S15 CF Φ2,4 Φ3 Φ3 Reset phase Φ2,4 S7 S13 S14 CI S16 Φ IN2+ Φ3 Φ2,4 Φ1 Φ1 Φ1,3 S1 S5 S9 S10 CI IN1+ Φ1 Out S2 Vo + Φ mux CS CMP IN1- Φ1 Vomux- S3 Out M1 CS M3 M4 IN2- Φ3 Φ2,4 Φ1 Φ1 M2 S4 S6 S11 CI S12 Φ2,4 Φ Φ2,4 Φ3 Φ3 S18 S8 S13 S14 CI Φ1,3 (c) VF- S17 (b) CF

Figure 3.4 – (a) Schematic of the proposed multiplexing interleaved oversampling Σ∆ converter in the evaluation phase. Each input has its own integration capacitor. (b) The proposed circuit in the reset phase performed before each evaluation phase, and (c) the implemented switch circuit.

3.2.2 Time-Interleaved Oversampling TDM Σ∆ Converter

Fig. 3.1-b illustrates the proposed multiplexing interleaved oversampling Σ∆ converter with time- interleaved oversampling (previously presented in [63]). In this scheme, all the input channels (CH1,

CH2,..., CHn) are oversampled successively, and the samples are interleaved in order to spread the oversampling sequences over the entire sampling interval. (Fig. 3.2-b). Hence, this minimizes the sam- pling imperfections and pushes the repeated input signal spectrums at OSRFNyq, which is located far outside the bandwidth of the converter, where it can easily be filtered out by the decimation filter. Fig. 3.1-b presents a block diagram of the associated Σ∆ converter topology implementing the proposed TDM scheme. The outputs of four low-noise amplifiers are multiplexed toward a switched op-amp integrator for processing several input signals simultaneously without the need for using more than one op-amp. A capacitor bank (C1 to C4) is used to hold the current integrated voltage values between the TDM intervals, thereby avoiding crosstalk without having to reset the integrator between the TDM

39 intervals. Each capacitor (C1 to C4) is associated with a specific input channel, and is used to integrate and store one specific input signal.

In contrast with the above-mentioned conventional TDM IΣ∆ scheme, the integrated value in the IΣ∆ is not reset between TDM intervals; thus, the TDM oversampling intervals can be spread over the entire sampling interval to avoid harmonic distortion and aliasing. In the IΣ∆ scheme, the latter are due to repeated baseband signal spectrums at multiple frequencies of the sampling frequency (Fig. 3.2-b). Fig. 3.3 presents a comparison between the output spectrums of a conventional TDM-IΣ∆ converter and the proposed interleaved oversampling TDM-Σ∆ converter. Both schemes use second-order Σ∆ converter topologies, with an OSR of 50, bandwidth of 10 kHz, and 4 multiplexed channels. As is evident in Fig. 3.3, the regular TDM-IΣ∆ scheme yields an SNDR of 31.5 dB, while the proposed scheme with interleaved oversampling yields an SNDR of 64.8 dB.

Φ1 Φ2 Φ3 Φ4 D Q D Q D Q D Q

Set Reset Reset Reset CLK

Reset

Reset Φ CLK

Reset Φ Φ1 D Φ Φ Φ2 Q Reset Φ3 Reset 0/1 Φ4

Figure 3.5 – Schematic of the clock sequence generator and associated timing diagram.

3.3 Time-Interleaved Oversampling Σ∆ System Design

In this application, neural recording systems typically use high-impedance input electrodes (i.e., ty- pically >1 MΩ), while the neural signal, including spikes and field potentials, is known to have a maximum bandwidth of approximately 10 kHz, and a maximum amplitude of 2-mVp−p [4]. Thus, the input signal is expected to include a thermal noise of approximately 12.8 µVrms, thereby provi- ding a maximum input SNR value of 35 dB. Consequently, the maximum achievable ENOB in this application is approximately 5.5 bits [42]. Thus, a resolution of 8 bits is deemed plenty satisfactory for this application. Therefore, a one-bit, first-order noise shaping TDM Σ∆ converter with interleaved

40 oversampling is demonstrated.

Capacitors

Clock sequence SD Converter Generator

Figure 3.6 – Die photograph of the proposed multiplexing interleaved oversampling Σ∆ converter along with its clock sequence generator circuit. The circuit occupies a silicon area of 150 µm × 135 µm.

3.3.1 Switched-Capacitor Op-amp Sharing

The schematic of the proposed time-interleaved oversampling TDM Σ∆ converter is depicted in Fig. 3.4. It includes one shared op-amp, a comparator, an analog multiplexer, a few transmission gates, and a clock sequence generator circuit. The converter takes the input signal (Vomux) and the feedback signal (Vf ), and provides appropriate output values within one clock cycle. A reset phase is provided between each TDM interval to reset the sampling capacitors and minimize inter-channel crosstalk. In this phase, the comparator, the feedback capacitors (CF ), and the sampling capacitors (CS) are reset and the input nodes of the op-amp are connected to the reference voltage through switches S5 and S6. In addition, during the reset phase, all the integrating capacitors are disconnected from the circuit to retain their current integrated value. Switches are used on both sides of the integrating capacitors to avoid dependency of the leakage currents on the input signal and avoid crosstalk (Fig. 3.4-a). In the evaluation phase, an input channel and its corresponding set of integrating capacitors are connected to the shared op-amp. Simultaneously, the input signal is sampled on capacitors CS, while CF are sampling the output signal and feeding it back to the input of the integrator. The comparator provides a new output state while the new integration cycle is being performed, all within one clock cycle. Both operating phases of the proposed circuit (the evaluatingphase and the reset phase) are presented in Fig. 3.4. The SC integrator opamp employs a current mirror topology (Fig. 3.4-a), with pseudo resistor-based common mode feedback to balance the DC level of the output nodes [28]. Capacitors

41 CI, CS, and CF are all equal to 550 fF.

Power Spectral Density 0 OSR=50 SNDR= 46.3 dB -20

SFDR= 74 dB

-40 Cross-talk= -83 dB

)

dB (

-60 Power -80

-100

-120 1 2 3 4 5 6 10 10 10 10 10 10 Frequency(Hz)

Figure 3.7 – Measured PSD from input Channel 2 and measured inter-channel crosstalk. Channels 1 and 2 are given input sine waves of 1 kHz and 2 kHz, respectively.

3.3.2 Dynamic Comparator and Switches

An ultra-low power dynamic comparator is employed [64]. This comparator uses a differential pair with cross-connected transistors at its load to maximise speed and minimize power consumption (Fig. 3.4-a). During the reset phase, the output node of the comparator is set to VDD, yielding "0" or GND at the outputs of the two buffer inverters (Fig. 3.4-b). Further, well-balanced transmission gates with dummy transistors (Fig. 3.4-c) are utilized for implementing switches S1 to S20. The W/L ratio of p-type MOSFETs is selected as three times the ratio of n-type MOSFETs to compensate for the electrons-vs-hole mobility difference in this CMOS process. Two dummy transistors are employed on both sides of each transmission gate to minimize charge feedthrough in the signal path.

3.3.3 Clock Sequence Generator

A chain of D flip-flops (DFF) is used to implement a dedicated clock sequence generator. The sche- matic of the DFF chain along with its input and output signals is depicted in Fig. 3.5. Two clock phases per channel are needed for control. Thus, a two-input channel system requires four different clock phases for control. Therefore, the complexity of the required clocking scheme is linearly related with the number of input channels, whereas the required TDM time interval decreases linearly with

42 the number of channels, for the same sampling interval. For this implementation, ts is equal to 0.5 µs. This design uses the clock phase Φ4 as a synchronization signal to demultiplex the converted signals before decimation.

CH1 CH2

0.1 V 0.1 V 5 mS 5 mS

Output Signal Output Signal Input Signal Input Signal

0.1 V 0.1 V 0.5 mS 0.5 mS

Figure 3.8 – Synthetic neural signal digitized with the fabricated Σ∆ converter after offline decimation in MATLAB.

3.4 Measurement Results

The proposed design was implemented in a TSMC 180-nm CMOS process yielding a chip area of 150 µm × 135 µm. The die photograph of the converter, including the clock sequence generator and all other building blocks (op-amp, comparator, capacitors and switches) is illustrated in Fig. 3.6. A 2- kHz input sine wave was used to test the converter. The measured SFDR 74 dB, SNDR is of 46.3 dB, thereby providing an ENOB of 7.4 bits, which meets the requirements of this application. To measure the inter channel crosstalk, two sine waves of different frequencies (1 kHz for Ch1 and 2 kHz for Ch2) are fed to the inputs of the converter. The measured output power spectrum densities of both channels are presented in Fig. 3.7. As evident from Fig. 3.7, there is no repeated input signal spectrum at the Nyquist frequency and its harmonics. In addition, the measured inter-channel crosstalk is smaller than the noise floor located at -83 dB. The performance of the proposed circuit is summarized and compared with previously published circuits in Table 3.1. The proposed architecture provides the output data at the same rate as the sampling clock, and consumes only 5.5 µW per channel. In order to show the improvement over previous IΣ∆ converters, which may exhibit multiplexing distortion, we compare the theoretical SNDR (noted SNDRtheory) with the measured SNDR (noted SNDRmeas) for all converters included in Table 3.1. Here, SNDRtheory represents the SNDR of the converters free from multiplexing distortion, and it is calculated using the data provided in the corresponding references.

43 TABLE 3.1 – Performance summary and comparison with state of the art.s

Parameter [61][65][66] This Work Year 2015 2015 2016 2017 Topology IΣ∆ 4th IΣ∆ 4nd IΣ∆ 2nd MΣ∆ 1st Order Order Order Order Tech. (nm) 180 180 180 180 VDD (V) 1.2 1.2 1.8 1.8 BW (kHz) 4 3.2 156 10 OSR 40 50 64 50 SNDRtheory (dB) 121.7 130.4 85 53.5 SNDRmeas. (dB) 75.9 82.5 57.7 46.3 ENOB (bits) 12.3 13.4 9.3 7.4 ∆SNDR* (dB) 45.8 47.9 27.3 7.2 Power/ch. (µW) 34.8 18.2 29.5 5.5 Area/ch (mm2) 0.02 0.2 0.0018 0.01 Result Meas. Sim. Meas. Meas.

*∆SNDR is the difference between theoretical SNDR and measured SNDR.

The SNDRtheory is calculated as follows [67]:

πL SNDRtheory = 6.02N + 1.76 − 20log(√ ) + (20L + 10)log(OSR) (3.1) 2L + 1 where, N is the number of bits of the digitizer and L is the order of noise shaping. As a figure of merit, the difference between SNDRtheory and SNDRmeas, noted as ∆SNDR, is provided for all converters in- cluded in Table 3.1. As is evident, the proposed converter has the lowest ∆SNDR by far, which suggests that it has much less multiplexing distortion then conventional schemes.

The fabricated converter was used in an in-vitro test to digitize synthetic neural signals played from an arbitrary function generator and collected using 1 MΩ tungsten electrodes in a buffered saline solution. The synthetic signals were collected, multiplexed, and digitized with the fabricated chip, and then further demultiplexed and decimated offline in MATLAB. Fig. 3.8 presents the decimated digitized output signals that were recorded using two separated channels of the fabricated Σ∆ converter chip, superimposed with the input synthetic signals. The proposed design can digitize the synthetic signal with sufficient precision.

3.5 Conclusion

In this chapter, a new TDM Σ∆ converter with time-interleaved oversampling intervals was presented. Instead of successively oversampling each channel within short separate multiplexed time frames, as is done in conventional designs, the proposed design uses interleaved oversampling intervals for sprea-

44 ding the input signal oversampling intervals over the entire sampling interval, which avoids harmonics and aliasing in baseband. The proposed TDM scheme improves conventional multiplexed schemes with successive oversampling by over 33 dB for equivalent hardware specifications. The presented CMOS circuit implementation uses an op-amp sharing strategy and a capacitor bank for processing multiple channels with a single integrator circuit, which enables the holding of integrated values of each channel between TDM intervals. The proposed circuit was implemented in a TSMC 180 nm CMOS process, and a 550 fF MiM capacitor was used as integration capacitance in the integrator. The design occupies a chip area of 150 µm × 135 µm. The measurement results show that the crosstalk between channels lies below the noise floor and is less than -83 dB. These attractive properties make this design highly suitable for high-density neural recording applications.

45 Chapitre 4

A 110-nW in-Channel Sigma-Delta Converter for Large-Scale Neural Recording Implants

Résumé

L’avancement de la technologie sans fil et des microsystèmes a engendré de nouveaux dispositifs qui peuvent directement interagir avec le système nerveux central pour stimuler et / ou surveiller les ré- seaux neuronaux. Dans cet article, nous présentons un convertisseur analogique-numérique (ADC) sigma-delta à très faible consommation d’énergie destiné à être utilisé dans des implants d’enregistre- ment neuronaux multicanaux à grande échelle. Cette conception proposée, qui fournit une résolution de 9 bits en utilisant un ADC suréchantillonné d’un bit, présente plusieurs caractéristiques souhai- tables qui permettent un schéma ADC dans le canal, où un convertisseur sigma-delta est fourni pour chaque canal, permettant le développement de systèmes évolutifs qui peut s’interfacer avec différents types de microsondes neuronales à haute densité. Le circuit proposé, qui a été fabriqué dans un pro- cessus CMOS 180nm TSMC, utilise une topologie de conformation de bruit de premier ordre avec un intégrateur passif et une tension d’alimentation faible de 0,6 V pour obtenir une consommation d’énergie très faible et une petite taille. L’ADC proposé surpasse clairement les autres conceptions avec une consommation d’énergie aussi faible que 110nW pour une précision de 9 bits (11-fJ par conversion), une surface de silicium de seulement 82µm × 84µm, et l’une des meilleurs figure de mérite publiés dans la littérature et utilisés dans des applications similaires.

Abstract

Advancements in wireless and microsystems technology have ushered in new devices that can directly interface with the central nervous system for stimulating and/or monitoring neural circuitry. In this paper, we present an ultra low-power sigma-delta analog-to-digital converter (ADC)intended for utili-

46 zation in large-scale multi-channel neural recording implants. This proposed design, which provides a resolution of nine bits using a one-bit oversampled ADC, presents several desirable features that allow for an in-channel ADC scheme, where one sigma-delta converter is provided for each channel, thereby enabling the development of scalable systems that can interface with different types of high-density neural microprobes. The proposed circuit, which has been fabricated in a TSMC 180 nm CMOS pro- cess through CMC Microsystems (Kingston, ON), employs a first-order noise-shaping topology with a passive integrator and a low-supply voltage of 0.6 V to achieve ultra low-power consumption and small size. The proposed ADC clearly outperforms other designs, with a power consumption as low as 110 nW for a precision of nine bits (11 fJ per conversion), a silicon area of only 82 µm × 84 µm, and one of the best reported figures of merit among recently published data converters utilized in similar applications.

Figure 4.1 – An implantable brain computer interface.

4.1 Introduction

Brain computer interfaces have greatly enhanced our understanding of brain functions, and play a key role in the development of new prostheses for treating different chronic brain diseases. Typically, such systems include several data acquisition channels (hundreds of them), all operating in parallel. Each channel comprises several cascaded stages, such as a low-noise amplifier, one or several analog filters, a second gain stage, a sample-and-hold circuit (SHA), and an analog-to-digital converter (ADC) [3], [13]. Thus, conventionally, the signal passes through several signal processing stages, each consuming

47 a given amount of power, before being buffered and multiplexed toward an SHA circuit, and then digitized using a low-power, medium resolution ADC [5]. Fig. 4.1 depicts a representation of an implantable brain computer interface. Such a system can be wirelessly powered from outside the body using an inductive link, and can communicate with a base station using either an implanted or external antenna [43]. Thus, small-form factor, low-power, and biocompatibility are critical in this application. However, as the size of the wireless power receiver always needs to be decreased, the recovered power available to power the implant is decreases too. Therefore, low-power consumption is among the most important design parameters in this application. In contrast, the number of monitoring channels in neural recording implants is constantly increasing, but conventional multichannel analog front-end circuits consume too much power, due to several cascaded modules, including fast SHA and ADC circuits [3], which often dominate since each channel must be sampled and converted within a very short period of time.

The recently reported multi-channel neural signal recording implant designs either employ one suc- cessive approximation (SAR) ADC within each channel or share one SAR ADC amongst several multiplexed channels [3]. SAR ADC present low-power, but offer medium precision, and require a complicated clock generator, as well as an accurate and linear digital-to-analog converter (DAC). Then, the digitized output can be wirelessly transmitted to a host device using a specific digital com- munication scheme, after the data undergo digital signal processing and appropriate encapsulation [6].

b

Integrator CMP -1

E(z) + a. z + X(z) +_ -1 Y(z) 1 - z

Figure 4.2 – Block diagram of the first order sigma-delta converter.

Sigma-delta converters are well suited for digitizing low frequency signals, such as neural signals. Such converters do not require a complex clocking circuit, and they can provide high precision. In- deed, they do not need to use a complicated DAC, and they can be built around a simple one-bit quantizer. Recently, a multiplexed Sigma-delta converter has been proposed in [63] to convert several input neural signals into a digital representation with reduced crosstalk. Sharing one ADC per several channels can be a good solution when one wants to optimize power consumption and chip area with

48 0.3V 0.23V

(a) (b)

Figure 4.3 – The error signal at the input of the comparator. a) Sigma-delta converter. b) Feed-forward sigma-delta converter.

SNDR=45.1 dB SNDR=49.3 dB ENOB=7.2 bits ENOB=7.9 bits

SFDR=52dB SFDR=61dB

(a) (b)

Figure 4.4 – The power spectral density of the output signal. a) Sigma-delta converter. b) Feed-forward sigma-delta converter.

equal priority [42]. When the priority is to minimize power consumption, an in-channel implementa- tion (i.e. one ADC per channel) can lead to major improvements [42]. A sigma-delta oversampling converter provides a pulse width modulated representation of the analog input signal. Thus, it acts as an analog-to-time converter, which allows for outsourcing the resource and power hungry time- to-digital converter portion [63] on the external receiver side when combined with a wireless radio transmitter, an efficient scheme for our application. In this chapter, a new sigma-delta converter to- pology using a low-power supply voltage and a passive integrator to reduce power consumption is presented for enabling an in-channel ADC scheme in a large-scale neural recording implant. Sec- tion 4.2 describes the proposed design. Then, performance results are presented in Section 4.3, and conclusions are finally drawn.

49 CS Φ1 Φ1 Φ2 In- S1 S3 Out+ CI fw+ PWM In+ Ref CMP GND In- CI fw- Out- PWM Φ1 Φ2 In+

S2 S4 CS

Figure 4.5 – Proposed circuit implementation of the sigma-delta converter depicted in Fig. 4.2.

Φ Φ1 Φ2 In Out S1 S2 CI CS MP/2 MN MP/2 MN/2 MP MN/2

FeedBack

Φ (a) (b)

Figure 4.6 – (a) Implementation of the subtractor and integrator. (b) Implementation of switches with dummy transistors for minimizing charge injection.

4.2 Circuit Design

The proposed ADC is designed to work with a 0.6 V supply voltage. Minimizing the supply voltage is one of the techniques used to decrease power consumption. It also forces the transistors to work in the sub-threshold region. In the sub-threshold region, the drain current of the transistors is extremely small and it leads to minimize the power consumption of the system. When the input transistors of the differential pairs work in weak inversion, it exhibits nonlinearities. Therefore, a feed-forward topology is used in the proposed design to minimize this effect. The block diagram of such a system is presented in Fig. 4.2. As shown, it includes a feed forward path b that helps to decrease nonlinearities in the sigma-delta converter [68]. Such a feed-forward path adds a representation of the input signal that is weighted by a factor b and summed with the integrated value of the error signal E(z). However, this feed-forward path changes the transfer function [69], it minimizes the variation of the error signal at the input of the comparator leading to minimizing the nonlinearity of the comparator (Fig. 4.3). The effect of adding a feed-forward path to the proposed sigma-delta converter on the power spectral density of the output signal is shown in the Fig. 4.4.

50 Vdd

M9 M7 M8 M10

Φ M5 M6 Φ

Out- Out+ M3 M4

fw - In- M1 M2 In+ fw+

M11=b.M1 M12=b.M2 Φ M11

Figure 4.7 – Schematic of the proposed multi-input comparator circuit.

A novel circuit level implementation of such a feed-forward diagram is proposed in Fig. 4.5. It is built around a passive integrator that takes the subtracted value between input signal X(z) and the output signal Y(z) and charges it in the capacitor CS ; thereafter, this charge is shared with capacitor CI. Then, a four-input latched comparator is located, which allows the addition of the feed-forward signals f w(z) with the integrated error signals In(z), which is charged in CI and provides the output value of Y(z). All the building blocks of the proposed sigma-delta converter are optimized to achieve ultra-low

Figure 4.8 – Die photograph of the proposed sigma delta converter. power. Conventionally, op-amps are utilized to implement integrators in sigma-delta converters, but they are usually the most power-hungry blocks. Then, the higher the noise-shaping order in a sigma delta converter, the higher the number of integrators needed. Therefore, a first-order noise shaping sigma-delta converter topology is utilized to keep the power consumption of the entire design as low as possible. Additionally, in order to further minimize power consumption, a passive integrator

51 is implemented and utilized in this design. The schematic of the implemented passive integrator is presented in Fig. 4.6. The output voltage of such a passive integrator is described below :

CI ·Vout (n − 1) +CS ·Vin(n − 1) Vout (n) = (4.1) CI +CS , which can be simplified and represented in the z domain by

−1 −1 CI · z CS · z Vout (z)(1 − ) = ·Vin(z) (4.2) CI +CS CI +CS

Then, (3) shows that larger CI/CS ratios can provide CI/(CI +CS) closer to 1 and improves the inte- grator. However, it also acts as a capacitor-based voltage divider and provides an attenuation factor of 1/19 (considering that a ratio CI/CS = 18 is selected) on the input signal, as shown in (4). Thus, a smaller input signal at the comparator input can translate to a smaller signal-to-noise ratio (SNR). The sigma-delta ADC can shape any noise produced inside the comparator (including thermal noise, flicker noise, and quantization noise), but having a poor SNR before the comparator can decrease the output signal resolution. In the implemented circuit, a value of CI/CS = 18 was found to found to be optimal with respect to the comparator noise and the convertor effective number of bits (ENOB).

( CI ≈ 1 CI CI +CS , i f = C 1 18 (4.3) S = CS CI +CS 19

V (z) 1 z−1 out (4.4) = · −1 Vin(z) 19 1 − z Moreover, improving the comparator noise performance by increasing the W/L of its input differential pair can necessitate a larger ratio CI/CS in order to further improve the integrator. To design a suitable comparator with four inputs, a dynamic comparator [70] design is employed. The proposed design, presented in Fig. 4.7, has two additional inputs to inject the feed-forward signal at the input of the comparator. In this design, M1 and M2 must be matched to minimize the comparator offset, and M11 and M12 must be matched as well. Finally, M3 and M4 must also be matched, and M5 must be matched with M6. As is evident from Fig. 4.5, input transistors at nodes IN+ and IN- have different DC voltage levels compared to the FW+ and FW- input nodes. Further, the transistors at IN+ and IN- are biased in weak inversion, and the transistors at FW+ and FW- are biased in strong inversion. The ratio of the drain current in weak inversion to the drain current in the strong inversion multiplied by an attenuation factor caused by the implemented passive integrator (1/19), corresponds to a b factor of 6×10−4. The ratio of the drain currents in the weak inversion and strong inversion comes from the technology parameters and are not accessible, so a simulation is made to achieve this value.

4.3 Simulation and Implementation Results

The proposed circuit uses two non-overlapping clock phases that are needed by the passive integrator. This proposed design has been fabricated in a TSMC 180 nm CMOS process and occupies an area

52 (a)

(b)

Figure 4.9 – (a) Output power spectrum density obtained from a transient post layout simulation for an input sine wave. (b) Post-layout transient simulation for a pre-recorded in-vivo neural signal.

of 82 µm × 84 µm, including the non-overlapping clock generator. The chip die photograph of the proposed sigma-delta converter is presented in Fig. 4.8. The proposed circuit uses a 0.6 V supply voltage and has its Vre f nodes connected to 3VDD/4. Post-layout simulation uses a 2 kHz input sine wave to characterize the proposed ADC. The spectrum of the output signal given an input sine wave is depicted in Fig. 4.9-a. Then, a pre-recorded in-vivo neural signal is played as the input of the ADC in a post-layout simulation to show the performance of the proposed circuit with realistic data. The output of the circuit was exported from Cadence Virtuoso to MATLAB and then decimated. The obtained output waveform is illustrated in Fig. 4.9-b. Post-layout simulation results are summarized in Table 4.1 for all technology corners. These simulation results show that the proposed circuit is robust, as process variation has no significant impact on its performance. The circuit consumes 110 nW and

53 TABLE 4.1 – Summary of performance of the proposed circuit against technology corners. TTSSSFFSFF VDD 0.6 V 0.7 V 0.7 V 0.6 V 0.5 V BW (KHz) 10 10 10 10 10 OSR 50 50 50 50 50 SNDR (dB) 55.2 49.79 45.5 43.3 47.39 ENOB (bits) 8.88 7.98 7.27 6.90 7.58 Power 110 nW 127 nW 132 nW 105 nW 91 nW FOM (fj/conv.) 11 25 42 44 23

provides 8.88 bits for a 105 mV input sine wave at 2 kHz. Moreover, since the maximum input value is 105 mV, there is no need for a high-gain amplifier prior to the ADC. However, considering the very low amplitude of the neural signals [3], an LNA with a gain of at least 40 dB must be used prior to the proposed ADC. Then, a figure of merit (FOM) [70], is used to compare the performance of the proposed circuit with other works : Power FOM = (4.5) 2 × BW × (2ENOB) Table 4.2 summarizes the performance of the proposed circuit and provides a comparison with pre- vious research. It shows that the proposed circuit has the best FOM among other analog-to-digital converters dedicated to similar applications.

4.4 Conclusion

In this chapter, a new low-power in-channel sigma-delta converter was presented. The proposed design occupies 82 µm × 84 µm and consumes only 110 nW for a bandwidth of 10 KHz; moreover, provides 8.88 bits of precision by leveraging a new feed-forward topology, while adding a minimum number of additional components and switches. An FOM has been defined and calculated for several reported designs, and the proposed circuit shows the best performance among similar data converters. Corner simulations show that the proposed circuit is robust against process variation, which makes it suitable for implantation inside a multi-channel recording neural implant.

54 TABLE 4.2 – Performance summary and comparison with sate of the art

[71] [72] [61] [73]* This Work (meas.) (meas.) (meas.) (meas.) (Post layout) 2013 2013 2015 2013 2016 Technology (nm) 180 160 180 28 180 Topology DT-Σ∆ DT-Σ∆ CT-Σ∆ CT-Σ∆ DT-Σ∆ BW (KHz) 5 0.013 4 18000 10 SNDR (dB) 105 119.8 75.9 73.6 55.2 ENOB (bits) 17.15 19.6 12.3 11.9 8.88 OSR – – – 18 50 Power (µW) 280 6.3 34.8 3900 0.11 FOM (fJ/conv.) 190 310 850 27.7 11

*Reference [73] has the best reported FOM for a sigma-delta converter, but is intended for a bandwidth of 18 Mhz.

55 Conclusion

The principal subject of this thesis was to design ultra-low power, ultra-low noise front-end for a multimodal implantable neural interface. A functional multimodal neural interface must be fully im- plantable and provide several hundred recording sites, while presenting ultra-low power and capturing different types of action potentials. This Ph.D. research comprises several ideas for designing low- power and high-precision front-ends.

The first chapter presented an overview of the application and motivation of the project as well as a literature review on the existing systems and methods for designing low-power, low-noise, and high- precision front-ends.

In the second chapter, we presented the mathematical noise performance calculations as well as pro- posed a new current reuse front-end, which contributes less noise and consumes less power in compa- rison to the conventional method. We presented the measurement results to show the performance of the circuit, and provided in-vivo experimental results as a proof of concept.

The third chapter introduced a new time domain multiplexing technique to be used mainly in sigma- delta ADCs for multichannel neural recording interfaces. Compared to the conventional multiplexing method, the proposed architecture improves the precision and crosstalk through a new time-interleaved oversampling scheme. Simulation and measurement results were presented to show the advantages of the proposed method. Moreover, in-vitro results were provided as a proof of concept for neural recording applications.

In the fourth chapter, we presented an ultra-low power sigma-delta ADC to be used inside an in- channel neural recording interface. The proposed idea benefits from a switched-capacitors integrator and a dynamic comparator, which works in the sub-threshold region to minimize the power consump- tion. The presented sigma-delta converter has the least FOM among most sigma-delta converters. Simulation results were provided as the proof of concept.

Future Works

In the second chapter of this thesis, a new current reuse ultra-low noise amplifier has been introduced, which can be implemented in high-density neural-recording applications. It is also possible to use this

56 ultra-low noise amplifier in applications where a poor signal needs to be recorded, like retinography.

The third chapter presented a multiplexed ADC that can be used as the digitizer in a high-density neural recording system. This circuit might be combined with the proposed front-end from the second chapter as well.

The last chapter presented an ADC that is suitable for in-channel implementation and consumes 110 nW per ADC. Combining this ADC with the designed LNA will provide an ultra-low power front-end that is suitable for ultra-high density neural recording applications or even retinography.

57 Publication List

Patent Applications

M. Rezaei and B. Gosselin, “A high-precision sigma-delta analog front-end” to be patented under invention disclosure number 01738-DIV

Journals

M. Rezaei, E. Maghsoudloo, M. Sawan, B. Gosselin," A TDM-Σ∆ Converter with Time-Interleaved Oversampling for High-Density Neural Implants" IEEE Transactions on Sensors (submitted)

M. Rezaei, E. Maghsoudloo, C. Bories, Y. De Koninck, B. Gosselin," A Low-Power Current-Reuse Analog Front-End" IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 2, pp. 271- 280, April 2018.

E. Maghsoudloo, M. Rezaei, M. Sawan, B. Gosselin,"A High-Speed and Ultra Low-Power Subthre- shold Signal Level Shifter" IEEE Transactions on Circuits and Systems I, vol. 64, no. 5, pp. 1164- 1172, 2016.

Conferences

M. Rezaei, E. Maghsoudloo, C. Bories, Y. De Koninck and B. Gosselin “A Fully Implantable Multi- chip Neural Interface with a New Scalable Current-Reuse Front-End” IEEE New Circuits and Systems Conference (NEWCAS), pp. 365-368, 2017.

E. Maghsoudloo, M. Rezaei, B. Gosselin, "A Wirelessly Powered High-Speed Transceiver for High- Density Bidirectional Neural Interfaces", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, 2017.

T. Elfaramawy, M. Rezaei, M. Morissette, B. Gosselin "Ultra-Low Distortion Linearized Pseudo-RC Low-Pass Filter" IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 221-224, 2016.

58 M. Rezaei and B. Gosselin,“Low-Power High-Speed Wireless Transceivers and Antennas for Large- Scale Neural Implants” IEEE New Circuits and Systems Conference (NEWCAS), pp. 1-4, 2016.

M. Rezaei, E. Maghsoudloo, M. Sawan and B. Gosselin, "A 110-nW in-channel sigma-delta converter for large- scale neural recording implants," IEEE International Conference on Engineering in Medi- cine and Biology Society (EMBC), pp. 5741-5744, 2016.

M. Rezaei, H. Bahrami, A. Mirbozorgi, L. A. Rusch and B. Gosselin, "A short-impulse UWB BPSK transmitter for large-scale neural recording implants," IEEE International Conference on Engineering in Medicine and Biology Society (EMBC), pp. 6315-6318, 2016.

E. Maghsoudloo, M. Rezaei, M. Sawan and B. Gosselin, "A new charge balancing scheme for electri- cal microstimulators based on modulated anodic stimulation pulse width," IEEE International Sym- posium on Circuits and Systems (ISCAS), pp. 2443-2446, 2016.

E. Maghsoudloo, M. Rezaei, M. Sawan and B. Gosselin, "A power-efficient wide-range signal level- shifter," IEEE New Circuits and Systems Conference (NEWCAS), pp. 1-4, 2015.

M. Rezaei, E. Maghsoudloo, M. Sawan and B. Gosselin, "A novel multichannel analog-to-time conver- ter based on a multiplexed sigma delta converter," IEEE New Circuits and Systems Conference (NEW- CAS), pp. 1-4, 2015.

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