DOCSLIB.ORG

Inline Assembly

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Inline Assembly Inline Assembly Florob Why? Assembler Inline Assembly Design Goals Prior Art D MSVC Florian “Florob” Zeitz gcc LLVM IR Rust (now) Rust’s Future? 2017-06-07 Questions 1 / 48 Inline Assembly Florob 1 Why? Why? Assembler 2 Assembler Design Goals Prior Art 3 Design Goals D MSVC gcc LLVM IR 4 Prior Art Rust (now) Rust’s Future? Questions 5 Rust (now) 6 Rust’s Future? 2 / 48 Inline Assembly Florob 1 Why? Why? Assembler 2 Assembler Design Goals Prior Art 3 Design Goals D MSVC gcc LLVM IR 4 Prior Art Rust (now) Rust’s Future? Questions 5 Rust (now) 6 Rust’s Future? 3 / 48 Why? Inline Assembly Florob Why? Assembler Design Goals Prior Art D MSVC gcc LLVM IR Rust (now) Rust’s Future? Questions 4 / 48 Why? Inline Assembly Florob low-level control config registers Why? hardware not otherwise accessible Assembler Design Goals performance Prior Art predictable timing D MSVC embedded gcc LLVM IR cryptography (side-channel) Rust (now) convenience Rust’s Future? no separate assembly file Questions no need for a build.rs Rust philosophy: safe with unsafe {} escape hatches where needed 5 / 48 Inline Assembly Florob 1 Why? Why? Assembler 2 Assembler Design Goals Prior Art 3 Design Goals D MSVC gcc LLVM IR 4 Prior Art Rust (now) Rust’s Future? Questions 5 Rust (now) 6 Rust’s Future? 6 / 48 Examples Inline Assembly Florob x86 (AT&T) x86 (Intel) Why? 1 jmp foo 1 jmp foo Assembler 2 mov $5, %eax 2 mov eax, 5 Design Goals 3 foo: 3 foo: Prior Art D 4 mov 5(%eax, %ebx, 2), %edx 4 mov edx, [eax + ebx*2 + 5] MSVC gcc LLVM IR Rust (now) ARM PowerPC Rust’s Future? Questions 1 ldmiaeq sp!, {r4-r7, pc} 1 lwz r0, 8(r1) 2 ldrb r0, [sp, #32] 2 rlwimi r11, r1, 0, 30, 28 7 / 48 Properties Inline Assembly Florob Why? textual representation of the instructions a CPU executes Assembler Design Goals mnemonics Prior Art operands D MSVC register gcc LLVM IR immediate Rust (now) label Rust’s Future? combinations thereof Questions 8 / 48 Inline Assembly Florob 1 Why? Why? Assembler 2 Assembler Design Goals Prior Art 3 Design Goals D MSVC gcc LLVM IR 4 Prior Art Rust (now) Rust’s Future? Questions 5 Rust (now) 6 Rust’s Future? 9 / 48 Design Goals Inline Assembly Florob Why? Assembler easy to use Design Goals portable Prior Art D between platforms (x86, AMD64, ARM, AVR, PowerPC, RISC-V, …) MSVC gcc between backends (LLVM, Cretone, gcc, …) LLVM IR Rust (now) support all instructions? (with all operand types?) Rust’s Future? Questions 10 / 48 Inline Assembly Florob 1 Why? Why? Assembler 2 Assembler Design Goals Prior Art 3 Design Goals D MSVC gcc LLVM IR 4 Prior Art Rust (now) Rust’s Future? Questions 5 Rust (now) 6 Rust’s Future? 11 / 48 D Inline Assembly Florob Why? 1 asm { mov RAX, RDX; } Assembler Design Goals implemented as DSL inside asm {} Prior Art D standardized per CPU family MSVC gcc can be marked pure and nothrow LLVM IR Rust (now) only x86/AMD64 are currently available Rust’s Future? Docs: https://dlang.org/spec/iasm.html Questions 12 / 48 D’s x86/AMD64 syntax Inline Assembly Florob close to regular Intel syntax Why? registers, always uppercase Assembler mnemonics, always lowercase Design Goals local variables accessed as var[EBP] Prior Art D (just var when not in naked code) MSVC gcc many D expressions allowed LLVM IR Rust (now) $ represents the PC, but can’t be used for PIC Rust’s Future? pseudo-ops for: Questions alignment data definition prefixes (lock, rep, …) 13 / 48 D Examples: Add 5 to variable Inline Assembly Florob Why? Assembler Design Goals 1 int var = 0; Prior Art 2 asm { D 3 add var, 3 + 2; MSVC gcc 4 } LLVM IR Rust (now) Rust’s Future? Questions 14 / 48 D Examples: Get L1 cache size Inline Assembly Florob 1 int ebx, ecx; Why? 2 asm { Assembler 3 mov EAX, 4; Design Goals 4 xor ECX, ECX; Prior Art 5 cpuid; D MSVC 6 mov ebx, EBX; gcc 7 LLVM IR mov ecx, ECX; 8 Rust (now) } 9 Rust’s Future? writefln("L1 Cache: %s", 10 ebx ebx Questions (( >> 22) + 1) * ((( >> 12) & 0x3ff) + 1) 11 * ((ebx & 0xfff) + 1) * (ecx + 1)); 15 / 48 MSVC Inline Assembly 1 __asm { mov rax, rdx } Florob Why? DSL after __asm Assembler only available for x86 (Pentium 4 and AMD Athlon opcodes) Design Goals Prior Art uses MASM (Microsoft Macro Assembler) expressions and C/C++ D MSVC elements gcc LLVM IR allows jumps to C labels from ASM and vice versa Rust (now) allows calls to C functions Rust’s Future? Questions C/C++ operators cannot be used Docs: https://docs.microsoft.com/en-us/cpp/assembler/ inline/inline-assembler 16 / 48 MSVC, supported MASM Inline Assembly Florob Why? Assembler not supported: Design Goals data definitions Prior Art macros D MSVC supported: gcc LLVM IR alignment Rust (now) comments Rust’s Future? Questions 17 / 48 MSVC, supported C/C++ elements Inline Assembly Florob Why? symbols (labels, function names, variable names) Assembler MASM reserved words take precedence over symbols Design Goals Prior Art constants D MSVC comments gcc LLVM IR macros and preprocessor directives Rust (now) Rust’s Future? type names where a MASM type would be legal Questions 18 / 48 MSVC Examples: Add 5 to variable Inline Assembly Florob Why? Assembler Design Goals 1 int var = 0; Prior Art 2 __asm { D 3 add var, 5 MSVC gcc 4 } LLVM IR Rust (now) Rust’s Future? Questions 19 / 48 MSVC Examples: Get L1 cache size Inline Assembly Florob 1 int ebx_v, ecx_v; 2 Why? __asm { 3 mov eax, 4 Assembler 4 xor ecx, ecx Design Goals 5 cpuid Prior Art D 6 mov ebx_v, ebx MSVC gcc 7 mov ecx_v, ecx LLVM IR 8 } Rust (now) 9 std::cout << "L1 Cache: " Rust’s Future? 10 << ((ebx_v >> 22) + 1) * (((ebx_v >> 12) & 0x3ff) + 1) Questions 11 * ((ebx_v & 0xfff) + 1) * (ecx_v + 1)) 12 << '\n'; 20 / 48 gcc Inline Assembly Florob 1 asm [volatile] ("template" : outs : ins : clobber) Why? Assembler special syntax within asm () Design Goals uses a template strings Prior Art D MSVC template interpreted by the assembler (compiler doesn’t have to gcc LLVM IR know instructions) Rust (now) compiler fills template based on constraints Rust’s Future? Docs: Questions https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html 21 / 48 gcc Template Inline Assembly Florob Why? Assembler %0, or %[name] as placeholders Design Goals supports modifiers, e.g. %w0 to print a HImode register name (%ax) Prior Art D multiple dialects as {mov %%eax, %%ebx | mov ebx, eax} MSVC gcc specify one or all aviailable dialects LLVM IR purely defined by order Rust (now) escapes: %%, %{, %}, %| Rust’s Future? Questions 22 / 48 gcc Arguments Inline Assembly Florob Why? specify outputs, inputs, and clobbers Assembler constraints determine how to reference arguments (register, Design Goals address, immediate) Prior Art D all inputs have to read before any output is written MSVC gcc clobbers specify touched state, that can not be inferred from inputs LLVM IR Rust (now) and outputs Rust’s Future? compiler moves arguments into registers, saves clobbered registers, Questions knows to reload changed memory 23 / 48 gcc Constraints Inline Assembly Florob Why? Assembler constraint codes are usually a single letter Design Goals architecture specific Prior Art D MSVC e. g. r for register, m for memory, i for immediate gcc LLVM IR multiple alternative constraints are allowed, allowing the compiler to Rust (now) choose the most efficient Rust’s Future? Questions 24 / 48 gcc Constraints Inline Assembly Florob output Why? start with = or + (input and output) Assembler can be modified with & to allow write before all inputs are read Design Goals (early-clobber) Prior Art input D MSVC can be tied to outputs by specifying the operand number as gcc LLVM IR constrained Rust (now) clobbers Rust’s Future? used registers Questions modified flags if memory was modified 25 / 48 gcc volatile Inline Assembly Florob Why? Assembler asm statements can be declared volatile Design Goals Prior Art disables code motion and dead code elimination D MSVC may be required when side-effects are not otherwise visible, gcc LLVM IR e. g. asm ("wfi"); Rust (now) Rust’s Future? Questions 26 / 48 gcc Examples: Add 5 to variable Inline Assembly Florob Why? Assembler Design Goals 1 int var = 0; Prior Art 2 asm ("add $5, %0" : "+r"(var)); D MSVC 3 asm ("add $5, %0" : "=r"(var) : "0"(var)); gcc LLVM IR Rust (now) Rust’s Future? Questions 27 / 48 gcc Examples: Get L1 cache size Inline Assembly 1 int ebx, ecx; Florob 2 asm ( Why? 3 "mov $4, %%eax;" Assembler 4 "xor %%ecx, %%ecx;" Design Goals 5 "cpuid;" Prior Art 6 "mov %%ebx, %0;" D 7 : "=r"(ebx), "=c"(ecx) MSVC gcc 8 : LLVM IR 9 : "eax", "ebx", "edx" Rust (now) 10 ); Rust’s Future? 11 printf("L1 Cache: %i\n", ((ebx >> 22) + 1) Questions 12 * (((ebx >> 12) & 0x3ff) + 1) 13 * ((ebx & 0xfff) + 1) 14 * (ecx + 1)); 28 / 48 No, in and out could be in the same register. gcc Examples: Increment Inline Assembly Florob Why? 1 int in = 3, out; Assembler 2 asm ( Design Goals 3 "mov $1, %0\r\n" Prior Art 4 "add %1, %0\r\n" D MSVC 5 : "=r"(out) gcc LLVM IR 6 : "r"(in) Rust (now) 7 ); Rust’s Future? Is this correct? Questions 29 / 48 gcc Examples: Increment Inline Assembly Florob Why? 1 int in = 3, out; Assembler 2 asm ( Design Goals 3 "mov $1, %0\r\n" Prior Art 4 "add %1, %0\r\n" D MSVC 5 : "=r"(out) gcc LLVM IR 6 : "r"(in) Rust (now) 7 ); Rust’s Future? Is this correct? No, in and out could be in the same register.
Load more

Recommended publications
  • AMD Athlon™ Processor X86 Code Optimization Guide
    AMD AthlonTM Processor x86 Code Optimization Guide © 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of AMD’s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, AMD Athlon, K6, 3DNow!, and combinations thereof, AMD-751, K86, and Super7 are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
    [Show full text]
  • Lecture Notes in Assembly Language
    Lecture Notes in Assembly Language Short introduction to low-level programming Piotr Fulmański Łódź, 12 czerwca 2015 Spis treści Spis treści iii 1 Before we begin1 1.1 Simple assembler.................................... 1 1.1.1 Excercise 1 ................................... 2 1.1.2 Excercise 2 ................................... 3 1.1.3 Excercise 3 ................................... 3 1.1.4 Excercise 4 ................................... 5 1.1.5 Excercise 5 ................................... 6 1.2 Improvements, part I: addressing........................... 8 1.2.1 Excercise 6 ................................... 11 1.3 Improvements, part II: indirect addressing...................... 11 1.4 Improvements, part III: labels............................. 18 1.4.1 Excercise 7: find substring in a string .................... 19 1.4.2 Excercise 8: improved polynomial....................... 21 1.5 Improvements, part IV: flag register ......................... 23 1.6 Improvements, part V: the stack ........................... 24 1.6.1 Excercise 12................................... 26 1.7 Improvements, part VI – function stack frame.................... 29 1.8 Finall excercises..................................... 34 1.8.1 Excercise 13................................... 34 1.8.2 Excercise 14................................... 34 1.8.3 Excercise 15................................... 34 1.8.4 Excercise 16................................... 34 iii iv SPIS TREŚCI 1.8.5 Excercise 17................................... 34 2 First program 37 2.1 Compiling,
    [Show full text]
  • Targeting Embedded Powerpc
    Freescale Semiconductor, Inc. EPPC.book Page 1 Monday, March 28, 2005 9:22 AM CodeWarrior™ Development Studio PowerPC™ ISA Communications Processors Edition Targeting Manual Revised: 28 March 2005 For More Information: www.freescale.com Freescale Semiconductor, Inc. EPPC.book Page 2 Monday, March 28, 2005 9:22 AM Metrowerks, the Metrowerks logo, and CodeWarrior are trademarks or registered trademarks of Metrowerks Corpora- tion in the United States and/or other countries. All other trade names and trademarks are the property of their respective owners. Copyright © 2005 by Metrowerks, a Freescale Semiconductor company. All rights reserved. No portion of this document may be reproduced or transmitted in any form or by any means, electronic or me- chanical, without prior written permission from Metrowerks. Use of this document and related materials are governed by the license agreement that accompanied the product to which this manual pertains. This document may be printed for non-commercial personal use only in accordance with the aforementioned license agreement. If you do not have a copy of the license agreement, contact your Metrowerks representative or call 1-800-377- 5416 (if outside the U.S., call +1-512-996-5300). Metrowerks reserves the right to make changes to any product described or referred to in this document without further notice. Metrowerks makes no warranty, representation or guarantee regarding the merchantability or fitness of its prod- ucts for any particular purpose, nor does Metrowerks assume any liability arising
    [Show full text]
  • Codewarrior® Targeting Embedded Powerpc
    CodeWarrior® Targeting Embedded PowerPC Because of last-minute changes to CodeWarrior, some of the information in this manual may be inaccurate. Please read the Release Notes on the CodeWarrior CD for the most recent information. Revised: 991129-CIB Metrowerks CodeWarrior copyright ©1993–1999 by Metrowerks Inc. and its licensors. All rights reserved. Documentation stored on the compact disk(s) may be printed by licensee for personal use. Except for the foregoing, no part of this documentation may be reproduced or trans- mitted in any form by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from Metrowerks Inc. Metrowerks, the Metrowerks logo, CodeWarrior, and Software at Work are registered trademarks of Metrowerks Inc. PowerPlant and PowerPlant Constructor are trademarks of Metrowerks Inc. All other trademarks and registered trademarks are the property of their respective owners. ALL SOFTWARE AND DOCUMENTATION ON THE COMPACT DISK(S) ARE SUBJECT TO THE LICENSE AGREEMENT IN THE CD BOOKLET. How to Contact Metrowerks: U.S.A. and international Metrowerks Corporation 9801 Metric Blvd., Suite 100 Austin, TX 78758 U.S.A. Canada Metrowerks Inc. 1500 du College, Suite 300 Ville St-Laurent, QC Canada H4L 5G6 Ordering Voice: (800) 377–5416 Fax: (512) 873–4901 World Wide Web http://www.metrowerks.com Registration information [email protected] Technical support [email protected] Sales, marketing, & licensing [email protected] CompuServe Goto: Metrowerks Table of Contents 1 Introduction 11 Read the Release Notes! . 11 Solaris: Host-Specific Information. 12 About This Book . 12 Where to Go from Here .
    [Show full text]
  • System Calls and Inline Assembler
    System calls and inline assembler Michal Sojka [email protected] ČVUT, FEL License: CC-BY-SA System calls ● A way for “normal” applications to invoke operating system (OS) kernel's services. ● Applications run in unprivileged CPU mode (user space, user mode) ● OS kernel runs in privileged CPU mode (kernel mode) ● System call is a way how to securely switch from user to kernel mode. What is a system call technically? ● A machine instruction that: – Increases the CPU privilege level and – Passes the control to a predefined place in the kernel. ● Arguments are (typically) passed in CPU registers. ● Instructions: – x86: int 0x80, sysenter, syscall – MIPS: syscall – ARM: swi x86 user execution environment (32 bit) Basic Program Execution Registers Address Space* 2^32 -1 Eight 32-bit General-Purpose Registers Registers General-Purpose Registers 31 16 15 8 07 16-bit 32-bit AH AL AX EAX Six 16-bit Segment Registers Registers BH BL BX EBX General-Purpose Registers 32-bits EFLAGS Register CH CL 031 CX ECX DH DL DX 32-bits EIP (Instruction Pointer Register) EAX EDX BP EBX EBP FPU Registers SI ECX ESI EDX Eight 80-bit Floating-Point DI EDI ESI Registers Data Registers 0 SP EDI ESP *The address space can be flat or segmented. Using EBP 16 bits Control Register the physical address ESP 16 bits Status Register extension mechanism, a physical address space of 16 bits Tag Register 2^36 - 1 canbeaddressed. Segment Registers Opcode Register (11-bits) 15 0 48 bits FPU Instruction Pointer Register CS 48 bits FPU Data (Operand) Pointer Register DS SS MMX
    [Show full text]
  • GCC and Assembly Language GCC and Assembly Language
    slide 2 slide 1 gaius gaius GCC and Assembly language GCC and Assembly language one could use an assembly language source file during the construction of an operating system kernel, define manyfunctions which: get, set registers microkernel, or embedded system it is vital to be able to access some of the microprocessor attribute unavailable in a high levellanguage this is inefficient, as it requires a call, ret to set a register cause cache misses and introduce a 3 instruction for example the operating system might need to: overhead modify a processes, stack pointer (%rsp) turn interrupts on and off manipulate the virtual memory directory processor register slide 3 slide 4 gaius gaius Consider an example (dangeous) foo.S suppose we wanted to get and set the value of the .globl foo_setsp stack pointer: rsp #void setsp (void *p) # #move the parameter, p, into $rsp # we might initially start to write an assembly file: foo_setsp: pushq %rbp foo.S which sets and gets the stack pointer movq %rsp, %rbp movq %rdi, %rsp leave ret # #void *getsp (void) # foo_getsp: movq %rsp, %rax ret slide 5 slide 6 gaius gaius Nowwrite some C code: bar.c Compile and link the code extern void foo_setsp (void *p); $ as -o foo.o foo.S $ gcc -c bar.c void someFunc (void) $ gcc foo.o bar.o { void *old = foo_getsp(); foo_setsp((void *)0x1234); } what are the problems with this code? hint examine what happens to the stack pointer slide 7 slide 8 gaius gaius Problems Writing the example the correct way the stack pointer is modified during the call and abetter technique is
    [Show full text]
  • In Using the GNU Compiler Collection (GCC)
    Using the GNU Compiler Collection For gcc version 6.1.0 (GCC) Richard M. Stallman and the GCC Developer Community Published by: GNU Press Website: http://www.gnupress.org a division of the General: [email protected] Free Software Foundation Orders: [email protected] 51 Franklin Street, Fifth Floor Tel 617-542-5942 Boston, MA 02110-1301 USA Fax 617-542-2652 Last printed October 2003 for GCC 3.3.1. Printed copies are available for $45 each. Copyright c 1988-2016 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with the Invariant Sections being \Funding Free Software", the Front-Cover Texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled \GNU Free Documentation License". (a) The FSF's Front-Cover Text is: A GNU Manual (b) The FSF's Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. i Short Contents Introduction ::::::::::::::::::::::::::::::::::::::::::::: 1 1 Programming Languages Supported by GCC ::::::::::::::: 3 2 Language Standards Supported by GCC :::::::::::::::::: 5 3 GCC Command Options ::::::::::::::::::::::::::::::: 9 4 C Implementation-Defined Behavior :::::::::::::::::::: 373 5 C++ Implementation-Defined Behavior ::::::::::::::::: 381 6 Extensions to
    [Show full text]
  • PA Build RM.Pdf
    CodeWarrior Development Studio for Power Architecture® Processors Build Tools Reference Revised: 2 March 2012 Freescale, the Freescale logo and CodeWarrior are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their re- spective owners. © 2005-2012 Freescale Semiconductor, Inc. All rights reserved. Information in this document is provided solely to enable system and software implementers to use Freescale Semicon- ductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any inte- grated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any partic- ular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam- ages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including
    [Show full text]
  • ARM Cortex-A Series Programmer's Guide
    ARM® Cortex™-A Series Version: 4.0 Programmer’s Guide Copyright © 2011 – 2013 ARM. All rights reserved. ARM DEN0013D (ID012214) ARM Cortex-A Series Programmer’s Guide Copyright © 2011 – 2013 ARM. All rights reserved. Release Information The following changes have been made to this book. Change history Date Issue Confidentiality Change 25 March 2011 A Non-Confidential First release 10 August 2011 B Non-Confidential Second release. Updated to include Virtualization, Cortex-A15 processor, and LPAE. Corrected and revised throughout 25 June 2012 C Non-Confidential Updated to include Cortex-A7 processor, and big.LITTLE. Index added. Corrected and revised throughout. 22 January 2014 D Non-Confidential Updated to include Cortex-A12 processor, Cache Coherent Interconnect, expanded GIC coverage, Multi-core processors, Corrected and revised throughout. Proprietary Notice This Cortex-A Series Programmer’s Guide is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this Cortex-A Series Programmer’s Guide may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this Cortex-A Series Programmer’s Guide. Your access to the information in this Cortex-A Series Programmer’s Guide is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the information herein infringe any third party patents. This Cortex-A Series Programmer’s Guide is provided “as is”.
    [Show full text]
  • Learn Linux Kernel Programming, Hands-On: a Uniquely Effective Top-Down Approach
    The Linux® Kernel Primer: A Top-Down Approach for x86 and PowerPC Architectures By Claudia Salzberg Rodriguez, Gordon Fischer, Steven Smolski ............................................... Publisher: Prentice Hall PTR Pub Date: September 21, 2005 ISBN: 0-13-118163-7 Pages: 648 Table of Contents | Index Learn Linux kernel programming, hands-on: a uniquely effective top-down approach The Linux® Kernel Primer is the definitive guide to Linux kernel programming. The authors' unique top-down approach makes kernel programming easier to understand by systematically tracing functionality from user space into the kernel and carefully associating kernel internals with user-level programming fundamentals. Their approach helps you build on what you already know about Linux, gaining a deep understanding of how the kernel works and how its elements fit together. One step at a time, the authors introduce all the tools and assembly language programming techniques required to understand kernel code and control its behavior. They compare x86 and PowerPC implementations side-by-side, illuminating cryptic functionality through carefully- annotated source code examples and realistic projects. The Linux® Kernel Primer is the first book to offer in-depth coverage of the rapidly growing PowerPC Linux development platform, and the only book to thoroughly discuss kernel configuration with the Linux build system. Coverage includes Data structures x86 and PPC assembly language Viewing kernel internals Linux process model User and kernel space Interrupts and exceptions Memory allocation and tracking Tracing subsystem behavior I/O interactions Filesystems and file operations Scheduling and synchronization Kernel boot process Kernel build system Configuration options Device drivers And more... If you know C, this book teaches you all the skills and techniques you need to succeed with Linux kernel programming.
    [Show full text]
  • The Shellcoder 039 S Handbook Discovering And
    80238ffirs.qxd:WileyRed 7/11/07 7:22 AM Page iii The Shellcoder’s Handbook Discovering and Exploiting Security Holes Second Edition Chris Anley John Heasman Felix “FX” Linder Gerardo Richarte The Shellcoder’s Handbook: Discovering and Exploiting Security Holes (1st Edition) was written by Jack Koziol, David Litchfield, Dave Aitel, Chris Anley, Sinan Eren, Neel Mehta, and Riley Hassell. Wiley Publishing, Inc. 80238ffirs.qxd:WileyRed 7/11/07 7:22 AM Page ii 80238ffirs.qxd:WileyRed 7/11/07 7:22 AM Page i The Shellcoder’s Handbook Second Edition 80238ffirs.qxd:WileyRed 7/11/07 7:22 AM Page ii 80238ffirs.qxd:WileyRed 7/11/07 7:22 AM Page iii The Shellcoder’s Handbook Discovering and Exploiting Security Holes Second Edition Chris Anley John Heasman Felix “FX” Linder Gerardo Richarte The Shellcoder’s Handbook: Discovering and Exploiting Security Holes (1st Edition) was written by Jack Koziol, David Litchfield, Dave Aitel, Chris Anley, Sinan Eren, Neel Mehta, and Riley Hassell. Wiley Publishing, Inc. 80238ffirs.qxd:WileyRed 7/11/07 7:22 AM Page iv The Shellcoder’s Handbook, Second Edition: Discovering and Exploiting Security Holes Published by Wiley Publishing, Inc. 10475 Crosspoint Boulevard Indianapolis, IN 46256 www.wiley.com Copyright © 2007 by Chris Anley, John Heasman, Felix “FX” Linder, and Gerardo Richarte Published by Wiley Publishing, Inc., Indianapolis, Indiana Published simultaneously in Canada ISBN: 978-0-470-08023-8 Manufactured in the United States of America 10 9 8 7 6 5 4 3 2 1 No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 646-8600.
    [Show full text]
  • CCES 2.9.0 C/C++ Compiler Manual for SHARC Processors
    CCES 2.9.0 C/C++ Compiler Manual for SHARC Processors (Includes SHARC+ and ARM Processors) Revision 2.2, May 2019 Part Number 82-100117-01 Analog Devices, Inc. One Technology Way Norwood, MA 02062-9106 Copyright Information ©2019 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Ana- log Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, Blackin+, CrossCore, EngineerZone, EZ-Board, EZ-KIT, EZ-KIT Lite, EZ-Ex- tender, SHARC, SHARC+, and VisualDSP++ are registered trademarks of Analog Devices, Inc. EZ-KIT Mini is a trademark of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CCES 2.9.0 C/C++ Compiler Manual for SHARC Processors ii Contents Preface Purpose of This Manual................................................................................................................................. 1±1 Intended Audience........................................................................................................................................
    [Show full text]