® MICRO COMPUTER SET mcs.4 :ii:f c-, :a

NOVEMBER 1971 g :ii: ""C C: -I m • Microprogrammable General · • 10.8 Microsecond Instruction :a en m Purpose Computer Set Cycle u£.C 1.'a ,�,, -I • 4-Bit Parallel CPU With 45 • Easy Expansion -One CPU can Instructions Directly Drive up to 32,768 • Instruction Set Includes Bits of ROM and up to 5120 Conditional Branching, Jump to Bits of RAM Subroutine and Indirect Fetching • Unlimited Number of Output • Binary and Decimal Arithmetic Lines Modes • Single Power Supply Operation • Addition of Two 8-Digit Numbers (Voo = -15 Volts) in 850 Microseconds • Packaged in 16-Pin Dual In-Line • 2 -Phase Dynamic Operation Configuration

The MCS-4 is a microprogrammable computer set designed for applications such as test systems, peripherals, terminals, billing machines, measuring systems, numeric and process control. The 4004 CPU, 4003 SR, and 4002 RAM are standard building blocks. The 4001 ROM contains the custom microprogram and is implemented using a metal mask accord­ ing to customer specifications. MCS-4 systems interface easily with switches, keyboards, displays, teletypewriters, 4001 J , I printers, readers, A-D converters and other popular peripherals. 1 A system built with the MCS-4 micro computer set can have up to 4K x 8 bit ROM words, 1280 x 4 bit RAM characters and 128 1/0 lines without requiring any interface logic. By AR. ITHMElJ..9-'P,f�. D?' adding a few simple gates the MCS-4 can have up to 48 RAM and ROM packages in any � A.N: L'f '{t, combination, and 192 1/0 lines. The minimum system configuration consists of one CPU 4004 l �\T�;ti I l , and one 256 x 8 bit ROM. 1q The MCS-4 has a very powerful instruction set that allows both binary and decimal arithmetic. It includes conditional branching, jump to subroutine, and provides for the 11 ,t!11·�""- efficient use of ROM look-up tables by indirect fetching. The Intel MCS-4 micro computer set (4001/2/3/4) is fabricated with Silicon Gate Tech­ nology. This low threshold technology allows the design and production of higher performance MOS circuits and provides a higher functional density on a monolithic chip than conventional MOS technologies.

Copyright Intel Corporation 1971. Contents may not be reproduced in whole or part without the written consent of Intel Corporation. ffl(S·4 Description 256 x 8 BIT MASK PROGRAMMABLE 4002 320 BIT RAM AND 4 BIT OUTPUT PORT 4001 ROM AND 4 BIT 1/0 PORT

® ¢ SYNC 0 TIMING 0 ¢, . I I � , J H J J i:. o, ONE OF FOUR REGISTERS D IN THE REGISTERRAM ARRAY O ,:,) o DATA ROM o, ADDRESS MEMORY CHARACTER O D © 1 BUS REGISTER ARRAY 03 � 16 X 16 X 8 D2 1/0 AND -...... - DECODER D3 i>- 0 MUX ,. @ Vooo-,;--..+- ,.;; GND INSTRUCTION � DECODER MEMORY CHA ACTER 15 I- CONTROL STATUS CHARACTER O CONTROL & }u Do STATUS CH�RACTER 3 I '---,--' � o, 4BITS 1- o, @) @!CM Po @) CL��'����� RESET The 4002 performs two func­ (!) PIN CONFIGURATION PIN CONFIGURATION tions. As a RAM it stores 320 16 bits arranged in 4 registers of

D D DATA 1 :;:!INPUT/ twenty 4-bit characters each (16 DATA 1 BUS OUTPUT BUS 1/0 D2 1/02 LINES main memory characters and 4 1/0 02

The 4001 is a 2048-bit metal o, 1/03 lo, status characters). As a vehicle !°'o, 1 mask programmable ROM pro­ 12 v00 -15V of communication with periph­ MEMORY CLOCK viding custom microprogram­ 1 } Oi 11 CM {CONTROL eral devices, it is provided with PHASE INPUT CLOCK CLEAR INPUT ming capability for the MCS-4 } lO CL { 4 output lines and associated PHASE 2 02 fOR l/0 LINES micro computer set. It is organ­ RESET control logic to perform output 1!��� }svNc ized as 256 x 8 bit words. operations. Address and data are transferred in and out by time In the RAM mode, the operation is as follows: When the CPU multiplexing on 4 data bus lines. Timing is internally generated executes an SRC instruction (see Instruction Set on page 5) it using two clock signals, ¢1 and ¢2 , and a SYNC signal supplied will send out the contents of the designated index register pair by the 4004. Addresses are received from the CPU on three during X2 and X3 as an address to the RAM, and will activate time periods following SYNC, and select 1 out of 256 words one CM-RAM line at X2 for the previously (Note 1) selected and 1 out of 16 ROM's. For that purpose, each ROM is RAM bank (see Basic Instruction Cycle on page 5). identified as #0, 1, 2, through 15, by metal option. A Command Line (CM) is also provided and its scope is to select The data at X2 and X 3 is interpreted as shown below: a ROM bank (group of 16 ROM's). X2 X3 During the two time periods (M1 & M2 ) following the D3 D2 D1 Do D3 D2 D1 Do addressing time, information is transferred from the ROM to Chip # Register # Main Memory Character # the data bus Iines. (0 through 3) (0 through 3) (0 through 15) A second mode of operation of the ROM is as an Input/Output The status character locations (0 through 3) are selected by control device. In that mode a ROM chip will route the OPA portion of one of the 1/0 and RAM Instructions. information to and from data bus lines in and out of 4 1/0 For chip selection, the 4002 is available in two metal options, external lines. Each chip has the capability to identify itself 4002-1 and 4002-2. An external pin, P0 (which may be hard for an 1/0 port operation, recognize an 1/0 port instruction wired to either VDD or V ss) is also available for chip selection. and decide whether it is an Input or an Output operation and The chip number is assigned as follows: execute the instruction. An external signal (CL) will asyn­ Chip # 4002 Option Po 03 D2 @ X2 chronously clear the output register during normal operation. 0 4002-1 GND O 0 All internal flip flops (including the output register) will be re­ 1 4002-1 vDD 0 1 set when the RESET line goes low (negative voltage). 2 4002-2 GND 0 3 4002-2 VDD Each 1/0 pin can be uniquely chosen as either an input or Timing is internally generated using two clock signals, ¢1 and output port by metal option. Direct or inverted input or ¢2 , and a sync signal provided by the 4004. Internal refresh output is optional. An on-chip resistor at the input pins, circuitry maintains data levels in the cells. connected to either VDD or Vss is also optional. (See ordering All communications with the system is through the data bus. information on page 12). The 1/0 port permits data out from the system. When the external RESET signal goes low, the memory and all static flip-flops (including the output registers) will be cleared. To fully clear the memory the RESET signal must be maintained for at least 32 memory cycles (32 x 8 clock periods).

2 fflC§.4 Description 10 BIT SERIAL-IN/PARALLEL-OUT, 4 BIT CENTRAL PROCESSOR UNIT 4003 4004 SERIAL-OUT SHIFT REGISTER (SR) (CPU) WITH 45 INSTRUCTIONS

Voo GND CM-ROM@ CM-RAMoe CM-RAM@ 1 CM-RAM14) 2 CM-RAM@ 3 ----...... @j j@-----, POWER SYNC CP � ON CLEAR INDEX GNO REG. @ ..J 16 X 4 0 a:: RAM lli INSTR. z... SERIAL 0 OATA IN {JI 10 BIT SHIFT REG. u PROGRAM OUT DEC. � COUNTER AND STACK4 X 12 RAM

ENABLE GATES Do D, ®0®®@'!) D2 @ ® 0, 00 a, 02 03 a4 o5 06 07 08 09 TEST RESET

PIN CONFIGURATION PIN CONFIGURATION

The 4003 is a 10 bit static shift 16 CM,RAMo '"'"�����}" The 4004 is a central processor DATA IN CM-RAM register with serial-in, parallel­ DATA!: 1 MEMORY unit (CPU) designed to work BUS ) CONTROL out and serial-out data. Its func­ -ISV 1/0 0i CM-RAM OUTPUTS PARALLEL .. 2 OUTPUTS { in conjunction with the other tion is to increase the number , CM-RAM3 o members of the MCS-4 (4001, 0, of output lines to interface with GND Vss GNO Vss v00 -15V , 4002, 4003) for microprogram­ MEMORY 1/0 devices such as keyboards, PARALLEL CLOCK}o OUTPUTS PHASE 1 , CM-ROM {CONTROL o mable computer applications. OUTPUT displays, printers, teletypewrit­ PARALLEL OUTPUTS O 3 p��gino2 TEST ers, switches, readers, A-D con­ {o, The CPU chip consists of a 4 bit ou\i�i} SYNC RESET verters, etc. adder, a 64 bit (16 x 4) index Data is loaded serially and is available in parallel on 10 output register, a 48 bit(4 x 12) program counter and stack(nesting lines which are accessed through enable logic. When enabled up to three levels if possible), an address incrementer, an 8 bit (E = low), the shift register contents is read out; when not instruction register and decoder, and control logic. Information flows between the 4004 and the other chips through a 4-line enabled(E = high), the parallel-out lines are at Vss . The serial­ out line is not affected by the enable logic. data bus. One 4004 may be combined with up to 48 ROM (4001) and RAM(4002) chips in any combination. Data is also available serially permitting an indefinite number of similar devices to be cascaded together to provide shift A typical machine cycle starts with the CPU sending a syn­ register length multiples of 10. chronization signal (SYNC) to the ROM's and RAM's. Next, 12 bits of ROM address are sent to the data bus using three The data shifting is controlled by the CP signal. An internal clock cycles(@ .75 MHz). The address is then incremented by power-on-clear circuit will clear the shift register(Q i = Vss ) one and stored in the program counter. The selected ROM between the application of the supply voltage and the first sends back 8 bits of instruction or data during the following 2 CP signal. clock cycles. This information is stored in two registers: OPR and OP A. The next three clock cycles are used to execute the instruction. (See Basic Instruction Cycle on page 5.) The ROM bank is controlled by a command ROM control signal (CM-ROM) and up to four RAM banks are controlled by four command RAM control signals (CM-RAM0 , CM­ RAM 1 , CM-RAM2, CM-RAM3 ). Bank switching is accom­ plished by the execution of the DCL instruction (see Note 1 this page). An input test signal (TEST) is used in conjunction with the jump on condition (JCN) instruction. An external RESET signal is used to clear all registers and flip-flops. To fully clear all registers, the RESET signal must be applied for at least 8 4002 320 BIT RAM AND 4 BIT OUTPUT PORT memory cycles(8 x 8 clock periods). After RESET the program NOTE 1: Bank switching is accomplished by the CPU after receiving will start from "O" step and CM-RAM0 will be selected. a "DCL" (designate command line) instruction. Prior to ex ­ The instruction repertoire of the 4004 consists of: ecution of the DCL instruction the desired CM-RAMi code has been stored in the accumulator (for example through an (a) 16 machine instructions(5 of which are double length). LDM instruction). During DCL the CM-RAMi code is trans­ (b) 14 accumulator group instructions. ferred from the accumulator to the CM-RAM register. The RAM bank is then selected starting with the next instruction. (c) 15 input/output & RAM instructions.

3 ffl(§.4 Operation

The detailed functional specifications describing the operation of the system, the instruction set, the activity of the CPU for each instruction and some programming and hardware examples are published separately and are available upon request. Following is a brief outline of the system operation.

The MCS-4 uses a 10.8 µsec instruction cycle. The CPU(4004) generates a synchronizing signal(SYNC), indicating the start of an instruction cycle, and sends it to the ROM's (4001) and RAM's (4002).

Basic instruction execution requires 8 or 16 cycles of a 750 KHz clock. In a typical sequence, the CPU sends 12 bits of address to the ROM's in the first three cycles(A 1 , A2, A3). The selected ROM chip sends back 8 bits of instruction(OPR, OPA) to the CPU in the next two cycles (M1 , M2 ). The instruction is then interpreted and executed in the final three cycles(X 1 , X2 , X3 ).(See Figure 2 .)

The CPU, RAM's and ROM's can be controlled by an external RESET line. While RESET is activated the contents of the registers and flip-flops are cleared. After RESET, the CPU will start from address O and CM-RAM0 is selected. The MCS-4 can have up to 4K x 8 bit ROM words, 1280 x 4 bit RAM characters and 128 1/0 lines, without requiring any interface logic. By adding a few simple gates, the MCS-4 can have up to 48 RAM and ROM packages in any combination and 192 1/0 lines.

The 4001, 4002, and 4004 are interconnected by a 4-line data bus(Do, 01, 02, 03), used for all information flow between the chips except for control signals sent by the CPU on 6 additional lines. The interconnection of the MCS-4 system is shown in Figure 1. An expanded configuration is shown. The minimum system configuration consists of one CPU(4004) and one ROM (4001). Figure 2 shows the activity on the data bus during each clock period, and how a basic instruction cycle is subdivided.

Each data bus output buffer has three possible states "1", "O", and floating. At a given time only one output buffer is allowed to drive a data line, therefore, all the other buffers must be in a floating condition. However, more than one input buffer per data line can receive data at the same time.

The MCS-4 has a very powerful Instruction Set that allows both binary and decimal arithmetic. It includes conditional branching, jump to subroutine and provides for the efficient use of ROM look up tables by indirect fetching. Typically, two 8 digit numbers can be added in 850 µsec. The complete Instruction Set is shown on pages 5 and 6.

Voo GND 1 2 4004 1 1 l l CM-ROM

SYNC RESET

SYNC RESET

SYNC RESET I I I I I I

4001 �15

CP

DATA IN DATA IN SERIAL SERIAL OUT OUT ENABLE ENABLE

a 0 0 1 o 9 Oo 01 09 010 011 019

Figure 1. MCS-4 System Interconnection

4 ffl(S·4 Operation

------INSTRUCTION CYCLE ------i

Address Sent to ROM From CPU --. E of lnstruction ----+-r t InstructionCPU From SentROM to ---+• + --• --- xecution I Data is Operated on in the CPU, Or ., 35µs � Data or Address is Sent to/from the CPU

SYNC

Memory x, Subcycles A1 A2 A3 M1 M2 X2 X3 If IOR1 "The The CPU The CPU The Selected 4001 Is Enabled Selected 4001 The CPU Is Enabled Is Enabled Is Enabled Device Or 4002 Are

ControllingData Bus wiseEnabled, The Other-CPU Output Is Enabled

Data or Address Data Middle 4-bit Higher 4-bit OPA Out to RAM's and Bus Address to RAM's If Lower 4·bit ROM's If f01 11 Address to Contents ROM's ROM's ROM's (Chip OPA to CPU SRCl21 Address to Address to OPR to CPU (Not Used) Or SRCl21 Select Code) and ROM's and RAM's Oata to CPU f0111 If IOR'" (1) IO instructions control the flow of information between accumulator in CPU, I/0 lines in IfROM's and RAM's and RAM storage. TOR stands for JO Read. In this case the CPU wilt receive data from RAM storage locations or UO input lines of 4001 's. (21 The SAC instruction designates the chip number and address for a following IO instruction,

Figure 2. MCS-4 Basic Instruction Cycle Instruction Set [Those instructions preceded by an asterisk (*) are 2 word instructions that occupy 2 successive locations in ROM] MACHINE INSTRUCTIONS

OPR OPA MNEMONIC D3 D2 D1 Do D3 D2 D1 Do DESCRIPTION OF OPERATION

NOP 0 0 0 0 0 0 0 0 No operation.

Jump to ROM address A2 A2 A2 A2, A 1 A 1 A 1 A 1 (within the same *JCN 0 0 0 1 c1 c2 c3 c4 (1 ROM that contains this JCN instruction) if condition C 1 C2 C3 C4 ) A 1 A 1 is true, otherwise skip (go to the next instruction in sequence}. A2 A2 A 2 A2 A 1 A 1 *FIM 0 0 1 0 A A A 0 Fetch immediate (direct) from ROM Data D2, D 1 to index register pair D (2) D2 D2 D2 2 o, o, o, o, location RR R. 0 0 0 A R Send the address (contents of index register pair RRR) to ROM and RAM SAC 1 A 1 at x2 and x3 time in the Instruction Cycle. Fetch indirect from ROM, Send contents of index register pair location 0 FIN 0 0 1 1 A R R 0 out as an address. Data fetched is placed into register pair location RRR at A 1 and A2 time in the Instruction Cycle. 0 0 1 A A 1 Jump indirect. Send contents of register pair RR A out as an address JIN 1 A at A 1 and A2 time in the Instruction Cycle. 0 1 0 0 A3 A3 A3 A3 *JUN Jump unconditional to ROM address A3, A2, A . A A 1 2 2 A2 A2 A 1 A 1 A 1 A 1

0 0 Jump to subroutine ROM address A3, A2, A 1 , save old address. (Up 1 level *JMS 1 1 A3 A3 A3 A3 in stack.) A2 A2 A2 A2 A 1 A 1 A 1 A 1 3 INC 0 1 1 0 A R A R Increment contents of register RRRR. ( ) Increment contents of register RRRR. Go to ROM address A , A 0 1 R A A 2 1 *ISZ 1 1 A (within the same ROM that contains this ISZ instruction) if result +o, otherwise skip (go to the next instruction in sequence . A2 A2 A2 A2 A1 A 1 A 1 A1 ) ADD 0 0 0 A R R R Add contents of register RRRR to accumulator with carry, 1 0 0 R R Subtract contents of register RRRR to accumulator with borrow. SUB 1 1 R R LO 0 1 R R R R Load contents of register ARAR to accumulator. 1 1 0 R R Exchange contents of index register RRRR and accumulator. XCH 1 1 1 R R BBL 1 0 0 D D D D Branch back (down 1 level in stack) and load data DODD to accumulator. 1 0 Load data DODD to accumulator. LDM 1 1 1 D D D D See Notes on Page 6. Continued on page 6.

5 Instruction Set

INPUT/OUTPUT AND RAM INSTR UCTIONS

(The RA M's and RO M's operated on in the I /0 and RAM instructions have been previously selected by the last SRC instruction executed.)

QPR OPA MNEMONIC Do DESC RIPTION OF OPERATION D3 D2 D1 o3 o2 01 Do Write the contents of the accumulator into the previously selected WRM 1 1 0 0 0 0 0 1 RAM main memory character. Write the contents of the accumulator into the previously selected 1 0 0 0 0 1 WMP 1 1 RAM output port. (Output Lines) Write the contents of the accumulator into the previously selected WRR 1 1 0 0 0 1 0 1 ROM output port. ( 1/0 Lines) Write the contents of the accumulator into the previously selected 0 0 0 0 WR (4) 1 1 1 1 RAM status character 0. Write the contents of the accumulator into the previously selected 1 (4) 1 1 1 0 WR 0 1 0 1 RAM status character 1. Write the contents of the accumulator into the previously selected 1 1 0 0 1 0 WR2(4) 1 1 RAM status character 2. Write the contents of the accumulator into the previously selected (4) WR3 1 1 1 0 0 1 1 1 RAM status character 3. Subtract the previously selected ma in memory character from SBM 1 1 1 0 1 0 0 0 accumu lator with borrow. RAM Read the previously selected RAM main memory character 1 1 1 0 ROM 1 0 0 1 into the accumulator. Read the contents of the previously selected ROM input port RDA 1 1 1 0 0 0 1 1 into the accumulator. ( I /0 Lines) Add the previously selected RAM main memory character to 1 ADM 1 1 1 0 1 0 1 accumulator with carry.

RD (4) 1 1 0 1 1 0 0 Read the previously selected status character O into accumulator. 1 RAM RD1(4l 1 1 1 0 1 1 0 1 Read the previously selected RAM status character 1 into accumulator.

RD2(4) 1 1 0 0 Read the previously selected RAM status character 2 into accumulator. 1 1 1 1 RD3(4) 1 1 0 1 1 1 1 Read the previously selected RAM status character 3 into accumulator. 1 ACCUM ULATOR GROUP INSTRUCTIONS

CLB 1 1 1 1 0 0 0 0 Clear both. ( Accumulator and carry)

CLC 1 1 1 1 0 0 0 1 Clear carry.

1 1 1 1 0 0 1 0 Increment accumulator. IAC CMC 1 1 1 1 0 0 1 Complement carry. 1 1 1 0 0 0 Complement accumulator. CMA 1 1 1 RAL 1 1 1 1 0 1 0 1 Rotate left. (Accumulator and carry)

1 0 0 Rotate right. (Accumulator and carry) RA R 1 1 1 1 1 TCC 1 1 1 1 0 1 1 1 Transmit carry to accumulator and clear carry.

1 1 0 0 0 Decrement accumulator. DAC 1 1 1 TCS 1 1 1 1 1 0 0 1 Transfer carry subtract and clear carry.

STC 1 1 1 0 0 Set carry. 1 1 1 DAA 1 1 1 1 1 0 1 1 Decimal adjust accumulator. Keyboard process. Converts the contents of the accumulator from a 1 1 0 0 KBP 1 1 1 1 one out of four code to a binary code. DCL 1 1 1 1 1 1 0 1 Designate command line. (See note 1 on page 3.)

NOTES: ( 1 )The condition code is assigned as follows: 1 c1 = 1 Invert jump condition � = Jump if accumulator is zero c4 = 1 Jump if test signal is a 0 c c 1 1 = 0 Not invert jump condition 3 = Jump if carry/link is a 1 ( 2) RRR is the address of 1 of 8 index register pairs in the CPU.

(3) RR RR is the address of 1 of 16 index registers in the CPU.

(4l Each RAM chip has 4 registers, each with twenty 4-bit characters subdivided into 1 6 main memory characters and 4 status characters. Chip number, RAM register and main memory character are addressed by an SRC instruction. For the selected chip and register, however, status character locations are se lected by the instruction code (OPA) .

6 Absolute Maximum Ratings*

0 0 Ambient Temperature Under Bias o c to +7o c *COMMENT ° 0 Storage Temperature -55 C to +15o c Stresses above those listed under "Absolute Maximum Ratings" I nput Voltages and Supply Voltage may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other With Respect to V +0.5 to -20V SS condition above those indicated in the operational sections of this Power Dissipation 1.0 W specification is not implied. D.C. and Operating Characteristics = 0 ° = TA o c to +70 C; v00 = -15V ±.5%, Vss = GND, tPW = tD l 400 nsec, t02 = 150 nsec, unless otherwise specified Logic "O" is defined as the more positive voltage (VI H • v0 H ), Logic "1" is defined as the more negative voltage (VI L• Voll

SUPPLY CURRENT Ll I � T PRODUCT SYMBOL PARAMETER 1 UNIT TEST CONDITIONS MIN. TVP. MAX. = ° 4001 1 001 AVERAGE SUPPLY CURRENT 15 30 mA TA 25 C T = 250C 4002 1 002 AVERAGE SUPPLY CURRENT 17 33 mA A = = 0 4003 1 003 AVERAGE SUPPLY CURRENT 5.0 8.5 mA twL = twH 8 µsec; TA 25 c T = 0 4004 1 004 AVERAGE SUPPLY CURRENT 30 40 mA A 25 c INPUT CHARACTERISTICS 4001 /2/3/4 I V = V L I INPUT LEAKAGE CURRENT 10 µA IL oo 4001 /2/3/4 VIH INPUT H I GH VO LTAGE -1 .5 +0.3 V (ALL I NPUTS EXCEPT CLOCKS) (2) 4001 /2/3/4 VI L INPUT LOW VOLTAGE Voo -5.5 V (ALL I NPUTS EXCEPT CLOCKS)

4001 /2/4 VILC CLOCK INPUT LOW VO LTAGE Voo -1 3.4 V 4001 /2/4 VIHC CLOCK INPUT HIGH VO LTAGE -1.5 +o.3 V I I 4001 R I 1/0 PINS NPUT RES STANCE 10 18 35 Kn Internal input resistor is optional OUTPUT CHARACTERISTICS

4001 /2/4 1 LO DATA BUS OUTPUT LEAKAGE 10 µA VoUT = -12V, Chip disabled CURRENT

4001 /2/3/4 VoH OUTPUT H I GH VOLTAGE 0 -0.5 V Driving 4000 Series loads only 4001 /2/4 1 DATA L I NES S I NKING 10 18 V ou m ouT = ov CURRENT "1 " LEVE L A

4001 /2 1 0L2 1 /0 OUTPUT L I NES S I NKING 2.5 5 mA VouT = ov CURRENT, "1" LEVEL = 4003 1 0L3 PARALLE L OUT PINS 0.6 1.0 mA VouT ov SINKING CURRENT, "1 " LEVEL

4003 10L4 SERIAL OUT S I NKING 1.0 2.0 mA VouT = OV CURRENT, "1" LEVEL = 4004 10L5 CM-ROM SINKI NG CURRENT 6.5 12 mA VouT ov "1 " LEVEL = 4004 10L6 CM-RAM L I NES S I NKI NG 2.5 4 mA VouT ov CURRENT "1" LEVEL = 4001 /2/4 Vou DATA LINES, CM LINES, -12 -10 -6.5 V 1 0u 500 µA SYNC OUTPUT LOW VO LTAGE

4001 /2 VOL2 1/0 OUTPUT L I NES -12 -7.5 -6.5 V 1 0L2 = 50 µA OUTPUT LOW VO LTAGE 4003 V OUTPUT LOW VO LTAGE -7.5 -6.5 V 1 = OL3 -1 1 0L3 10µA 4001 /2/4 ROH1 OUTPUT RESISTANCE 150 250 n VouT = -0.5V DATA LINES "O" LEVEL V = - .5 4001 /2 R OUTPUT RESIST NCE 1.2 1.8 Kn ouT o v oH2 1/0 LINES "O" LEVA E L

4003 ROH3 PARALLEL-OUT P I NS OUTPUT 400 750 n VouT = -0.5V RESISTANCE "O" LEVE L = 3 n VouT -o.5v 400 ROH4 SERIA L OUT OUTPUT 650 1200 RESISTANCE "O" LEVEL = 4004 ROH5 CM-ROM OUTPUT 320 600 n VouT -0.5V RESISTANCE "O" LEVE L 1.1 = vo uT -0.5V 4004 ROH6 CM-RAM LINES OUTPUT 1.8 Kn RESISTA NCE "O" LEVEL 0 (1) Typical values are for TA = 25 c and Nominal Supply Voltages. (2) If non-inverting input option Is used, v1 L = -6.5 Volts maximum.

7 Typical D.C. Characteristics

POWER SUPPLY CURRENT POWER SUPPLY CURRENT VS. TEMPERATURE VS. TEMPERATURE (4001 ) (4002) 18 .------.-----...... ---...... -----, 21 r----,-----..------,------,

= = tq,PW tq, Dl 400 nsec = = N t¢PW tq,Dl 400 nsec = 0 tq, D2 150 nsec t = 150 nsec .E q,02 � 16 1---�------+----+------t 19 c,: .§. .§. .... z .... w z a: w a: a: 14 1----...,.,...... -+----+- ---+- --1 a: B - -- ::J 17 t------'l",;;;:---+----"-....::t------l u >­ ...J >­ c.. ...J c.. c.. ::J c.. (/) ::J (/) ffi 12 f----P,,....---+----==,-...d-----1 t------"'�---t-----f"'--..:::-----l s: ffi 15 0 s: c.. 0 c..

10 +------�---���___. 1 3 ._____ ..__ ___ ..__ ___ ..__..;::,,,+---' 0 20 40 60 80 0 20 40 60 80 ° AMBIENT TEMPERATURE ( CI AMBIENT TEMPERATURE (° CI

POWER SUPPLY CURRENT POWER SUPPLY CURRENT VS. TEMPERATURE VS. TEMPERATURE (4003) (4004) 7 ,-----,-----..-----..------, 36 ,------,-----.,...... ----,------,

o = 400 nsec twL = twH = 8 µsec ., 1¢PW = tq, 1 M 0 = 0 tq,02 150 nsec .E .E 6 1------1-----+----+------! t- ----l � 32 t-=---=-+----+------� .§. .§...... z z w w a: a: a: � 5 F""--::::---il----+---=="""-+-=----I ::J 28 f----+-="""-""" u u >­ >­ ...J ...J c.. c.. c.. c.. ::J ::J (/) (/) a: 4 t----<,----+----+-----I ffi 24 1-- --+-----l-"'...... ;::,---+------l w s: s: 0 � c..

3 �---+----+----+------' 20 ...... ____ ..__ ___ ..__ ___ ..______. 0 20 40 60 80 0 20 40 60 80 AMBIENT TEMPERATURE (° CI AMBIENT TEMPERATURE (° CI

OUTPUT CURRENT VS. OUTPUT CURRENT VS. OUTPUT VOLTAGE OUTPUT VOLTAG E (4001, 4002) (4003) 7 .---..---.--...... -- .----.----..-----.. 1.4 ,---..---,--...... --.----,-- ...... ---,

v = -15.0V 00 v = -15.0V 1 _2 t---+---+---+--+- 00 tq,PW = tq, o 1 = 400 nsec twL = twH= 8 µsec = tq,02 150 nsec M N ..J .2 5 .9 1.0 -----+-- -+---+---+---+----< � � .§. .§. 4-�� -,..,_-+---+--+---t----+----t .... . 8 r-...... ,.,..__ _.... _ __.,. _ _+-- --t----+----< .... z z w w a: a: � .6 f---l-'....,.,....,.�=--<"O:::..-+c= a: ::J u u ...... ::J ::J � .4 t----t---+- ---1'"'-:-'""""ok:---+---+-----l c...... :, ::J 0 0

0 ...... _....__...... __--+--+--�---� 0 +-_....__...... __--+__ ..___�---+---' 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 OUTPUT VOLTAGE (VI OUTPUT VOLTAGE (VI

8 4001, 4002,4004 A. C. Characteristics

° ° TA =0 C to+70 C; VDD =-15V±5%, vss =GND

LIMIT PRODUCT SYMBO L TEST UNIT CONDITIONS MIN. MAX.

4001 /2/4 CLOCK RISE AN D \p R 10 50 FALL TIMES nsec tF

tPW CLOCK WI DTH 380 480 nsec

t CLOC K DELAY 01 400 550 nsec FROM 1 TO 2 CLOCK DELAY t02 150 300 FROM 2 TO 1 nsec

DATA-IN WRITE VI/ 350 TIME nsec

DATA-IN HOLD tH 40 TIME nsec

1 ) SET TIME FOR tos ( C 0uT = 500 pF for data lines DATA OUT, SYNC, 0 500 pF SYNC 2 nsec for CM-ROM, ( l CM- 160 pF CM-ROM RAM- (2l LINES for I 50 pF for CM-RAM HOLD TIME FOR t CouT = 20 pF OH DATA OUT, SYNC, 50 nsec CM-ROM ' CM-RAM I· LINES RISE AND FALL t ,t C u = 500 pF data R F TIMES FOR DATA 0 T for lines 500 pF for SYNC OUT, SYNC, CM-ROM, 500 nsec 160 pF for CM-ROM CM-RAMjLINES 50 pF for CM-RAM

4001/2 1/0 OUTPUT LINES to DELAY 600 nsec COUT = 20 pF

twc CM WRITE TIME 350 nsec

t HC CM HOLD TIME 10 nsec 1/0 INPUT LI NES 4001 t ,s SET TIME 50 nsec 1/0 INPUT LINES t l H HOLD TIME 100 nsec (3) t 1/0 OUTPUT LI NES C DELA Y ON CLEA R 200 nsec COUT = 20 pF

OTES: (1 loata out, S'l1\IC, CM-ROM, and CM-RAMi l ines are clocked out with the trailing edge of the 2blo ck. 2 ( )The CM-ROM and the selected CM-RAMi lines are always activated during A3 time. They are also activated during M2 time if an 1/0 and RAM instruction was fetched by the CPU, and during X2 time if an SAC instruction was fetched by the CPU. (3)Pin C L on 400 1 is used to asynchronously clear the output flip-flops associated with the 1/0 l ines.

9 4001, 4002, 4004 Timing Diagram

Outputs with loading conditions specified on A.C. Characteristics table. t _____.t

10% ¢1 90% 1 ----. \ 1 - ¢01 I 07 -

2

1 10s -- 0H @-1V DATA BUS LINES D ( 0 , D 1 . o 2 • o3 ) to

@-1V 4002 OUTPUT LINES. 400 1 1/0 OUTPUT LINES

1 1os ... -- 0H @-1V CM LINES @-5V CM OUT tF - --

4001 1/0 INPUT LINES

4001 CLEAR LINE (CL )

4001 1/0 OUTPUT LINES

Typical Load Characteristics SET TIME VS. OUTPUT CAPACITANCE (DATA LINES FOR 4001, 4002, 4004 SET TIME VS. OUTPUT CAPACITANCE & SYNC FOR 4004) (CM-ROM 4004)

t¢PW = 380 nsec t ¢PW = 380 nsec 1---+ --+---+- t¢Dl = 400 nsec 600 - - 600 >-- -+---+--- t¢Dl = 400 nsec t 02 = 150 nsec 9 t¢ = 150 nsec t¢ 02 t-- + -+- -+- R = t¢F = 40 nsec 500 - -- - = 40 nsec t\?R = t�F "' V00 = -15.0V 1-- -- - .9 § 500 -"',,c-+ -+- - v00 = -15.0V u 400 P-..:---'F"-'"'-"-+---+--+---1-----1---l ill E ;:;;- 400 ,___.,_-+�------+-----+----+---< ::;; 300 l-----""k---!----""-.!c,----P'.,.....,--1-- ---!---l ::;; I­ ;::: I­ I­ w � 300 ------' - - - - 1 -+ ""-.-+ ---"'k- ""',,,;;::- TA = O"C "' 200 t-- +- -t- -,) """,'""-::-+- -'l'--.::----lf----1 I +25° C

+70° C

OL---'--�---+---�--'----'---' 100 ...__ _._ __ _._ __ ..______,_ __ _.__ _ __, 100 200 300 400 500 600 700 800 100 200 300 400 500 600

OUTPUT CAPACITANCE (pF) OUTPUT CAPACITANCE (pF)

10 4003 A. C. Characteristics

T = 0° C to +70° C· V = - 1 5 + 5 °/ V = GND A ' DD - /O, SS LIMIT

SYMBOL TEST MIN. MAX. UNIT CONDITIONS

twL CP LOW WIDTH 6 10,000 µsec

1WH CP HIGH WIDTH 6 Note (1) 1;.sec

tcD CLOCK-ON TO DATA-OFF TIME 3 µsec

tDd CP TO DATA SET DE LAY Note (2) 250 nsec

td1 CP TO DATA OUT DELAY 250 1,750 nsec

td2 ENABLE TO DATA OUT DELAY 350 nsec CouT = 20 pF

td3 CP TO SERIAL OUT DELAY 200 1,250 nsec CouT = 20 pF NOTES: ( 1 ltwH can be any time greater than 6 µ sec. (2lData can occur prior to CP. 4003 Timing Diagram

CP

DATA IN

� td2 .._

ENABLE @ -5v (E) __...... """""1

SERIAL OUT

Capacitance = = 5° f = 1 MHz; V1N 0 V; TA 2 C ; Unmeasured Pins Grounded.

LIMIT (pF) LIMIT (pF)

PRODUCT SYMBOL TEST TYP. MAX. PRODUCT SYMBOL TEST TYP. MAX.

(1) 4001 /2/3/4 C1N INPUT 5 10 4002/4 CD1 DATA BUS 6.5 10 CAPACITANCE 1/0 LINES CAPACITANCE 4001 /2 CLOCK INPUT 8 c¢1 15 CAPACITANCE 4001 CD2 DATA BUS 9.5 15 1/0 LINES 4004 C¢2 CLOCK INPUT 14 20 CAPACITANCE CAPACITANCE

NOTE: (1) Refers to all input pins except data bus 1/0 and ¢1 and ¢2.

11 Packaging Information Ordering Information ( 1) The 4004 (CPU) is available in ceramic only and should be ordered as C4004. (2) The 4001 (ROM), 4002 (RAM) and 4003 (SR) are presently available off the shelf in plastic only. These devices can be ordered in ceramic on special request. Standard devices .�� CERAMIC PACKAGE should be ordered as fol lows: I OUTLINE P4001 Plastic Package P4002-1 (Metal Option #1 )- Plastic Package [PIN 1 : [ : : : [ :n P4002-2 (Metal Option #2)- Plastic Package P4003 Plastic Package

(3) Mask Programming of the 4001 The custom patterns, chip numbers and 1/0 10 1--�__j. 10 .065 4 options (including inverting and non-inverting 0 inputs or outputs and on-chip resistor con­ 45 ...____ .8557 - PLASTIC PACKAGE nected to either V or V ) must be specified OUTLINE 00 55 on a truth table for each 4001 ordered. Blank custom truth tables are available upon request 310 2 0 from Intel . . 025 REF . 9 1

.008 r.012 . 90 RTio 2

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