Intel(R) 64 and IA-32 Architectures Optimization Reference Manual

Total Page:16

File Type:pdf, Size:1020Kb

Intel(R) 64 and IA-32 Architectures Optimization Reference Manual N Intel® 64 and IA-32 Architectures Optimization Reference Manual Order Number: 248966-020 November 2009 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR IN- TENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITU- ATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "un- defined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The Intel® 64 architecture processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel® processor supporting Hyper- Threading Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information, see http://www.in- tel.com/technology/hyperthread/index.htm; including details on which processors support HT Technology. Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, perfor- mance or other benefits will vary depending on hardware and software configurations. Intel® Virtualization Technology-enabled BIOS and VMM applications are currently in development. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, oper- ating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel® 64 architecture-enabled BIOS. Performance will vary de- pending on your hardware and software configurations. Consult with your system vendor for more infor- mation. Intel, Pentium, Intel Atom, Intel Centrino, Intel Centrino Duo, Intel Xeon, Intel NetBurst, Intel Core, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel Speed- Step, MMX, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel lit- erature, may be obtained by calling 1-800-548-4725, or by visiting Intel’s website at http://www.intel.com Copyright © 1997-2009 Intel Corporation CONTENTS PAGE CHAPTER 1 INTRODUCTION 1.1 TUNING YOUR APPLICATION. 1-1 1.2 ABOUT THIS MANUAL . 1-2 1.3 RELATED INFORMATION. 1-4 CHAPTER 2 INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES 2.1 INTEL® CORE™ MICROARCHITECTURE AND ENHANCED INTEL CORE MICROARCHITECTURE . 2-2 2.1.1 Intel® Core™ Microarchitecture Pipeline Overview . 2-3 2.1.2 Front End. 2-4 2.1.2.1 Branch Prediction Unit . 2-6 2.1.2.2 Instruction Fetch Unit . 2-6 2.1.2.3 Instruction Queue (IQ) . 2-7 2.1.2.4 Instruction Decode . 2-8 2.1.2.5 Stack Pointer Tracker . 2-8 2.1.2.6 Micro-fusion . 2-9 2.1.3 Execution Core . 2-9 2.1.3.1 Issue Ports and Execution Units . 2-10 2.1.4 Intel® Advanced Memory Access . 2-13 2.1.4.1 Loads and Stores . 2-14 2.1.4.2 Data Prefetch to L1 caches. 2-15 2.1.4.3 Data Prefetch Logic . 2-15 2.1.4.4 Store Forwarding . 2-16 2.1.4.5 Memory Disambiguation. 2-17 2.1.5 Intel® Advanced Smart Cache . 2-18 2.1.5.1 Loads . 2-19 2.1.5.2 Stores. 2-20 2.2 INTEL® MICROARCHITECTURE (NEHALEM) . 2-21 2.2.1 Microarchitecture Pipeline . 2-21 2.2.2 Front End Overview. 2-23 2.2.3 Execution Engine . 2-25 2.2.3.1 Issue Ports and Execution Units . 2-25 2.2.4 Cache and Memory Subsystem. 2-27 2.2.5 Load and Store Operation Enhancements . 2-28 2.2.5.1 Efficient Handling of Alignment Hazards . 2-28 2.2.5.2 Store Forwarding Enhancement . 2-29 2.2.6 REP String Enhancement . 2-31 2.2.7 Enhancements for System Software . 2-32 2.2.8 Efficiency Enhancements for Power Consumption . 2-33 2.2.9 Hyper-Threading Technology Support in Intel Microarchitecture (Nehalem). 2-33 2.3 INTEL NETBURST® MICROARCHITECTURE . 2-33 2.3.1 Design Goals. 2-34 2.3.2 Pipeline . 2-35 2.3.2.1 Front End. 2-36 2.3.2.2 Out-of-order Core. 2-37 iii CONTENTS PAGE 2.3.2.3 Retirement . 2-37 2.3.3 Front End Pipeline Detail. 2-38 2.3.3.1 Prefetching. 2-38 2.3.3.2 Decoder . 2-38 2.3.3.3 Execution Trace Cache . 2-39 2.3.3.4 Branch Prediction . 2-39 2.3.4 Execution Core Detail . 2-40 2.3.4.1 Instruction Latency and Throughput . 2-40 2.3.4.2 Execution Units and Issue Ports . 2-41 2.3.4.3 Caches . 2-42 2.3.4.4 Data Prefetch . 2-44 2.3.4.5 Loads and Stores . ..
Recommended publications
  • Fujitsu Siemens Computers
    SPEC CINT2006 Result spec Copyright 2006-2014 Standard Performance Evaluation Corporation Fujitsu Siemens Computers SPECint_rate2006 = 21.4 PRIMERGY TX150 S5, Intel Pentium D processor 945, 3.40 GHz SPECint_rate_base2006 = 20.5 CPU2006 license: 22 Test date: May-2007 Test sponsor: Fujitsu Siemens Computers Hardware Availability: Sep-2006 Tested by: Fujitsu Siemens Computers Software Availability: Mar-2007 Copies 0 2.00 4.00 6.00 8.00 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0 38.0 40.0 25.5 400.perlbench 2 2 24.1 17.8 401.bzip2 2 2 16.7 22.4 403.gcc 2 22.5 429.mcf 2 2 23.2 19.8 445.gobmk 2 2 18.7 19.5 456.hmmer 2 2 17.1 18.5 458.sjeng 2 2 17.4 19.4 462.libquantum 2 2 18.8 39.9 464.h264ref 2 2 38.3 16.7 471.omnetpp 2 2 15.7 15.5 473.astar 2 2 14.9 28.2 483.xalancbmk 2 SPECint_rate_base2006 = 20.5 SPECint_rate2006 = 21.4 Hardware Software CPU Name: Intel Pentium D 945 Operating System: 64-Bit SUSE LINUX Enterprise Server 10, Kernel CPU Characteristics: 800 MHz system bus 2.6.16.21-0.8-smp on an x86_64 CPU MHz: 3400 Compiler: Intel C++ Compiler for IA32/EM64T application, Version 9.1 - Build 20070215, Package-ID: FPU: Integrated l_cc_p_9.1.047 CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip Auto Parallel: No CPU(s) orderable: 1 chip File System: ReiserFS Primary Cache: 12 K micro-ops I + 16 KB D on chip per core System State: Multiuser, Runlevel 3 Secondary Cache: 2 MB I+D on chip per core Base Pointers: 32-bit L3 Cache: None Peak Pointers: 32/64-bit Other Cache: None Other Software: Smart Heap Library, Version
    [Show full text]
  • Rochyderabad 27072017.Pdf
    List of Companies under Strike Off Sl.No CIN Number Name of the Company 1 U93000TG1947PLC000008 RAJAHMUNDRY CHAMBER OF COMMERCE LIMITED 2 U80301TG1939GAP000595 HYDERABAD EDUCATIONAL CONFERENCE 3 U52300TG1957PTC000772 GUNTI AND CO PVT LTD 4 U99999TG1964PTC001025 HILITE PRODUCTS PVT LTD 5 U74999AP1965PTC001083 BALAJI MERCHANTS ASSOCIATION PRIVATE LIMITED 6 U92111TG1951PTC001102 PRASAD ART PICTURES PVT LTD 7 U26994AP1970PTC001343 PADMA GRAPHITE INDUSTRIES PRIVATE LIMITED 8 U16001AP1971PTC001384 ALLIED TOBBACCO PACKERS PVT LTD 9 U63011AP1972PTC001475 BOBBILI TRANSPORTS PRIVATE LIMITED 10 U65993TG1972PTC001558 RAJASHRI INVESTMENTS PRIVATE LIMITED 11 U85110AP1974PTC001729 DR RANGARAO NURSING HOME PRIVATE LIMITED 12 U74999AP1974PTC001764 CAPSEAL PVT LTD 13 U21012AP1975PLC001875 JAYALAKSHMI PAPER AND GENERAL MILLS LIMITED 14 U74999TG1975PTC001931 FRUTOP PRIVATE LIMITED 15 U05005TG1977PTC002166 INTERNATIONAL SEA FOOD PVT LTD 16 U65992TG1977PTC002200 VAMSI CHIT FUNDS PVT LTD 17 U74210TG1977PTC002206 HIMALAYA ENGINEERING WORKS PVT LTD 18 U52520TG1978PTC002306 BLUEFIN AGENCIES AND EXPORTS PVT LTD 19 U52110TG1979PTC002524 G S B TRADING PRIVATE LIMITED 20 U18100AP1979PTC002526 KAKINADA SATSANG SAREES PRINTING AND DYEING CO PVT LTD 21 U26942TG1980PLC002774 SHRI BHOGESWARA CEMENT AND MINERAL INDUSTRIES LIMITED 22 U74140TG1980PTC002827 VERNY ENGINEERS PRIVATE LIMITED 23 U27109TG1980PTC002874 A P PRECISION LIGHT ENGINEERING PVT LTD 24 U65992AP1981PTC003086 CHAITANYA CHIT FUNDS PVT LTD 25 U15310AP1981PTC003087 R K FLOUR MILLS PVT LTD 26 U05005AP1981PTC003127
    [Show full text]
  • Class-Action Lawsuit
    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.
    [Show full text]
  • Professor Won Woo Ro, School of Electrical and Electronic Engineering Yonsei University the Intel® 4004 Microprocessor, Introdu
    Professor Won Woo Ro, School of Electrical and Electronic Engineering Yonsei University The 1st Microprocessor The Intel® 4004 microprocessor, introduced in November 1971 An electronics revolution that changed our world. There were no customer‐ programmable microprocessors on the market before the 4004. It propelled software into the limelight as a key player in the world of digital electronics design. 4004 Microprocessor Display at New Intel Museum A Japanese calculator maker (Busicom) asked to design: A set of 12 custom logic chips for a line of programmable calculators. Marcian E. "Ted" Hoff Recognized the integrated circuit technology (of the day) had advanced enough to build a single chip, general purpose computer. Federico Faggin to turn Hoff's vision into a silicon reality. (In less than one year, Faggin and his team delivered the 4004, which was introduced in November, 1971.) The world's first microprocessor application was this Busicom calculator. (sold about 100,000 calculators.) Measuring 1/8 inch wide by 1/6 inch long, consisting of 2,300 transistors, Intel’s 4004 microprocessor had as much computing power as the first electronic computer, ENIAC. 2 inch 4004 and 12 inch Core™2 Duo wafer ENIAC, built in 1946, filled 3000‐cubic‐ feet of space and contained 18,000 vacuum tubes. The 4004 microprocessor could execute 60,000 operations per second Running frequency: 108 KHz Founders wanted to name their new company Moore Noyce. However the name sounds very much similar to “more noise”. "Only the paranoid survive". Moore received a B.S. degree in Chemistry from the University of California, Berkeley in 1950 and a Ph.D.
    [Show full text]
  • A Viga T Ing R T Ificia L N Te Ll Igence
    July 24, 2018 Semiconductor Get real with artificial intelligence (AI) "Seriously, do you think you could actually purchase one of my kind in Walmart, say in the next 10 years?" NTELLIGENCE I "You do?! You'd better read this report from RTIFICIAL RTIFICIAL cover to cover, and I assure you Peter is not being funny at all this time." A ■ Fantasies remain in Star Trek. Let’s talk about practical AI technologies. ■ There are practical limitations in using today’s technology to realise AI elegantly. ■ AI is to be enabled by a collaborative ecosystem, likely dominated by “gorillas”. ■ An explosion of innovations in AI is happening to enhance user experience. ■ Rewards will go to the problem solvers that have invested in R&D ahead of others. Analyst(s) AVIGATING AVIGATING Peter CHAN T (82) 2 6730 6128 E [email protected] N IMPORTANT DISCLOSURES, INCLUDING ANY REQUIRED RESEARCH CERTIFICATIONS, ARE PROVIDED AT THE Powered by END OF THIS REPORT. IF THIS REPORT IS DISTRIBUTED IN THE UNITED STATES IT IS DISTRIBUTED BY CIMB the EFA SECURITIES (USA), INC. AND IS CONSIDERED THIRD-PARTY AFFILIATED RESEARCH. Platform Navigating Artificial Intelligence Technology - Semiconductor│July 24, 2018 TABLE OF CONTENTS KEY CHARTS .......................................................................................................................... 4 Executive Summary .................................................................................................................. 5 I. From human to machine .......................................................................................................10
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • Pentium Dual-Core Core2
    Intel Desktop CPU Roadmap 2004 2005 2008 2009 2010 2011 System Price 2006 2007 TDP Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 2H Q4 3.73GHz Core2 Extreme Kentsfield QX9775 (3.2GHz/ Northwood Presler Core2 Extreme Kentsfield 12MB/FSB1600) 6 cores/12MB L3 Prescott 2M QX6850 (3GHz/ Core2 Extreme Gulftown QX 3.2GHz(840) 3.46GHz(955) 3.73GHz(965) QX6700 (2.66GHz/ 8MB/FSB1333) Bloomfield 130W Extreme ≧ Extreme Extreme 3.46GHz 8MB/FSB1066) QX9770 (3.2GHz/ 965 (3.2GHz/8MB/ 975 (3.33GHz/8MB/ (XE) Smithfield-XE QX6800 (2.93GHz/ 12MB/FSB1600) Gulftown (XE) 130W Pentium 2.93GHz(X6800) 8MB/FSB1066) Yorkfield QPI6.4/DDR3 1066) QPI6.4/DDR3 1066) 999- Pentium 4 3.8GHz(670) Extreme Edition QX9650 (3GHz/ Extreme Edition Conroe XE 12MB/FSB1333) Core i7 4cores/PCIe x16 Nehalem/Core 2 Bloomfield $900 Prescott Gulftown Presler Core2 Quad Yorkfield Boundary 940 (2.93GHz/8MB/ 950 (3.06GHz/8MB/ 3.8GHz(571) 3.8GHz(672) 3.4GHz(950) 3.6GHz(960) Kentsfield Q9550 (2.83GHz/ QPI4.8/DDR3 1066) QPI4.8/DDR3 1066) Gulftown 3.8GHz(570) 12MB/FSB1333) Lynnfield Performance Conroe Q6600 (2.4GHz/ 130W Performance Performance 3.8GHz(670) 8MB/FSB1066) Q6700 (2.66GHz/ 2.xxGHz/8MB/ (P1) Prescott 3.6GHz(660) PCIe/DDR3 1066 (P1) Prescott 2M 3.2GHz(940) Pentium D 2.66GHz(E6700) 8MB/FSB1066) $560 Prescott 2M Q9650 (3GHz/ 3.2GHz(840) 9xx 12MB/FSB1333) Sandy Bridge 65W $4xx Smithfield Core2 Duo 4 cores/2 cores Pentium D Boundary Q9550s (2.83GHz/ 2.xxGHz/8MB/ 8xx Core2 Quad 12MB/FSB1333) PCIe/DDR3 1066 Cedar Mill Q9550 (2.83GHz/ Gulftown 3.6GHz(662) 3.6GHz(661)
    [Show full text]
  • Intel® Core™ Microarchitecture • Wrap Up
    EW N IntelIntel®® CoreCore™™ MicroarchitectureMicroarchitecture MarchMarch 8,8, 20062006 Stephen L. Smith Bob Valentine Vice President Architect Digital Enterprise Group Intel Architecture Group Agenda • Multi-core Update and New Microarchitecture Level Set • New Intel® Core™ Microarchitecture • Wrap Up 2 Intel Multi-core Roadmap – Updates since Fall IDF 3 Ramping Multi-core Everywhere 4 All products and dates are preliminary and subject to change without notice. Refresher: What is Multi-Core? Two or more independent execution cores in the same processor Specific implementations will vary over time - driven by product implementation and manufacturing efficiencies • Best mix of product architecture and volume mfg capabilities – Architecture: Shared Caches vs. Independent Caches – Mfg capabilities: volume packaging technology • Designed to deliver performance, OEM and end user experience Single die (Monolithic) based processor Multi-Chip Processor Example: 90nm Pentium® D Example: Intel Core™ Duo Example: 65nm Pentium D Processor (Smithfield) Processor (Yonah) Processor (Presler) Core0 Core1 Core0 Core1 Core0 Core1 Front Side Bus Front Side Bus Front Side Bus *Not representative of actual die photos or relative size 5 Intel® Core™ Micro-architecture *Not representative of actual die photo or relative size 6 Intel Multi-core Roadmap 7 Intel Multi-core Roadmap 8 Intel® Core™ Microarchitecture Based Platforms Platform 2006 20072007 Caneland Platform (2007) MP Servers Tigerton (QC) (2007) Bensley Platform (Q2’06)/ Glidewell Platform (Q2’06) ) DP Servers/ Woodcrest (Q3’06) DP Workstation Clovertown (QC) (Q1’07) Kaylo Platform (Q3’06)/ Wyloway Platform (Q3 ’06) UP Servers/ Conroe (Q3’06) UP Workstation Kentsfield (QC) (Q1’07) Bridge Creek Platform (Mid’06) Desktop -Home Conroe (Q3’06) Kentsfield (QC) (Q1’07) Desktop -Office Averill Platform (Mid’06) Conroe (Q3’06) Mobile Client Napa Platform (Q1’06) Merom (2H’06) All products and dates are preliminary 9 Note: only Intel® Core™ microarchitecture QC refers to Quad-Core and subject to change without notice.
    [Show full text]
  • Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
    Intel® Architecture Instruction Set Extensions and Future Features Programming Reference 319433-041 OCTOBER 2020 Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All product plans and roadmaps are subject to change without notice. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not “commercial” names and not intended to function as trademarks. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be ob- tained by calling 1-800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Copyright © 2020, Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
    [Show full text]
  • Efficient Parallel Algorithms for 3D Laplacian Smoothing on The
    applied sciences Article Efficient Parallel Algorithms for 3D Laplacian Smoothing on the GPU Lei Xiao 1, Guoxiang Yang 1,*, Kunyang Zhao 2,3 and Gang Mei 1,* 1 School of Engineering and Technology, China University of Geosciences (Beijing), Beijing 100083, China; [email protected] 2 Airport Engineering Civil Aviation R&D Base, China Airport Construction Group Co., Ltd., Beijing 100621, China; [email protected] 3 China Super-Creative Airport Technical Co., Ltd., Beijing 100621, China * Correspondence: [email protected] (G.Y.); [email protected] (G.M.); Tel.: +86-10-8232-2627 (G.Y.) Received: 13 November 2019; Accepted: 6 December 2019; Published: 11 December 2019 Abstract: In numerical modeling, mesh quality is one of the decisive factors that strongly affects the accuracy of calculations and the convergence of iterations. To improve mesh quality, the Laplacian mesh smoothing method, which repositions nodes to the barycenter of adjacent nodes without changing the mesh topology, has been widely used. However, smoothing a large-scale three dimensional mesh is quite computationally expensive, and few studies have focused on accelerating the Laplacian mesh smoothing method by utilizing the graphics processing unit (GPU). This paper presents a GPU-accelerated parallel algorithm for Laplacian smoothing in three dimensions by considering the influence of different data layouts and iteration forms. To evaluate the efficiency of the GPU implementation, the parallel solution is compared with the original serial solution. Experimental results show that our parallel implementation is up to 46 times faster than the serial version. Keywords: computational mesh processing; 3D laplacian smoothing; parallel algorithm; graphics processing unit 1.
    [Show full text]
  • Understanding the Performance of HPC Applications
    Understanding the Performance of HPC Applications Brian Gravelle March 2019 Abstract High performance computing is an important asset to scientific research, enabling the study of phe- nomena such as nuclear physics or climate change, that are difficult or impossible to be studied in traditional experiments or allowing researchers to utilize large amounts of data from experiments such as the Large Hadron Collider. No matter the use of HPC, the need for performance is always present; however, the fast-changing nature of computer systems means that software must be continually updated to run efficiently on the newest machines. In this paper, we discuss methods and tools used to understand the performance of an application running on HPC systems and how this understanding can translate into improved performance. We primarily focus on node-level issues, but also mention some of the basic issues involved with multi-node analysis as well. 1 Introduction In the modern world, supercomputing is used to approach many of the most important questions in science and technology. Computer simulations, machine learning programs, and other applications can all take ad- vantage of the massively parallel machines known as supercomputers; however, care must be taken to use these machines effectively. With the advent of multi- and many- core processors, GPGPUs, deep cache struc- tures, and FPGA accelerators, getting the optimal performance out of such machines becomes increasingly difficult. Although many modern supercomputers are theoretically capable of achieving tens or hundreds of petaflops, applications often only reach 15-20% of that peak performance. In this paper, we review recent research surrounding how users can understand and improve the performance of HPC applications.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]