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MCS® 51 Microcontroller Family User's Manual

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MCS® 51 Microcontroller Family User's Manual MCS@51 MICROCONTROLLER FAMILY USER’S MANUAL ORDER NO.: 272383-002 FEBRUARY 1994 Intel Corporation makes no warrsnfy for the uee of ite products and assumes no responsibility for any ewors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notk Contact your local Intel sales office or your distributor to obtain the latest speoificationa before placing your product order. MDS is an ordering code only and is not usad ae a product name or trademark of Intel Corporation. Intel Corporation and Intel’s FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products, ●Ofher brands and names are the properly of their respective owners, Additional copies of this document or other Intel literature maybe obtained from: Intel Corporation Literature Selas P.O. Box 7S41 Mt. Prospect, IL 6005S-7641 or call 1-800-879-4683 c-INTELCORPORATION, 1093 MCS” 51 CONTENTS PAGE MICROCONTROLLER c“*pTf==1 FAMILY MCS 51 Family of Microcontrollers USER’S MANUAL Archkedural Ovewiew .............................l-l CHAPTER 2 MCS 51 Programmer’s Guide and Instruction Set ..........................................2-l CHAPTER 3 8051, 8052 and 80C51 Hardware Description ...............................................3.l CHAPTER 4 8XC52J54/58 Hardware Description ............4-1 CHAPTER 5 8XC51 FX Hardware Description .................5-1 CHAPTER 6 87C51GB Hardware Description .................8-1 CHAPTER 7 83CI 52 Hardware Description ....................7-1 MCS@51 Family of 1 Microcontrollers Architectural Overview MCS@51 FAMILY OF CONTENTS PAGE MICROCONTROLLERS INTRODUCTION .........................................1-3 ARCHITECTURAL CHMOSDevices .....”.....’.......”.....-...-..........I-5 OVERVIEW M;~$&:RGA-~oN INMc- 51 .................................................1-6 Lo ical Separation of Program and Data h emoy ....................................................l+ Program Memo~ .........................................l-7 Data Memory ...............................................1 -8 THE MC951 INSTRUCTION SET .............1 -9 Program Status Word ..................................1 -9 Addressing Modes .....................................l-l O Arithmetic Instructions ...............................1-10 Logical lnstrudions ....................................l.l2 Data Tran#ers ...........................................l.l2 Boolean Instructions ..................................1-14 Jump Instructions ......................................1-16 CPU TIMING .............................................l-l7 Machine Cycles .........................................1-18 Interrupt Structure ......................................l.2O ADDITIONAL REFERENCES ...................1 -22 1-1 ir&L [email protected] ARCHITECTURAL OVERVIEW INTRODUCTION The8051 is the original member of the MCW-51 family, and is the core for allMCS-51 devices. The features of the 8051 core are - ● 8-bit CPU optimized for control applications ● Extensive Boolean processing (Single-blt logic) capabtilties ● 64K Program Memory address space ● 64K Data Memory address space ● 4K bytes of on-chip Program Memory ● 128 bytesof on-chip Data RAM ● 32 bidirectional and individually addressable 1/0 lines ● Two 16-bit timer/counters ● Full duplex UART ● 6-source/5-vector interrupt structure with two priority levels ● On-chip clock oscillator The basic architectural structure of this 8051 core is shown in Figure L EXTERNAL INTERRUPTS ,, I I COUNTER INPUTS w II H H BUS SERIAL 4 1/0 PORTS CONTROL PORT 11 QTXO RXD Po P2 PI P3 AODRESS/DATA 270251-1 Figure 1. Block Diagram of the 8051 Core 1-3 intd. MCS@-51 ARCHITECTURAL OVERVIEW 1-4 i~. MCS@’-5l ARCHITECTURAL OVERVIEW 1-5 i~. [email protected] ARCHITECTURAL OVERVIEW PROORAMMrhtosv OATAMEMORY (REM ONLY) (RW/WRlT2) * ----------- -------------- ------------------------ . 8 $ t 8 1 FFFFw s 8 8 1 I I I 1 1 1 I 1 1 I 0 1 T - 1 8 I 1 1 I * 1 1 I 0 I 1 I I 1 1 EXIERNALm I I 1 : # o 1 o I 8 1 # I 0 1 8 I 0 EXTERNAL 1 9 I 0 1 8 I 8 1 8 - I 0 1 0 1 0 I 0 9 1 9 : I 1 t 1 I 1 # I I I I I , , , 1 B 1 IN7ERNM I I I : FfH: ------ 1 I : 0: I # : 9, o G=o m.1 e, 1 0 2STERNAL IN7ERNAL : 9 1 0 0 1 0 9 9 @ * 8 0 * I 1 1 I 0000 I I 00 0000 J: 1 I ,1+ : 1 ● - --- -------- -------- -.! ●-------- --------- ..- -. -.-: 1% tiR 270251-2 Figure 2. MCW’-51 Memory Structure CHMOS Devices MEMORY ORGANIZATION IN MCS@-51 DEVICES Functionally, the CHMOS devices (designated with “C” in the middle of the device name) me all fiuy compatible with the 8051, but being CMOS, draw less Logical Separation of Program and current than an HMOS counterpart. To further exploit Data Memory the power savings available in CMOS circuitry, two re- duced power modes are added AU MCS-51 devices have separate address spacea for ● Software-invoked Idle Mode, during which the CPU Program and Data Memory, as shown in Figure 2. The is turned off while the RAM and other on-chip logical separation of Program and Data Memory allows peripherals continue operating. In this mode, cur- the Data Memory to be acceased by 8-bit addressea, rent draw is reduced to about 15% of the current which can be more quickly stored and manipulated by drawn when the device is fully active. an 8-bit CPU. Nevertheless, ld-bh Data Memory ad- dresses can also be generated through the DPTR regis- ● Software-invoked Power Down Mode, during which ter. all on-chip activities are suspended. The on-chip RAM continues to hold its data. In this mode the Program Memory can only be read, not written to. device typically draws less than 10 pA. There can be up to 64K bytes of Program Memory. In Although the 80C51BH is functionally compatible with the ROM and EPROM versions of these devices the its HMOS counterpart, s~lc differeneea between the loweat 4K, 8K or 16K bytes of Program Memory are two types of devices must be considered in the design of provided on-chip. Refer to Table 1 for the amount of an application circuit if one wiahea to ensure complete on-chip ROM (or EPROM) on each device. In the interchangeability between the HMOS and CHMOS ROMleas versions all Program Memory is external. devices. These considerations are discussed in the Ap The read strobe for external Program Memory is the plieation Note AP-252, “Designing with the signal PSEN @rogram Store Enable). 80C5lBH. For more information on the individual devices and features listed in Table 1, refer to the Hardware De scriptions and Data Sheets of the specific device. 1-6 intel. MCS@-51 ARCHITECTURAL OVERVIEW Data Memory occupies a separate addrexs space from The lowest 4K (or SK or 16K) bytes of Program Mem- %OgrCt122 hkznory. Up to 64K bytes of exterttd RAM ory can be either in the on-chip ROM or in an external can be addreased in the externrd Data Memo~. ROM. This selection is made by strapping the ~ (Ex- The CPU generatea read and write signals RD and ternal Access) pin to either VCC or Vss. ~, as needed during external Data Memory accesses. In the 4K byte ROM devices, if the= pin is strapped External Program Memory and external Data Memory to VcC, then program fetches to addresses 0000H ~~ combined if-desired by applying the ~ ~d through OFFFH are directed to the internal ROM. Pro- PSEN signals to the inputs of an AND gate and using gram fetches to addresses 1000H through FFFFH are the output of the gate as the read strobe to the external directed to external ROM. Program/Data memory. In the SK byte ROM devices, = = Vcc selects ad- dresses (XtOOHthrough lFFFH to be internal, and ad- ProgramMemory dresses 2000H through F’FFFH to be external. Figure 3 shows a map of the lower part of the Program In the 16K byte ROM devices, = = VCC selects ad- Memory. After reset, the CPU begins execution from dresses 0000H through 3FFFH to be internal, and ad- location OWOH. dresses 4000H through FFFFH to be external. AS shown in F@ure 3, each interrupt is assigned a tixed If the ~ pin is strapped to Vss, then all program location in Program Memory. The interrupt causes the fetches are directed to external ROM. The ROMleas CPU to jump to that location, where it commences exe- parts must have this pin externally strapped to VSS to cution of the serviee routine. External Interrupt O, for enable them to execute properly. example, is assigned to location 0003H. If External In- terrupt O is going to & used, its service routine must The read strobe to externally: PSEN, is used for all begin at location 0003H. If the interrupt is not going to external oro.cram fetches. PSEN LSnot activated for in- be used, its service location is available as general pur- pose Program Memory. m% EPROM & ‘s 1 Po INSTR. ..-. (O033H) m 002EH = ALE 002SH LArcn AOOR INTSRRUPT 00IBH LOCATIONS l== Ssvrm a’s ‘z~ 1 0013H II 000SH 270251-4 0003H Figure 4. Executing from External R2S~i 0000H Program Memory 270251-3 The hardware configuration for external program exe- Figure 3. MCW’-51 Program Memory cution is shown in Figure 4. Note that 16 I/O lines (Ports O and 2) are dedicated to bus fictions during The interrupt aeMce locations are spaced at 8-byte in- external Program Memory f~hes. Port O(POin Figure tervak 0U03H for External Interrupt O, 000BH for 4) servex as a multiplexed address/data bus. It emits Tmer O, 0013H for External Interrupt 1, 00IBH for the low byte of the Program Counter (PCL) as an ad- Timer 1, etc. If an interrupt service routine is short dress, snd then goes into a float state awaiting the arriv- enough (as is often the case in control applications), it al of the code byte from the Program Memory. During can reside entirely within that 8-byte interval. Longer the time that the low byte of the Program Counter is service routinea can use a jump instruction to skip over valid on PO, the signal ALE (Address Latch Enable) subsequent interrupt locations, if other interrupts are in clocks this byte into an address latch.
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