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Computational Economics and Econometrics
Computational Economics and Econometrics A. Ronald Gallant Penn State University c 2015 A. Ronald Gallant Course Website http://www.aronaldg.org/courses/compecon Go to website and discuss • Preassignment • Course plan (briefly now, in more detail a few slides later) • Source code • libscl • Lectures • Homework • Projects Course Objective – Intro Introduce modern methods of computation and numerical anal- ysis to enable students to solve computationally intensive prob- lems in economics, econometrics, and finance. The key concepts to be mastered are the following: • The object oriented programming style. • The use of standard data structures. • Implementation and use of a matrix class. • Implementation and use of numerical algorithms. • Practical applications. • Parallel processing. Details follow Object Oriented Programming Object oriented programming is a style of programming devel- oped to support modern computing projects. Much of the devel- opment was in the commercial sector. The features of interest to us are the following: • The computer code closely resembles the way we think about a problem. • The computer code is compartmentalized into objects that perform clearly specified tasks. Importantly, this allows one to work on one part of the code without having to remember how the other parts work: se- lective ignorance • One can use inheritance and virtual functions both to describe the project design as interfaces to its objects and to permit polymorphism. Inter- faces cause the compiler to enforce our design, relieving us of the chore. Polymorphism allows us to easily swap in and out objects so we can try different models, different algorithms, etc. • The structures used to implement objects are much more flexible than the minimalist types of non-object oriented language structures such as subroutines, functions, and static common storage. -
Daniel D. Garcia
DANIEL D. GARCIA [email protected] http://www.cs.berkeley.edu/~ddgarcia/ 777 Soda Hall #1776 UC Berkeley Berkeley, CA 94720-1776 (510) 517-4041 ______________________________________________________ EDUCATION MASSACHUSETTS INSTITUTE OF TECHNOLOGY Cambridge, MA B.S. in Computer Science, 1990 B.S. in Electrical Engineering, 1990 UNIVERSITY OF CALIFORNIA, BERKELEY Berkeley, CA M.S. in Computer Science, 1995 Ph.D. in Computer Science, 2000. Area: computer graphics and scientific visualization. Brian Barsky, advisor. TEACHING AWARDS • Outstanding Graduate Student Instructor in Computer Science (1992) • Electrical Engineering and Computer Science Outstanding Graduate Student Instructor (1997) • Computer Science Division Diane S. McEntyre Award for Excellence in Teaching (2002) • Computer Science Division IT Faculty Award for Excellence in Undergraduate Teaching (2005) • UC Berkeley “Everyday Hero” Award (2005) • Highest “teaching effectiveness” rating for any EECS lower division instructor, ever (6.7, since tied) (2006) • CS10: The Beauty and Joy of Computing chosen as 1 of 5 national pilots for AP CS: Principles course (2010) • CS10: The Beauty and Joy of Computing chosen as a University of California Online Course Pilot (2011) • Association of Computing Machinery (ACM) Distinguished Educator (2012) • Top 5 Professors to Take Classes with at UC Berkeley, The Black Sheep Online (2013) • CS10 becomes first introductory computing class at UC Berkeley with > 50% women (2013,2014) • Ten Most Popular MOOCs Starting in September 2015 and January 2016, Class Central (2015, 2016) • LPFI's Lux Award for being “Tech Diversity Champion” (2015) • NCWIT’s Undergraduate Research Mentoring (URM) Award (2016) • NCWIT’s Extension Services Transformation Award, Honorable Mention (2016) • CS10 becomes first introductory computing class at UC Berkeley with > 60% women (2017) • SAP Visionary Member Award (2017) • Google CS4HS Ambassador (2017) • CS10 becomes first introductory computing class at UC Berkeley with > 65% women (2018) Updated through 2018-07-01 1 / 28 Daniel D. -
Xinya (Leah) Zhao Abdulahi Abu Outline
K-Computer Xinya (Leah) Zhao Abdulahi Abu Outline • History of Supercomputing • K-Computer Architecture • Programming Environment • Performance Evaluation • What's next? Timeline of Supercomputing Control Data The Cray era Massive Processing Petaflop Computing Corporation (1960s) (mid-1970s - 1980s) (1990s) (21st century) • CDC 1604 (1960): First • 80 MHz Cray-1 (1976): • Hitachi SR2201 (1996): • Realization: Power of solid state The most successful used 2048 processors large number of small • CDC 6600 (1964): 100 supercomputers in history connected via a fast three processors can be computers were sold at $8 • Vector processor dimensioanl corssbar harnessed to achieve high million each • Introduced chaining in network performance • Gained speed by "farming which scalar and vector • ASCI Red: mesh-based • IBM Blue Gene out" work to peripheral registers generate interim MIMD massively parallel architecture: trades computing elements, results system with over 9,000 processor speed for low freeing the CPU to • The Cray-2 (1985): No compute nodes and well power consumption, so a process actual data chaning and high memory over 12 terabytes of disk large number of • STAR-100: First to use latency with deep storage processors can be used at vector processing pipelinging • ASCI Red was the first air cooled temperature ever to break through the • K computer (2011) : 1 teraflop barrier fastest in the world K Computer is #1 !!! Why K Computer? Purpose: • Perform extremely complex mathematical or scientific calculations (ex: modelling the changes -
Fortran Resources 1
Fortran Resources 1 Ian D Chivers Jane Sleightholme May 7, 2021 1The original basis for this document was Mike Metcalf’s Fortran Information File. The next input came from people on comp-fortran-90. Details of how to subscribe or browse this list can be found in this document. If you have any corrections, additions, suggestions etc to make please contact us and we will endeavor to include your comments in later versions. Thanks to all the people who have contributed. Revision history The most recent version can be found at https://www.fortranplus.co.uk/fortran-information/ and the files section of the comp-fortran-90 list. https://www.jiscmail.ac.uk/cgi-bin/webadmin?A0=comp-fortran-90 • May 2021. Major update to the Intel entry. Also changes to the editors and IDE section, the graphics section, and the parallel programming section. • October 2020. Added an entry for Nvidia to the compiler section. Nvidia has integrated the PGI compiler suite into their NVIDIA HPC SDK product. Nvidia are also contributing to the LLVM Flang project. Updated the ’Additional Compiler Information’ entry in the compiler section. The Polyhedron benchmarks discuss automatic parallelisation. The fortranplus entry covers the diagnostic capability of the Cray, gfortran, Intel, Nag, Oracle and Nvidia compilers. Updated one entry and removed three others from the software tools section. Added ’Fortran Discourse’ to the e-lists section. We have also made changes to the Latex style sheet. • September 2020. Added a computer arithmetic and IEEE formats section. • June 2020. Updated the compiler entry with details of standard conformance. -
Fujitsu PRIMEHPC FX10 Supercomputer
Brochure Fujitsu PRIMEHPC FX10 Supercomputer Fujitsu PRIMEHPC FX10 Supercomputer Fujitsu's PRIMEHPC FX10 supercomputer provides the ability to address these high magnitude problems by delivering over 23 Petaflops, a quantum leap in processing performance. Combining high performance, scalability, and Green Credentials as well as High Performance High Reliability and Operability in Large reliability with superior energy efficiency, Mean Power Savings Systems PRIMEHPC FX10 further improves on Fujitsu's In today's quest for a greener world the Incorporating RAS functions, proven on supercomputer technology employed in the "K compromise between high performance and mainframe and high-end SPARC64 servers, computer," which achieved the world's environmental footprint is a major issue. At the SPARC64 IXfx processor delivers higher top -ranked performance*¹ in November 2011. heart of PRIMEHPC FX10 are SPARC64 IXfx reliability and operability. The flexible 6D All of the supercomputer's components—from processors that deliver ultra high performance of Mesh/Torus architecture of the Tofu processors to middleware—have been 236.5 Gigaflops and superb power efficiency of interconnect also contributes to overall developed by Fujitsu, thereby delivering high over 2 Gigaflops per watt. reliability. The result is outstanding levels of reliability and operability. The system operation: enhanced by the advanced set of can be scaled to meet customer needs, up to a Application Performance and Simple system management, monitoring, and job 1,024 rack configuration achieving a Development management software, and the highly super -high speed of 23.2 PFLOPS. SPARC64 IXfx processor includes extensions for scalable distributed file system. HPC applications known as HPC-ACE. This plus Fujitsu has developed PRIMEHPC FX10, a wide memory bandwidth, high performance Tofu supercomputer capable of world-class interconnect, Technical Computing Suite, HPC performance of up to 23.2 PFLOPS. -
ACM Education Board and Education Council FY2017-2018 Executive
ACM Education Board and Education Council FY2017-2018 Executive Summary This report summarizes the activities of the ACM Education Board and the Education Council1 in FY 2017-18 and outlines priorities for the coming year. Major accomplishments for this past year include the following: Curricular Volumes: Joint Taskforce on Cybersecurity Education CC2020 Completed: Computer Engineering Curricular Guidelines 2016 (CE2016) Enterprise Information Technology Body of Knowledge (EITBOK) Information Technology 2017 (IT2017) Masters of Science in Information Systems 2016 (MSIS2016) International Efforts: Educational efforts in China Educational efforts in Europe/Informatics for All Taskforces and Other Projects: Retention taskforce Learning at Scale Informatics for All Committee International Education Taskforce Global Awareness Taskforce Data Science Taskforce Education Policy Committee NDC Study Activities and Engagements with ACM SIGs and Other Groups: CCECC Code.org CSTA 1 The ACM Education Council was re-named in fall 2018 to the ACM Education Advisory Committee. For historical accuracy, the EAC will be called the Education Council for this report. 1 SIGCAS SIGCHI SIGCSE SIGHPC SIGGRAPH SIGITE Other Items: Education Board Rotation Education Council Rotation Future Initiatives Global Awareness Taskforce International Education Framework Highlights This is a very short list of the many accomplishments of the year. For full view of the work to date, please see Section One: Summary of FY 2017-2018 Activities. Diversity Taskforce: The Taskforce expects to complete its work by early 2019. Their goals of Exploring the data challenges Identifying factors contributing to the leaky pipeline Recommending potential interventions to improve retention Learning at Scale: The Fifth Annual ACM Conference on Learning @ Scale (L@S) was held in London, UK on June 26-28, 2018. -
Candidate for Chair Jeffrey K. Hollingsworth University Of
Candidate for Chair Jeffrey K. Hollingsworth University of Maryland, College Park, MD, USA BIOGRAPHY Academic Background: Ph.D., University of Wisconsin, 1994, Computer Sciences. Professional Experience: Professor, University of Maryland, College Park, MD, 2006 – Present; Associate /Assistant Professor, University of Maryland, College Park, MD, 1994 – 2006; Visiting Scientist, IBM, TJ Watson Research Center, 2000 – 2001. Professional Interest: Parallel Computing; Performance Measurement Tools; Auto-tuning; Binary Instrumentation; Computer Security. ACM Activities: Vice Chair, SIGHPC, 2011 – Present; Member, ACM Committee on Future of SIGs, 2014 – 2015; General Chair, SC Conference, 2012; Steering Committee Member (and Chair '13), SC Conference, 2009 – 2014. Membership and Offices in Related Organizations: Editor in Chief, PARCO, 2009 – Present; Program Chair, IPDPS, 2016; Board Member, Computing Research Association (CRA), 2008 – 2010. Awards Received: IPDPS, Best Paper - Software, 2011; SC, Best Paper - Student lead Author, 2005; IPDPS, Best Paper - Software, 2000. STATEMENT There is a critical need for a strong SIGHPC. Until SIGHPC was founded five years ago, the members of the HPC community lacked a home within ACM. While the SC conference provides a nexus for HPC activity in the fall, we needed a full-time community. Now that the initial transition of the SC conference from SIGARCH to SIGHPC is nearly complete, the time is right to start considering what other meetings and activities SIGHPC should undertake. We need to carefully identify meetings to sponsor or co-sponsor. Also, SIGHPC needs to continue and expand its role as a voice for the HPC community. This includes mentoring young professionals, actively identifying and nominating members for society wide awards, and speaking for the HPC community within both the scientific community and society at large. -
2017 ALCF Operational Assessment Report
ANL/ALCF-20/04 2017 Operational Assessment Report ARGONNE LEADERSHIP COMPUTING FACILITY On the cover: This visualization shows a small portion of a cosmology simulation tracing structure formation in the universe. The gold-colored clumps are high-density regions of dark matter that host galaxies in the real universe. This BorgCube simulation was carried out on Argonne National Laboratory’s Theta supercomputer as part of the Theta Early Science Program. Image: Joseph A. Insley, Silvio Rizzi, and the HACC team, Argonne National Laboratory Contents Executive Summary ................................................................................................ ES-1 Section 1. User Support Results .............................................................................. 1-1 ALCF Response ........................................................................................................................... 1-1 Survey Approach ................................................................................................................ 1-2 1.1 User Support Metrics .......................................................................................................... 1-3 1.2 Problem Resolution Metrics ............................................................................................... 1-4 1.3 User Support and Outreach ................................................................................................. 1-5 1.3.1 Tier 1 Support ........................................................................................................ -
Totalview: Debugging from Desktop to Supercomputer
ATPESC 2017 TotalView: Debugging from Desktop to Supercomputer Peter Thompson Principal Software Support Engineer August 8, 2017 © 2017 Rogue Wave Software, Inc. All Rights Reserved. 1 Some thoughts on debugging • As soon as we started programming, we found out to our surprise that it wasn’t as easy to get programs right as we had thought. Debugging had to be discovered. I can remember the exact instant when I realized that a large part of my life from then on was going to be spent in finding mistakes in my own programs. – Maurice Wilkes • Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not smart enough to debug it. – Brian W. Kernigan • Sometimes it pays to stay in bed on Monday, rather than spending the rest of the week debugging Monday’s code. – Dan Saloman © 2017 Rogue Wave Software, Inc. All Rights Reserved. 2 Rogue Wave’s Debugging Tool TotalView for HPC • Source code debugger for C/C++/Fortran – Visibility into applications – Control over applications • Scalability • Usability • Support for HPC platforms and languages © 2017 Rogue Wave Software, Inc. All Rights Reserved. 3 TotalView Overview © 2017 Rogue Wave Software, Inc. All Rights Reserved. 4 TotalView Origins Mid-1980’s Bolt, Berenak, and Newman (BBN) Butterfly Machine An early ‘Massively Parallel’ computer © 2017 Rogue Wave Software, Inc. All Rights Reserved. 5 How do you debug a Butterfly? • TotalView project was developed as a solution for this environment – Able to debug multiple processes and threads – Point and click interface – Multiple and Mixed Language Support • Core development group has been there from the beginning and have been/are involved in defining MPI interfaces, DWARF, and lately OMPD (Open MP debugging interface) © 2017 Rogue Wave Software, Inc. -
Masahori Nunami (NIFS)
US-Japan Joint Institute for Fusion Theory National Institute for Fusion Science Workshop on Innovations and co-designs of fusion simulations towards extreme scale computing August 20-21, 2015 Nagoya University, Nagoya, Japan Numerical Simulation Research in NIFS and Fujitsu’s New Supercomputer PRIMEHPC FX100 Masanori Nunamia, Toshiyuki Shimizub aNational Institute for Fusion Science, Japan bFujitsu, Japan Outline M. Nunami (NIFS) l Overview of Numerical Simulation Reactor Research Project in NIFS l Supercomputers in NIFS and Japan T. Shimizu (Fujitsu) l Fujitsu’s new supercomputer (FX100) l Features and evaluations l Application evaluation l The next step in exascale capability Page § 2 Research activities in NIFS In NIFS, there exists 7 divisions and 3 projects for fusion research activities. LHD project NSR project FER project Page § 3 Numerical Simulation Reactor Research Project ( NSRP ) NSRP has been launched to continue the tasks in simulation group in NIFS, and evolve them on re-organization of NIFS in 2010. Final Goal Based on large-scale numerical simulation researches by using a super-computer, - To understand and systemize physical mechanisms in fusion plasmas - To realize ultimately the “Numerical Simulation Reactor” which will be an integrated predictive modeling for plasma behaviors in the reactor. Realization of numerical test reactor requires - understanding all element physics in each hierarchy, - inclusion of all elemental physical processes into our numerical models, - development of innovative simulation technology -
IMSL C Function Catalog 2020.0
IMSL® C Numerical Library Function Catalog Version 2020.0 1 At the heart of the IMSL C Numerical Library is a comprehensive set of pre-built mathematical and statistical analysis functions that developers can embed directly into their applications. Available for a wide range of computing platforms, the robust, scalable, portable and high performing IMSL analytics allow developers to focus on their domain of expertise and reduce development time. 2 IMSL C Numerical Library v2020.0 Function Catalog COST-EFFECTIVENESS AND VALUE including transforms, convolutions, splines, The IMSL C Numerical Library significantly shortens quadrature, and more. application time to market and promotes standardization. Descriptive function names and EMBEDDABILITY variable argument lists have been implemented to Development is made easier because library code simplify calling sequences. Using the IMSL C Library readily embeds into application code, with no reduces costs associated with the design, additional infrastructure such as app/management development, documentation, testing and consoles, servers, or programming environments maintenance of applications. Robust, scalable, needed. portable, and high performing analytics with IMSL Wrappers complicate development by requiring the forms the foundation for inherently reliable developer to access external compilers and pass applications. arrays or user-defined data types to ensure compatibility between the different languages. The A RICH SET OF PREDICTIVE ANALYTICS IMSL C Library allows developers to write, build, FUNCTIONS compile and debug code in a single environment, and The library includes a comprehensive set of functions to easily embed analytic functions in applications and for machine learning, data mining, prediction, and databases. classification, including: Time series models such as ARIMA, RELIABILITY GARCH, and VARMA vector auto- 100% pure C code maximizes robustness. -
Daniel Andresen
Daniel Andresen Professor, Department of Computer Science Director, Institute for Computational Research in Engineering and Science Michelle Munson-Serban Simu Keystone Research Scholar Kansas State University 2174 Engineering Hall Manhattan, KS 66506-2302 Tel: 785–532–6350 Fax: 785–532–7353 Email: [email protected] WWW: http://www.cis.ksu.edu/∼dan EDUCATION Ph.D., Computer Science, University of California, Santa Barbara, CA. September, 1997 Thesis Title: “SWEB++: Distributed Scheduling and Software Support for High Performance WWW Applications.” Advisor: Prof. Tao Yang M.S., Computer Science, California Polytechnic State University, San Luis Obispo, CA. September, 1992. B.S., Computer Science and Mathematics, double major, magna cum laude, honors in major, Westmont College, Santa Barbara, CA. May, 1990. AWARDS Michelle Munson-Serban Simu Keystone Research Scholar September, 2020 NSF CAREER Award 2001 KSU Engineering Student Council Outstanding Leadership Award December, 2004, 2005, 2008 Residencehall’sProfessoroftheYearnominee 2000,2002 Cargill Faculty Fellow 1999, 2000 College of Engg. James L. Hollis Memorial Award for Excellence in Undergrad- uate Teaching nominee 1999, 2006 RESEARCH Parallel and distributed systems, HPC scheduling, Research Cyberinfrastructure, INTERESTS digital libraries/WWW applications, Grid/cloud computing, and scientific mod- eling. TEACHING Graduate-level parallel/distributed computing, scientific computing, networking, INTERESTS operating systems, and computer architectures. Courses taught include operat- ing systems (CIS520), Topics in Distributed Systems (CIS825), Introduction to Computer Architecture (CIS450), Software Engineering (CIS642), Web Interface Design (CIS526), and Advanced World Wide Web Technologies (CIS726). 1 WORK Professor in the Department of Computing and Information Sciences at EXPERIENCE Kansas State University. 2015-present Associate Professor in the Department of Computing and Information SciencesatKansasStateUniversity.