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A Baseband, Impulse Ultra-Wideband Transceiver Front-End for Low Power Applications

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A Baseband, Impulse Ultra-Wideband Transceiver Front-End for Low Power Applications A Baseband, Impulse Ultra-Wideband Transceiver Front-end for Low Power Applications Ian David O'Donnell Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-47 http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-47.html May 8, 2006 Copyright © 2006, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement This research was supported by the Office of Naval Research (Award No. N00014-00-1-0223), an Army Research Office MURI grant (#065861), and the industrial members of the Berkeley Wireless Research Center. The authors would like to thank Mike S. W. Chen for valuable discussions and assistance with the digital backend design, and Stanley B. T. Wang (U.C. Berkeley) for his work on the transmitter design and layout. A Baseband, Impulse Ultra-Wideband Transceiver Front-end for Low Power Applications by Ian David O’Donnell B.S. (University of California, Berkeley) 1993 M.S. (University of California, Berkeley) 1996 A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the GRADUATE DIVISION of the UNIVERSITY OF CALIFORNIA, BERKELEY Committee in charge: Professor Robert W. Brodersen, Chair Professor Kristofer S. J. Pister Professor Paul K. Wright Spring 2006 The dissertation of Ian David O’Donnell is approved: Chair Date Date Date University of California, Berkeley Spring 2006 A Baseband, Impulse Ultra-Wideband Transceiver Front-end for Low Power Applications Copyright 2006 by Ian David O’Donnell 1 Abstract A Baseband, Impulse Ultra-Wideband Transceiver Front-end for Low Power Applications by Ian David O’Donnell Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Robert W. Brodersen, Chair Interest in indoor wireless communications has been increasing. In addition to high through- put WLAN systems such as 802.11a/b/g/n, attention is also being focused on lower rate, short distance systems such as Bluetooth and Zigbee. These low rate radios are being proposed for a variety of applications including automation/security, smart toys, remote sensing/control, asset tracking, and as a replacement for computer peripheral wires. While not demanding aggressive throughput, these radios do require low cost, power efficient oper- ation and optionally the ability to perform ranging. Unfortunately, currently reported radios are up to an order of magnitude away from these power and cost targets or do not support ranging. However, a recent ruling from the FCC has opened up nearly 8GHz of unlicensed spectrum (from dc to 960MHz and from 3.1GHz to 10.6GHz) for ultra-wideband (UWB) deployment. One attractive method of UWB signaling that seems suited to a low power, highly integrated implementation communicates with short pulses, on the order of a nanosec- ond, that spread energy over at least 500MHz of bandwidth. Termed “impulse-UWB,” the baseband nature of this signaling promises low cost and low power consumption through design simplicity, pulsed (or “duty-cycled”) operation, and a “mostly-digital” implemen- tation. The benefits of this approach are balanced by the risk of jamming from in-band interference, of stricter sampling and gain constraints, and of increased digital complexity. This dissertation presents the system exploration, specification, design, and demonstration of a low power, highly integrated, flexible, baseband, impulse ultra-wideband transceiver front-end. Comprising a 1-bit, 1.92Gsample/s ADC, 50Ω input matched gain stage with 2 0dB to 42dB of variable gain, programmable control logic, a sub-1P P M trimmable 60MHz third-harmonic oscillator, and pulse transmitter, this front-end was implemented in a stan- dard digital 0.13µm CMOS process in 2.52mm2 of active area. Aggressively designed at the circuit level for low power, the front-end gain and sampling are also duty-cycled be- tween pulses to further reduce power consumption, yielding 4mW (RX) and 2mW (TX) at 30Mpulse/s, and 0.6mW (RX) and 0.4mW (TX) at 1Mpulse/s. Communication rates on the order of 1Mbps are supported over short distances and ranging is possible through time-of-flight measurements. Professor Robert W. Brodersen Dissertation Committee Chair i Dedicated to my family and friends who supported me during this undertaking. ii Contents List of Figures iv List of Tables viii Acknowledgments ix 1 Introduction 1 1.1 Motivation .................................... 1 1.2 Existing low power radios: Narrowband . ..... 2 1.3 Alternate Modulation: Ultra-Wideband (UWB) . ....... 10 1.4 ExistingUWBradios............................... 12 1.5 UWBRegulationsandStandards . 15 1.5.1 FCCRegulations............................. 16 1.5.2 802.15.3a and 802.15.4a . 18 1.6 Opportunity.................................... 19 1.7 OutlineofDissertation. 21 2 System 23 2.1 PulseGeneration ................................. 25 2.2 Antennas ..................................... 26 2.3 Interference .................................... 30 2.4 TheUWBChannel................................ 37 2.5 ReceiveSignalProcessing . 39 2.5.1 Acquisitionvs.Area ........................... 42 2.6 LinkBudget.................................... 43 2.7 SystemSimulation ................................ 46 2.8 SimulationConclusions . 51 2.8.1 ADCPrecision .............................. 51 2.8.2 TemplateFilter.............................. 58 2.8.3 NoiseFigure ............................... 61 2.8.4 Modulation ................................ 63 2.9 SamplingClockRequirements. 65 2.9.1 Jitter ................................... 65 2.9.2 FrequencyMismatch ........................... 67 CONTENTS iii 2.10 GainRangeandOffset.............................. 69 2.11Filtering...................................... 71 2.12 SystemArchitecture . 77 3 Circuit 80 3.1 ReceiverGainStages.............................. 81 3.1.1 TransimpedanceAmplifier. 87 3.1.2 Intermediate Gain Stages . 96 3.1.3 ADCBuffer................................ 99 3.1.4 Offsettrim ................................ 104 3.1.5 Debug/Observability . 111 3.1.6 Bias .................................... 115 3.2 Oscillator ..................................... 120 3.2.1 Oscillator to Clock Conversion . 125 3.3 DelayLockedLoop................................ 129 3.3.1 DelayCell................................. 131 3.3.2 PhaseDetector .............................. 138 3.3.3 ChargePumpandLoopFilter . 139 3.3.4 Measurements .............................. 142 3.4 Analog to Digital Converter . 150 3.4.1 Sampler .................................. 152 3.4.2 Comparator................................ 155 3.4.3 ControlLogic............................... 160 3.4.4 Performance ............................... 166 3.4.5 Layout................................... 167 3.5 Digital....................................... 169 3.5.1 ControlBlocks .............................. 170 3.5.2 CustomStandardCellLogic . 187 3.5.3 ChipInterface .............................. 190 3.6 PulseGeneration ................................. 190 3.7 Berkeley Impulse Transceiver (BIT) . 191 4 Conclusion 197 4.1 TransceiverOperation . 197 4.1.1 LoopbackTest .............................. 198 4.1.2 TransmissionandReception. 199 4.1.3 PowerConsumption .. .. .. .. .. .. .. .. 205 4.2 ClosingRemarks ................................. 212 Bibliography 213 A BIT Register list 223 B BIT Testboard 242 C BIT Pinout 254 iv List of Figures 1.1 ReceiverPowervs. Throughput . 4 1.2 Comparison of Narrowband and “Mostly-Digital” Architectures....... 9 1.3 Narrowband vs. Ultra-Wideband in Time and Frequency . ....... 13 2.1 ImpulseSamplingOperation . 24 2.2 TransceiverSystemModel . 25 2.3 ExamplePulsesinTimeandFrequency . 27 2.4 MeasuredInterferencePSD(TEMHorn). 34 2.5 Measured Interference in Time: Max. and Min. (TEM Horn) . ....... 35 2.6 Measured Interference PSD (440MHz/880MHz Stub)............ 36 2.7 Proposed Digital Backend Architecture . ....... 41 2.8 Worst-Case Acquisition Time vs. Area . ..... 44 2.9 Throughput vs. Pulse Rate for Simple Link Budget. ....... 47 2.10 SNIRvs.ADCBitwidth. .. .. .. .. .. .. .. .. 53 2.11 Probability of Error: Predicted vs. Time Domain Simulation . 54 2.12 SNIR vs. Template Filter Bit Width (ADC Bitwidth=1) . ........ 59 2.13 Probability of Error: Predicted vs. Time Domain Simulation . 60 2.14 Template Filter Length and Bitwidth vs. Area . ....... 62 2.15 Allowable Phase Noise for 75ps Std. Dev. Jitter Over One Symbol . .. 66 2.16 Allowable Mismatch for 100ps Drift over One Symbol . ........ 68 2.17 Single Pole Notch Filter Impedance . ...... 72 2.18 Simple Pole Filtering vs. Butterworth for Various Orders .......... 74 2.19 Simple Pole With Const. 3dB BW vs. Butterworth for VariousOrders . 75 2.20 Proposed Analog Front-end Architecture . ........ 79 3.1 Block-Level Sampling Operation . 81 3.2 Single-Ended Gain Stage Diagram . 82 3.3 GainStageS-Parameters . 84 3.4 NoiseFigureforGainStages . 85 3.5 Gain Stage S21 vs. Gain from Noise Figure Meter . ..... 86 3.6 Transimpedance Amplifier Topologies . ..... 88 3.7 TransimpedanceAmplifierCircuit . 89 3.8 Transimpedance
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