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Clustered VLIW Architectures : a Quantitative Approach Clustered VLIW architectures : a quantitative approach Citation for published version (APA): Terechko, A. S. (2007). Clustered VLIW architectures : a quantitative approach. Technische Universiteit Eindhoven. https://doi.org/10.6100/IR617141 DOI: 10.6100/IR617141 Document status and date: Published: 01/01/2007 Document Version: Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: [email protected] providing details and we will investigate your claim. Download date: 01. Oct. 2021 Clustered VLIW Architectures: a Quantitative Approach Andrei Sergeevich Terechko Doctorate committee: prof.dr.ir. A.C.P.M. Backx Technical University Eindhoven, chairman prof.dr. H. Corporaal Technical University Eindhoven, Netherlands dr.ir. J.T.J. van Eijndhoven NXP Semiconductors, Netherlands prof.dr. A. González Intel and Universitat Politècnica de Catalunya, Spain prof.dr.ir. J.L. van Meerbergen Royal Philips Electronics, Netherlands prof.dr.ir. R.H.J.M. Otten Technical University Eindhoven, Netherlands dr.ir. P. Stravers NXP Semiconductors, Netherlands The cover design by Henny Herps, Floris van den Haar, and Andrei Terechko. The front cover shows a layout of a tiny synchronous digital IC with 24 standard cell gates and 26 nets in the Philips CMOS 65 nm standard Vth technology. The reader is challenged to guess the ASCII string with an extra proposition of this PhD thesis that this IC generates on the 8 out- put pins. Note that the clock and reset are not shown to simplify the fig- ure; the colors for polysilicon, diffusion, etc. are non-standard; metal vias are not visible. The reverse engineering associated with this chal- lenge is a “walk in the park” compared to what Soviet Union engineers did in the 1980s to clone DEC and Intel processors with thousands of gates. If no solution is found before 06 May 2007, I will publish hints to the solution on http://terechko.net/andrei/phd. Clustered VLIW Architectures: a Quantitative Approach PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de Rector Magnificus, prof.dr.ir. C.J. van Duijn, voor een commissie aangewezen door het College voor Promoties in het openbaar te verdedigen op dinsdag 6 februari 2007 om 16.00 uur door Andrei Sergeevich Terechko geboren te Minsk, Wit-Rusland Dit proefschrift is goedgekeurd door de promotoren: prof.dr. H. Corporaal en prof.dr.ir. R.H.J.M. Otten Copromotor: dr.ir. P. Stravers CIP-DATA LIBRARY TECHNISCHE UNIVERSITEIT EINDHOVEN Terechko, Andrei S. Clustered VLIW architectures : a quantitative approach / by Andrei Sergeevich Terechko. – Eindhoven : Technische Universiteit Eindhoven, 2007. Proefschrift. – ISBN-10: 90-386-1953-7 ISBN-13: 978-90-386-1953-8 NUR 959 Trefw.: ingebedde systemen / computerontwerp ; microprocessoren / compilers / multimedia. Subject headings: embedded systems / computer architecture / program compilers / multimedia systems. The work described in this thesis has been carried out at the Philips Research Laboratories Eindhoven and NXP Semiconductors as part of the Research pro- gram. © NXP Semiconductors 2007 All rights reserved. Reproduction or dissemination in whole or in part is prohibited without the prior written consent of the copyright holder. Acknowledgments According to T. Kuhn's “The Structure of Scientific Revolutions” a scientific work can be successfully carried out only through intensive interactions among the members of a scientific community. First, I'm deeply grateful to my PhD su- pervisor Professor Henk Corporaal. Henk's mighty creativity and dedication to Science continuously inspired and motivated me in my winding quest for under- standing processor architecture. Furthermore, sheer and extravagant ingenuity of Paul Stravers hugely influenced my scientific and cultural existence. No doubt I'll be writing more open-source code, reading Maarten Biesheuvel and listening to Jacques Brel thanks to Paul. I also like to acknowledge Professor Ralph Otten who helped me better understand technological aspects in my re- search. On top of that, I thank Erwan Le Thénaff, Manish Garg, and Evert-Jan Pol, who supported (and bore with) my first steps in our joint scientific publica- tions. My life got a surrealistic kick in 1999, when I moved from Belarus to The Netherlands accepting a research position at Philips Research laboratories in Eindhoven. Luckily, this step allowed me to submerge into a cutting-edge Com- puter Science community and to hang out with a mind-boggling international crowd. I'm deeply grateful to Jos van Eijndhoven, who not only withstood me for 6 years in the same office at Research, but also dedicated many vivid hours to brainstorming with me about processor architecture, neat programming and the intricate Dutch society. Furthermore, I would like to acknowledge the ele- gant programming style of Jan Hoogerbrugge, whose VLIW instruction sched- uler formed the basis for my quantitative exploration. I will always have great memories of Philips, especially, of my intense scientific and engineering argu- ments with the Indian genius of Jayram Nageswaran and the Dutch genius of Jan-Willem van de Waerdt; let alone the fun of being part of an international micro-society with Giovanni Nisato, Catherine Nisato, Natalino Busa, Enith Vlooswijk, Clara Otero-Perez, Eugenio Cantatore, Manvi Agarwal, Otto Stein- busch, Martijn Rutten, Orlando Moreira and the guitarist Mathias Lang. My very first scientific experience in 1995-1998 was guided by Professor Gen- nadiy Shpackovsky at the Belarusian State University, who introduced me to the most intellectual game invented by the human society – Science. Finally, I ac- knowledge the contribution of many (anonymous) people to the open-source software (GNU Linux, GNU emacs, Mediabench, Putty, OOo, sWiki, WP) and free resources (e.g. http://wikipedia.org) that I used for my research. My love goes to Masha, Polina, and my parents Sergei and Tamara Terechko. Andrei Terechko Eindhoven, The Netherlands, 2007 v vi Table of Contents ACKNOWLEDGMENTS.......................................................................................... V 1. INTRODUCTION.............................................................................................. 1 1.1. Embedded computing........................................................................................... 2 1.1.1. Embedded multimedia workload................................................................. 2 1.1.2. Instruction-Level Parallelism....................................................................... 5 1.1.3. Embedded multimedia System-on-a-Chip................................................... 7 1.2. Deep sub-micron VLSI technology trends......................................................... 10 1.2.1. Poor scalability of interconnect delay........................................................ 11 1.2.2. Power consumption constraints..................................................................12 1.3. Problem statement of the thesis.......................................................................... 14 1.4. Thesis organization............................................................................................. 15 2. ARCHITECTURE OF CLUSTERED PROCESSORS.................................................. 17 2.1. Unicluster VLIW processor architecture............................................................ 17 2.2. From the unicluster to a clustered architecture................................................... 19 2.3. Clustered microarchitecture................................................................................ 23 2.3.1. Inter-cluster communication networks.......................................................23 2.3.1.1. Networks with non-uniform latency..................................................25 2.3.2. Clustering memory hierarchy.....................................................................26 2.3.3. Control for clustered processors.................................................................29
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