2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing Shafiur Rahman Nael Abu-Ghazaleh Rajiv Gupta Computer Science and Engineering Computer Science and Engineering Computer Science and Engineering University of California, Riverside University of California, Riverside University of California, Riverside Riverside, USA Riverside, USA Riverside, USA
[email protected] [email protected] [email protected] Abstract—Graph processing workloads are memory intensive GraphLab [31], GraphX [16], PowerGraph [17], Galois [37], with irregular access patterns and large memory footprint result- Giraph [4], GraphChi [28], and Ligra [49]. ing in low data locality. Their popular software implementations Large scale graph processing introduces a number of chal- typically employ either Push or Pull style propagation of changes through the graph over multiple iterations that follow the Bulk lenges that limit performance on traditional computing systems. Synchronous Model. The performance of these algorithms on First, memory-intensive processing stresses the memory system. traditional computing systems is limited by random reads/writes Not only is the frequency of memory operations relative of vertex values, synchronization overheads, and additional over- to compute operations high, the memory footprints of the heads for tracking active sets of vertices or edges across iterations. graph computations are large. Standard techniques in modern In this paper, we present GraphPulse, a hardware framework for asynchronous graph processing with event-driven schedul- processors for tolerating high memory latency, such as caching ing that overcomes the performance limitations of software and prefetching, have limited impact because irregular graph frameworks. Event-driven computation model enables a parallel computations lack data locality.