A Unified Compiler Framework for Program Analysis, Optimization, and Automatic Vectorization with Chains of Recurrences

Total Page:16

File Type:pdf, Size:1020Kb

A Unified Compiler Framework for Program Analysis, Optimization, and Automatic Vectorization with Chains of Recurrences A UNIFIED COMPILER FRAMEWORK FOR PROGRAM ANALYSIS, OPTIMIZATION, AND AUTOMATIC VECTORIZATION WITH CHAINS OF RECURRENCES Name: Yixin Shou Department: Department of Computer Science Major Professor: Robert A. van Engelen Degree: Ph.D. Term Degree Awarded: Spring, 2009 In this dissertation I propose a unified compiler framework for program analysis, op- timization, and automatic vectorization with techniques based on the Chains of Recurrences (CR) algebra. The root theoretical foundations of the CR algebra and the CR# additions for program analysis, that I specifically developed for this dissertation research, are given. Based on the theory, I propose an extension of the Single Static Assignment (SSA) form, called the Inductive SSA form. The form associates inductive proofs with SSA variables to describe their inductive properties. The proofs are derived with algorithms based on the CR# theory. Inductive SSA provides an internal program representation that facilitates more effective loop analysis by a compiler. Based on the Inductive SSA form, I describe and evaluate a collection of compiler algorithms for program optimization at the SSA level. More specifically, Inductive SSA merges static SSA information with semantic recurrence information to describe the value progressions of loop-variant variables. I will show how Inductive SSA enables and/or enhances loop-variant variable analysis, improves dependence testing for loops, and how it can be effectively used by many classic compiler optimizations to improve compilation results. Inductive SSA is based on my theoretical work on extending the CR formalism by the CR# (CR-sharp) algebra and lattice to effectively represent the value sequences and value ranges of conditionally updated variables in loops. Using empirical results on SPEC benchmarks with GCC 4.1, I will show that the Inductive SSA form captures more recurrence relations compared to state-of-the-art induction variable recognition techniques. Because the CR# term rewriting system is complete (confluent and terminating), it can be used for congruence detection in programs at all optimization levels. The Inductive SSA program analysis is far less sensitive to syntactical code changes, due to the real semantic information it captures. As a result of the independence of code structure, the phase ordering problem, in which multiple optimizing transformations can be ordered based on their effect on enabling or disabling other transformations, is greatly alleviated with Inductive SSA for many traditional low-level and loop-level optimizations. The experimental results show that the effectiveness of loop-variant variable analysis, congruence detection, and loop optimizations can be significantly increased with Inductive SSA. For this dissertation research I also developed a math function library generator. Many computational tasks require repeated evaluation of functions over structured grids, such as plotting in a coordinate system, rendering of parametric objects in 2D and 3D, numerical grid generation, and signal processing. The library generator speeds up closed-form function evaluations over grids by vectorizing the CR forms of these functions. The approach is comparable to aggressive strength reduction and short-vector vectorization of the resulting CRs. Strength reduction of floating point operations is usually prevented in a compiler due to safety issues related to floating point roundoff. Auto-tuning of the library ensures safe floating point evaluation. Experiments show significantly improved execution of streaming SIMD extensions (SSE) and instruction-level parallelism (ILP) of math function evaluations. THE FLORIDA STATE UNIVERSITY COLLEGE OF ARTS AND SCIENCES A UNIFIED COMPILER FRAMEWORK FOR PROGRAM ANALYSIS, OPTIMIZATION, AND AUTOMATIC VECTORIZATION WITH CHAINS OF RECURRENCES By YIXIN SHOU A Dissertation submitted to the Department of Computer Science in partial fulfillment of the requirements for the degree of Ph.D. Degree Awarded: Spring Semester, 2009 The members of the Committee approve the Dissertation of Yixin Shou defended on April 8, 2009. Robert A. van Engelen Professor Directing Dissertation Gordon Erlebacher Outside Committee Member Kyle Gallivan Committee Member David Whalley Committee Member Xin Yuan Committee Member Approved: David Whalley, Chair Department of Computer Science Joseph Travis, Dean, College of Arts and Sciences The Office of Graduate Studies has verified and approved the above named committee members. ii The members of the Committee approve the Dissertation of Yixin Shou defended on April 8, 2009. Robert A. van Engelen Professor Directing Dissertation Gordon Erlebacher Outside Committee Member Kyle Gallivan Committee Member David Whalley Committee Member Xin Yuan Committee Member The Office of Graduate Studies has verified and approved the above named committee members. ii To my father iii ACKNOWLEDGEMENTS This dissertation would not have been possible without the support of many individuals. First of all, I would like to thank my advisor, Dr. Robert A. van Engelen, for his extensive support, patience and encouragement throughout my doctoral work. His insightful comments and guidance at every stage of this dissertation were essential for me to complete my research and has taught me innumerable lessons and insights on the working of research in general. I am also grateful to him for his great help with scientific writing and his careful reading, commenting and revising of the manuscript. I am also very grateful to my committee members, Dr. Gordon Erlebacher, Dr. Kyle Gallivan, Dr. David Whalley and Dr. Xin Yuan, for their guidance and support through my graduate studies and for their insightful comments on my dissertation research. I would also like to thank all of the group members of ACIS laboratory at FSU for all the support and help I have received. Especially I would like to thank Johnnie Birch for many valuable and interesting discussions and his collaboration and help in integrating CR library into the experimental compiler. Last but not least, I would like to thank my family members who have been a constant source of love, support and strength. I would like to thank my parents with my deepest gratitude for their unconditional love and support all these years. I am grateful to my husband Yunsong for his understanding and love during these past years. His understanding and encouragement made it possible to complete this study. iv TABLE OF CONTENTS List of Tables...................................... vii List of Figures..................................... viii Abstract........................................ xii 1. INTRODUCTION.................................1 1.1 Motivation..................................1 1.2 The Inductive SSA Concept......................... 12 1.3 Automatic SIMD Vectorization of Chains of Recurrences......... 15 1.4 Thesis Statement............................... 16 1.5 Dissertation Outline............................. 17 2. PRELIMINARIES AND RELATED WORK.................. 18 2.1 Static Single Assignment Form....................... 18 2.2 Induction Variable Analysis......................... 21 2.3 Classic Compiler Optimizations....................... 30 2.4 The Chains of Recurrences Formalism................... 42 3. THEORY...................................... 50 3.1 The CR# Chains of Recurrences Extension................ 50 3.2 Inductive SSA................................. 71 4. ALGORITHMS................................... 80 4.1 Inductive SSA Construction......................... 80 4.2 Compiler Analysis and Optimization with Inductive SSA......... 87 5. IMPLEMENTATION............................... 101 5.1 GNU Compiler Collection (GCC)...................... 101 5.2 Implementation of Inductive SSA Extension................ 103 5.3 Loop-variant Variable Analysis Implementation.............. 105 5.4 Enhanced GVN-PRE with Inductive SSA-based Optimizations...... 105 6. EXPERIMENTAL RESULTS........................... 106 6.1 SPEC CPU2000 Benchmarks........................ 106 6.2 Measuring the Inductive Proof Choice Set Sizes.............. 106 6.3 Results of Loop-Variant Variable Classification with Inductive SSA... 108 v 6.4 Results for Inductive SSA-based Optimizations.............. 112 6.5 Inductive SSA Impact Analysis on GVN-PRE............... 116 7. SIMD Vectorization of Chains of Recurrences.................. 123 7.1 Introduction.................................. 123 7.2 Vector Chains of Recurrences........................ 125 7.3 Results.................................... 136 7.4 Related Work................................. 149 8. CONCLUSION................................... 152 REFERENCES..................................... 154 BIOGRAPHICAL SKETCH............................. 163 vi LIST OF TABLES 2.1 Chains of Recurrences simplification rules.................... 48 2.2 Chains of Recurrences inverse simplification rules................ 49 3.1 CR# simplification rules.............................. 52 3.2 CR# inverse simplification rules......................... 53 6.1 The SPEC CPU2000 benchmark suite...................... 107 6.2 Measuring the sizes of choice sets in Inductive SSA on SPEC2000....... 108 6.3 Results of loop-variant variable classification with Inductive SSA on SPEC2000.109 6.4 Inductive SSA classification of conditional loop-variant variables in SPEC2000.110 6.5 Number of additional equivalences and loop-invariants detected by Inductive SSA enhancement of GVN-PRE for SPEC CPU2000 benchmarks using GCC 4.1 -O3. Note: − indicates no difference....................
Recommended publications
  • Redundancy Elimination Common Subexpression Elimination
    Redundancy Elimination Aim: Eliminate redundant operations in dynamic execution Why occur? Loop-invariant code: Ex: constant assignment in loop Same expression computed Ex: addressing Value numbering is an example Requires dataflow analysis Other optimizations: Constant subexpression elimination Loop-invariant code motion Partial redundancy elimination Common Subexpression Elimination Replace recomputation of expression by use of temp which holds value Ex. (s1) y := a + b Ex. (s1) temp := a + b (s1') y := temp (s2) z := a + b (s2) z := temp Illegal? How different from value numbering? Ex. (s1) read(i) (s2) j := i + 1 (s3) k := i i + 1, k+1 (s4) l := k + 1 no cse, same value number Why need temp? Local and Global ¡ Local CSE (BB) Ex. (s1) c := a + b (s1) t1 := a + b (s2) d := m&n (s1') c := t1 (s3) e := a + b (s2) d := m&n (s4) m := 5 (s5) if( m&n) ... (s3) e := t1 (s4) m := 5 (s5) if( m&n) ... 5 instr, 4 ops, 7 vars 6 instr, 3 ops, 8 vars Always better? Method: keep track of expressions computed in block whose operands have not changed value CSE Hash Table (+, a, b) (&,m, n) Global CSE example i := j i := j a := 4*i t := 4*i i := i + 1 i := i + 1 b := 4*i t := 4*i b := t c := 4*i c := t Assumes b is used later ¡ Global CSE An expression e is available at entry to B if on every path p from Entry to B, there is an evaluation of e at B' on p whose values are not redefined between B' and B.
    [Show full text]
  • Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism*
    Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism* David A. Berson 1 Pohua Chang 1 Rajiv Gupta 2 Mary Lou Sofia2 1 Intel Corporation, Santa Clara, CA 95052 2 University of Pittsburgh, Pittsburgh, PA 15260 Abstract. Code optimizations and restructuring transformations are typically applied before scheduling to improve the quality of generated code. However, in some cases, the optimizations and transformations do not lead to a better schedule or may even adversely affect the schedule. In particular, optimizations for redundancy elimination and restructuring transformations for increasing parallelism axe often accompanied with an increase in register pressure. Therefore their application in situations where register pressure is already too high may result in the generation of additional spill code. In this paper we present an integrated approach to scheduling that enables the selective application of optimizations and restructuring transformations by the scheduler when it determines their application to be beneficial. The integration is necessary because infor- mation that is used to determine the effects of optimizations and trans- formations on the schedule is only available during instruction schedul- ing. Our integrated scheduling approach is applicable to various types of global scheduling techniques; in this paper we present an integrated algorithm for scheduling superblocks. 1 Introduction Compilers for multiple-issue architectures, such as superscalax and very long instruction word (VLIW) architectures, axe typically divided into phases, with code optimizations, scheduling and register allocation being the latter phases. The importance of integrating these latter phases is growing with the recognition that the quality of code produced for parallel systems can be greatly improved through the sharing of information.
    [Show full text]
  • Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files ?
    Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files ? Chung-Ju Wu Sheng-Yuan Chen Jenq-Kuen Lee Department of Computer Science National Tsing-Hua University Hsinchu 300, Taiwan Email: {jasonwu, sychen, jklee}@pllab.cs.nthu.edu.tw Abstract. High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and mul- timedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register archi- tectures are being adopted to eliminate the amount of read/write ports in register files. This presents new challenges for devising compiler op- timization schemes for such architectures. In our research work, we ad- dress the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files. We show how to support an important class of compiler optimization problems, known as copy propagations, for such architecture. We illustrate that a naive deployment of copy propagations in embedded VLIW DSP processors with distributed register files might result in performance anomaly. In our proposed scheme, we derive a communication cost model by clus- ter distance, register port pressures, and the movement type of register sets. This cost model is used to guide the data flow analysis for sup- porting copy propagations over PAC architecture. Experimental results show that our schemes are effective to prevent performance anomaly with copy propagations over embedded VLIW DSP processors with dis- tributed files. 1 Introduction Digital signal processors (DSPs) have been found widely used in an increasing number of computationally intensive applications in the fields such as mobile systems.
    [Show full text]
  • Garbage Collection
    Topic 10: Dataflow Analysis COS 320 Compiling Techniques Princeton University Spring 2016 Lennart Beringer 1 Analysis and Transformation analysis spans multiple procedures single-procedure-analysis: intra-procedural Dataflow Analysis Motivation Dataflow Analysis Motivation r2 r3 r4 Assuming only r5 is live-out at instruction 4... Dataflow Analysis Iterative Dataflow Analysis Framework Definitions Iterative Dataflow Analysis Framework Definitions for Liveness Analysis Definitions for Liveness Analysis Remember generic equations: -- r1 r1 r2 r2, r3 r3 r2 r1 r1 -- r3 -- -- Smart ordering: visit nodes in reverse order of execution. -- r1 r1 r2 r2, r3 r3 r2 r1 r3, r1 ? r1 -- r3 r3, r1 r3 -- -- r3 Smart ordering: visit nodes in reverse order of execution. -- r1 r3, r1 r3 r1 r2 r3, r2 r3, r1 r2, r3 r3 r3, r2 r3, r2 r2 r1 r3, r1 r3, r2 ? r1 -- r3 r3, r1 r3 -- -- r3 Smart ordering: visit nodes in reverse order of execution. -- r1 r3, r1 r3 r1 r2 r3, r2 r3, r1 : r2, r3 r3 r3, r2 r3, r2 r2 r1 r3, r1 r3, r2 : r1 -- r3 r3, r1 r3, r1 r3 -- -- r3 -- r3 Smart ordering: visit nodes in reverse order of execution. Live Variable Application 1: Register Allocation Interference Graph r1 r3 ? r2 Interference Graph r1 r3 r2 Live Variable Application 2: Dead Code Elimination of the form of the form Live Variable Application 2: Dead Code Elimination of the form This may lead to further optimization opportunities, as uses of variables in s of the form disappear. repeat all / some analysis / optimization passes! Reaching Definition Analysis Reaching Definition Analysis (details on next slide) Reaching definitions: definition-ID’s 1.
    [Show full text]
  • Phase-Ordering in Optimizing Compilers
    Phase-ordering in optimizing compilers Matthieu Qu´eva Kongens Lyngby 2007 IMM-MSC-2007-71 Technical University of Denmark Informatics and Mathematical Modelling Building 321, DK-2800 Kongens Lyngby, Denmark Phone +45 45253351, Fax +45 45882673 [email protected] www.imm.dtu.dk Summary The “quality” of code generated by compilers largely depends on the analyses and optimizations applied to the code during the compilation process. While modern compilers could choose from a plethora of optimizations and analyses, in current compilers the order of these pairs of analyses/transformations is fixed once and for all by the compiler developer. Of course there exist some flags that allow a marginal control of what is executed and how, but the most important source of information regarding what analyses/optimizations to run is ignored- the source code. Indeed, some optimizations might be better to be applied on some source code, while others would be preferable on another. A new compilation model is developed in this thesis by implementing a Phase Manager. This Phase Manager has a set of analyses/transformations available, and can rank the different possible optimizations according to the current state of the intermediate representation. Based on this ranking, the Phase Manager can decide which phase should be run next. Such a Phase Manager has been implemented for a compiler for a simple imper- ative language, the while language, which includes several Data-Flow analyses. The new approach consists in calculating coefficients, called metrics, after each optimization phase. These metrics are used to evaluate where the transforma- tions will be applicable, and are used by the Phase Manager to rank the phases.
    [Show full text]
  • Using Program Analysis for Optimization
    Analysis and Optimizations • Program Analysis – Discovers properties of a program Using Program Analysis • Optimizations – Use analysis results to transform program for Optimization – Goal: improve some aspect of program • numbfber of execute diid instructions, num bflber of cycles • cache hit rate • memory space (d(code or data ) • power consumption – Has to be safe: Keep the semantics of the program Control Flow Graph Control Flow Graph entry int add(n, k) { • Nodes represent computation s = 0; a = 4; i = 0; – Each node is a Basic Block if (k == 0) b = 1; s = 0; a = 4; i = 0; k == 0 – Basic Block is a sequence of instructions with else b = 2; • No branches out of middle of basic block while (i < n) { b = 1; b = 2; • No branches into middle of basic block s = s + a*b; • Basic blocks should be maximal ii+1;i = i + 1; i < n } – Execution of basic block starts with first instruction return s; s = s + a*b; – Includes all instructions in basic block return s } i = i + 1; • Edges represent control flow Two Kinds of Variables Basic Block Optimizations • Temporaries introduced by the compiler • Common Sub- • Copy Propagation – Transfer values only within basic block Expression Elimination – a = x+y; b = a; c = b+z; – Introduced as part of instruction flattening – a = (x+y)+z; b = x+y; – a = x+y; b = a; c = a+z; – Introduced by optimizations/transformations – t = x+y; a = t+z;;; b = t; • Program variables • Constant Propagation • Dead Code Elimination – x = 5; b = x+y; – Decldiiillared in original program – a = x+y; b = a; c = a+z; – x = 5; b
    [Show full text]
  • CSE 401/M501 – Compilers
    CSE 401/M501 – Compilers Dataflow Analysis Hal Perkins Autumn 2018 UW CSE 401/M501 Autumn 2018 O-1 Agenda • Dataflow analysis: a framework and algorithm for many common compiler analyses • Initial example: dataflow analysis for common subexpression elimination • Other analysis problems that work in the same framework • Some of these are the same optimizations we’ve seen, but more formally and with details UW CSE 401/M501 Autumn 2018 O-2 Common Subexpression Elimination • Goal: use dataflow analysis to A find common subexpressions m = a + b n = a + b • Idea: calculate available expressions at beginning of B C p = c + d q = a + b each basic block r = c + d r = c + d • Avoid re-evaluation of an D E available expression – use a e = b + 18 e = a + 17 copy operation s = a + b t = c + d u = e + f u = e + f – Simple inside a single block; more complex dataflow analysis used F across bocks v = a + b w = c + d x = e + f G y = a + b z = c + d UW CSE 401/M501 Autumn 2018 O-3 “Available” and Other Terms • An expression e is defined at point p in the CFG if its value a+b is computed at p defined t1 = a + b – Sometimes called definition site ... • An expression e is killed at point p if one of its operands a+b is defined at p available t10 = a + b – Sometimes called kill site … • An expression e is available at point p if every path a+b leading to p contains a prior killed b = 7 definition of e and e is not … killed between that definition and p UW CSE 401/M501 Autumn 2018 O-4 Available Expression Sets • To compute available expressions, for each block
    [Show full text]
  • Machine Independent Code Optimizations
    Machine Independent Code Optimizations Useless Code and Redundant Expression Elimination cs5363 1 Code Optimization Source IR IR Target Front end optimizer Back end program (Mid end) program compiler The goal of code optimization is to Discover program run-time behavior at compile time Use the information to improve generated code Speed up runtime execution of compiled code Reduce the size of compiled code Correctness (safety) Optimizations must preserve the meaning of the input code Profitability Optimizations must improve code quality cs5363 2 Applying Optimizations Most optimizations are separated into two phases Program analysis: discover opportunity and prove safety Program transformation: rewrite code to improve quality The input code may benefit from many optimizations Every optimization acts as a filtering pass that translate one IR into another IR for further optimization Compilers Select a set of optimizations to implement Decide orders of applying implemented optimizations The safety of optimizations depends on results of program analysis Optimizations often interact with each other and need to be combined in specific ways Some optimizations may need to applied multiple times . E.g., dead code elimination, redundancy elimination, copy folding Implement predetermined passes of optimizations cs5363 3 Scalar Compiler Optimizations Machine independent optimizations Enable other transformations Procedure inlining, cloning, loop unrolling Eliminate redundancy Redundant expression elimination Eliminate useless
    [Show full text]
  • Code Improvement:Thephasesof Compilation Devoted to Generating Good Code
    Code17 Improvement In Chapter 15 we discussed the generation, assembly, and linking of target code in the middle and back end of a compiler. The techniques we presented led to correct but highly suboptimal code: there were many redundant computations, and inefficient use of the registers, multiple functional units, and cache of a mod- ern microprocessor. This chapter takes a look at code improvement:thephasesof compilation devoted to generating good code. For the most part we will interpret “good” to mean fast. In a few cases we will also consider program transforma- tions that decrease memory requirements. On occasion a real compiler may try to minimize power consumption, dollar cost of execution under a particular ac- counting system, or demand for some other resource; we will not consider these issues here. There are several possible levels of “aggressiveness” in code improvement. In a very simple compiler, or in a “nonoptimizing” run of a more sophisticated com- piler, we can use a peephole optimizer to peruse already-generated target code for obviously suboptimal sequences of adjacent instructions. At a slightly higher level, typical of the baseline behavior of production-quality compilers, we can generate near-optimal code for basic blocks. As described in Chapter 15, a basic block is a maximal-length sequence of instructions that will always execute in its entirety (assuming it executes at all). In the absence of delayed branches, each ba- sic block in assembly language or machine code begins with the target of a branch or with the instruction after a conditional branch, and ends with a branch or with the instruction before the target of a branch.
    [Show full text]
  • Abstract Interpretations, 14 Access Expressions, 137 Access Graph
    Index abstract interpretations, 14 φ placement, 196 access expressions, 137 dominance frontier, 194 access graph, 141 renaming, 199 empty, 141 SSA destruction, 214 operations, 143–146 register allocation, 224 cleanUp, 143 alias analysis, 129–135 CN, 143 data flow equations, 134 extension, 145 of parameters, 268 factorization, 145 data flow equations, 269–271 field, 143 alias relations, 129 lastNode, 143 aliasing makeGraph, 143 data flow equations, 134 path removal, 145 direct aliases, 131 root, 143 indirect aliases, 131 safety of, 146 link aliases, 130 union, 144 node aliases, 130 summarization, 142 of access paths, 3, 9 access path, 3, 137 of parameters, 267 aliasing of, 3 of pointers, 2, 129–135 base of, 137 all paths analysis, 33 directly generated, 139 anti-symmetric, 64 frontier of, 137 anticipable expressions analysis, 37–39 killed, 139 data flow equations, 38 liveness of, 3 any path analysis, 26 simple, 137 applications of data flow analysis, 16 summarization, 3, 12 assignment, 176, 177, 181 target of, 137 maximum fixed point (MFP), 77 transfer of, 139 maximum safe, 75 algorithm meet over paths (MOP), 75 DFST construction, 60 associativity, 66 elimination, 184 available expressions analysis, 33–35 iterative common subexpressions elimination, round-robin, 4, 19, 79, 90, 163– 34 164 data flow equations, 33 work list, 165–172,312, 319, 320, 322 backward data flow problem, 26 SSA construction backward edges, 61 379 380 Index backward flow, 24, 160 termination length, 328 basic block, 23 termination, issues in, 305–310 bidirectional data flow equations,
    [Show full text]
  • Compiler Construction
    Compiler construction PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 10 Dec 2011 02:23:02 UTC Contents Articles Introduction 1 Compiler construction 1 Compiler 2 Interpreter 10 History of compiler writing 14 Lexical analysis 22 Lexical analysis 22 Regular expression 26 Regular expression examples 37 Finite-state machine 41 Preprocessor 51 Syntactic analysis 54 Parsing 54 Lookahead 58 Symbol table 61 Abstract syntax 63 Abstract syntax tree 64 Context-free grammar 65 Terminal and nonterminal symbols 77 Left recursion 79 Backus–Naur Form 83 Extended Backus–Naur Form 86 TBNF 91 Top-down parsing 91 Recursive descent parser 93 Tail recursive parser 98 Parsing expression grammar 100 LL parser 106 LR parser 114 Parsing table 123 Simple LR parser 125 Canonical LR parser 127 GLR parser 129 LALR parser 130 Recursive ascent parser 133 Parser combinator 140 Bottom-up parsing 143 Chomsky normal form 148 CYK algorithm 150 Simple precedence grammar 153 Simple precedence parser 154 Operator-precedence grammar 156 Operator-precedence parser 159 Shunting-yard algorithm 163 Chart parser 173 Earley parser 174 The lexer hack 178 Scannerless parsing 180 Semantic analysis 182 Attribute grammar 182 L-attributed grammar 184 LR-attributed grammar 185 S-attributed grammar 185 ECLR-attributed grammar 186 Intermediate language 186 Control flow graph 188 Basic block 190 Call graph 192 Data-flow analysis 195 Use-define chain 201 Live variable analysis 204 Reaching definition 206 Three address
    [Show full text]
  • Optimization.Pdf
    1. statement-by-statement code generation 2. peephole optimization 3. “global” optimization 0-0 Peephole optimization Peephole: a short sequence of target instructions that may be replaced by a shorter/faster sequence One optimization may make further optimizations possible ) several passes may be required 1. Redundant load/store elimination: 9.9 MOV R0 a MOV a R0 delete if in same B.B. 2. Algebraic simplification: eliminate instructions like the Section following: x = x + 0 x = x * 1 3. Strength reduction: replace expensive operations by equivalent cheaper operations, e.g. x2 ! x * x fixed-point multiplication/division by power of 2 ! shift Compiler Construction: Code Optimization – p. 1/35 Peephole optimization 4. Jumps: goto L1 if a < b goto L1 ... ... L1: goto L2 L1: goto L2 + + goto L2 if a < b goto L2 ... ... L1: goto L2 L1: goto L2 If there are no other jumps to L1, and it is preceded by an unconditional jump, it may be eliminated. If there is only jump to L1 and it is preceded by an unconditional goto goto L1 if a < b goto L2 ... goto L3 L1: if a < b goto L2 ) ... L3: L3: Compiler Construction: Code Optimization – p. 2/35 Peephole optimization 5. Unreachable code: unlabeled instruction following an unconditional jump may be eliminated #define DEBUG 0 if debug = 1 goto L1 ... goto L2 if (debug) { ) L1: /* print */ /* print stmts */ L2: } + if 0 != 1 goto L2 if debug != 1 goto L2 /* print stmts */ ( /* print stmts */ L2: L2: eliminate Compiler Construction: Code Optimization – p. 3/35 Example i = m-1; j = n; v = a[n]; while (1) { do i = i+1; while (a[i] < v); do j = j-1; while (a[j] > v); if (i >= j) break; x = a[i]; a[i] = a[j]; a[j] = x; } 10.1 x = a[i]; a[i] = a[n]; a[n] = x; Section Compiler Construction: Code Optimization – p.
    [Show full text]