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Intel Opensource HD Graphics Programmer's Reference Manual Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 2 Part 1: 3D/Media – 3D Pipeline (SandyBridge) For the 2011 Intel Core Processor Family May 2011 Revision 1.0 NOTICE: This document contains information on products in the design phase of development, and Intel reserves the right to add or remove product features at any time, with or without changes to this open source documentation. Doc Ref #: IHD-OS-V2 Pt1 – 05 11 Creative Commons License You are free to Share — to copy, distribute, display, and perform the work Under the following conditions: Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any way that suggests that they endorse you or your use of the work). No Derivative Works. You may not alter, transform, or build upon this work. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The SandyBridge chipset family, Havendale/Auburndale chipset family, Intel® 965 Express Chipset Family, Intel® G35 Express Chipset, and Intel® 965GMx Chipset Mobile Family Graphics Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel® sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel®. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2011, Intel Corporation. All rights reserved. 2 Doc Ref #: IHD-OS-V2 Pt1 – 05 11 Contents 1. 3D Pipeline ............................................................................................................................................. 7 1.1 Introduction .......................................................................................................................................... 7 1.2 3D Pipeline Overview........................................................................................................................... 7 1.2.1 3D Pipeline Stages......................................................................................................................... 8 1.3 3D Primitives Overview........................................................................................................................ 8 1.4 3D Pipeline State Overview ............................................................................................................... 17 1.4.1 3D State Model............................................................................................................................. 17 1.4.2 3DSTATE_CC_STATE_POINTERS [DevSNB]........................................................................... 18 1.4.3 3DSTATE_BINDING_TABLE_POINTERS .................................................................................. 20 1.4.4 3DSTATE_SAMPLER_STATE_POINTERS [DevSNB]............................................................... 22 1.4.5 3DSTATE_VIEWPORT_STATE_POINTERS [DevSNB+]........................................................... 24 1.4.6 3DSTATE_SCISSOR_STATE_POINTERS [DevSNB+].............................................................. 26 1.4.7 3DSTATE_URB [DevSNB]...........................................................................................................27 1.4.8 Gather Constants ......................................................................................................................... 29 1.5 Vertex Data Overview ........................................................................................................................ 29 1.5.1 Vertex URB Entry (VUE) Formats................................................................................................ 30 1.5.2 Vertex Positions ........................................................................................................................... 39 1.6 3D Pipeline Stage Overview .............................................................................................................. 41 1.6.1 Generic 3D FF Unit Block Diagram.............................................................................................. 41 1.6.2 Common 3D FF Unit Functions....................................................................................................42 1.6.3 Thread Initiation Management ..................................................................................................... 44 1.6.4 Thread Request Generation......................................................................................................... 47 1.6.5 Thread Output Handling............................................................................................................... 54 1.6.6 VUE Readback............................................................................................................................. 56 1.6.7 Statistics Gathering [DevSNB] ..................................................................................................... 56 1.7 Synchronization of the 3D Pipeline .................................................................................................... 59 1.7.1 Top-of-Pipe Synchronization........................................................................................................ 59 1.7.2 End-of-Pipe Synchronization........................................................................................................ 59 1.7.3 Synchronization Actions............................................................................................................... 59 1.7.4 PIPE_CONTROL Command........................................................................................................ 60 2. Vertex Fetch (VF) Stage...................................................................................................................... 74 2.1 Vertex Fetch (VF) Stage Overview .................................................................................................... 74 2.1.1 Input Assembly............................................................................................................................. 74 2.1.2 Vertex Cache................................................................................................................................ 75 2.1.3 Input Data: Push Model vs. Pull Model ....................................................................................... 75 2.1.4 Generated IDs.............................................................................................................................. 75 2.2 Index Buffer (IB) ................................................................................................................................. 76 2.2.1 3DSTATE_INDEX_BUFFER [DevSNB+]..................................................................................... 77 2.2.2 Index Buffer Access ..................................................................................................................... 81 2.3 Vertex Buffers (VBs) .......................................................................................................................... 82 2.3.1 3DSTATE_VERTEX_BUFFERS.................................................................................................. 82 2.3.2 VERTEX_BUFFER_STATE Structure ......................................................................................... 83 2.3.3 VERTEXDATA Buffers – SEQUENTIAL Access ......................................................................... 89 2.3.4 VERTEXDATA Buffers – RANDOM Access ................................................................................ 90 2.3.5 INSTANCEDATA Buffers ............................................................................................................. 91 2.4 Input Vertex Definition........................................................................................................................ 91 2.4.1 3DSTATE_VERTEX_ELEMENTS ............................................................................................... 91 2.4.2 VERTEX_ELEMENT_STATE Structure .....................................................................................
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