System for Exercise Analysis
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS 2013) Abu Dhabi, United Arab Emirates 8-11 December 2013 IEEE Catalog Number: CFP13773-POD ISBN: 978-1-4799-2453-0 TABLE OF CONTENTS Session A1L-A: Analog Circuits I Chair: Mourad Loulou, University of Sfax Time: December 9, 2013, 11:20 - 13:00 Location: Room 1 A 12 Gb/s Standard Cell based ECL 4:1 Serializer with Asynchronous Parallel Interface ................................................ 1 Oliver Schrape (IHP), Markus Appel (Humboldt University Berlin), Frank Winkler (Humboldt University Berlin), Miloš Krstić (IHP) A Pulse Width Controlled PLL and its Automated Design Flow ........................................................................................ 5 Norihito Tohge (University of Tokyo), Toru Nakura (University of Tokyo), Tetsuya Iizuka (University of Tokyo), Kunihiro Asada (University of Tokyo) A Wideband Unity-Gain Buffer in 0.13-µm CMOS .............................................................................................................. 9 Kamyar Keikhosravy (University of British Columbia), Pouya Kamalinejad (University of British Columbia), Shahriar Mirabbasi (University of British Columbia), Victor Leung (University of British Columbia) A 5-9 GHz CMOS Ultra-Wideband Power Ampilifier Design using Load-Pull ................................................................... 13 H. Mosalam (Egypt-Japan University of Science and Technology), A. Allam (Egypt-Japan University of Science and Technology), H. Jia (Kyushu University),
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