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BIST for Logic and Memory Resources in Virtex-4 Fpgas

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BIST for Logic and Memory Resources in Virtex-4 Fpgas BIST for Logic and Memory Resources in Virtex-4 FPGAs Sachin Dhingra, Daniel Milton, and Charles E. Stroud Dept. of Electrical and Computer Engineering 200 Broun Hall, Auburn University, AL 36849-5201 emails: dhingsa/miltoda/[email protected] ABSTRACT: We present a Built-In Self-Test (BIST) details of BIST configurations for specific logic and approach for testing and diagnosing the programmable memory resources including programmable logic blocks logic and memory resources in Xilinx Virtex-4 series (PLBs) and block RAMs are presented in Sections 4 and Field Programmable Gate Arrays (FPGAs). The re- 5, respectively. Experimental results are presented in sources under test include the programmable logic Section 6 and the paper is summarized in Section 7. blocks (PLBs) and block random access memories (RAMs) in all of their modes of operation. The BIST 2. OVERVIEW OF VIRTEX-4 ARCHITECTURE architecture and configurations needed to completely test these resources are presented. The BIST approach The Virtex-4 FPGA is easily the most complex FPGA offered by Xilinx to date. The general architecture is exploits architectural and operational features of the Virtex-4 FPGA to reduce the amount of storage required illustrated in Figure 1 and consists of columns of PLBs, for BIST configuration data as well as the total testing block RAMs, and DSPs [3]. The PLBs consist of four slices, each containing two 4-input look-up tables time required for testing the FPGA.1 (LUTs) and two flip-flops along with other specialized logic. The LUTs in two of the four slices can also func- 1. INTRODUCTION AND BACKGROUND tion as small RAMs or shift registers. The block RAMs Built-In Self-Test (BIST) of programmable logic and are 18K-bit dual-port RAMs programmable in a variety routing resources in Field Programmable Gate Arrays of modes of operation including first-in first-out (FIFO) (FPGAs) has been a topic of research and development and error correcting code (ECC) modes. The DSPs in- for the past decade [1]. The ability to reprogram an clude an 18×18-bit signed multiplier and a 48-bit ad- FPGA to test itself for fault detection in conjunction der/subtractor with registers for accumulator operations. with fault diagnosis provides the fundamental step for The number of rows and columns of PLBs, block fault-tolerant operation since the FPGA can be recon- RAMs, and DSPs varies with the size and family (LX, figured to avoid faulty resources. The primary barrier to SX, or FX) of Virtex-4 FPGAs. The ranges for the total practical application of this idea has been the large number of PLBs, block RAMs, and DSPs for the vari- number of BIST and diagnostic configurations required ous sizes of Virtex-4 FPGAs are included in the legend to achieve detection and identification of faulty re- in Figure 1. The array size for Virtex-4 tend to be large sources. This barrier is compounded by the time re- compared to previous FPGAs and these large arrays quired to download these configurations into the FPGA pose a number of challenges to BIST as will be dis- since the download time represents the major portion of cussed in the next section. Unlike the example shown the total testing time [1]. The problem is further con- in Figure 1, Virtex-4 arrays have more rows than col- founded by the increase in size and complexity of umns with an average ratio of about 2-to-1. FPGAs with the addition of specialized cores, including large random access memories (RAMs) and digital sig- nal processors (DSPs) [2]. In this paper, we present a case study of BIST for the Xilinx Virtex-4 series FPGA which exploits architec- tural and operational features of the FPGA for dynamic partial reconfiguration and configuration memory read- back for BIST and diagnosis of faulty resources based on the BIST results. We begin with a brief overview of the architectural features of the Virtex-4 series FPGAs = PLBs = block RAMs = DSPs (48 – 552) (32-512) in Section 2. This is followed by a discussion of the (1,536 – 22,272) BIST architecture and prior work in BIST for FPGAs, Figure 1. Basic Virtex-4 Architecture as it relates to this BIST architecture, in Section 3. The Virtex-4 supports frame addressable write and read ac- cess of the configuration memory [4]. This facilitates 1 This work was sponsored by the National Security Agency both dynamic partial reconfiguration of the FPGA via under contract H98230-04-C-1177. frame addressable write operations and partial configu- ration memory readback via frame addressable read edge of the array were monitored by only one ORA [1]. operations. An important new feature in the Virtex-4 is As a result, the diagnostic resolution was the lower the ability to write multiple frame addresses with the along the edges of the array, making unique diagnosis of same configuration data once the single frame of con- a set of faulty PLBs difficult and sometimes requiring figuration data has been written to the Frame Data Reg- additional BIST configurations. The MULTICELLO pro- ister. This multiple frame write feature helps to reduce cedure was later extended for use in on-line BIST and the total time required to reconfigure the FPGA; this is PLBs where a sequence of separate test structures with particularly important in the case of large FPGAs and two BUTs and one ORA resulted in a small circular useful in very regular-structured designs that repeat array of four BUTs and four ORAs when superimposed across the array (as is the case with our BIST approach). over time [5]. When the diagnostic procedure was ex- During configuration memory readback, the contents of tended for use when testing the block RAMs and multi- memory elements, including PLB flip-flops/latches and pliers in Virtex II, the circular comparison was found to RAMs as well as block RAMs, are also read with the provide an improvement in diagnostic resolution over contents of the configuration memory. The frames of that of the BIST architecture for which MULTICELLO the configuration memory are fixed in size and are ori- was originally developed since there are no edges where ented along the columns of the FPGA with each frame BUTs are observed by only one ORA [2]. associated with the equivalent of a column of 16 PLBs The contents of the ORA flip-flops are obtained via [4]. Furthermore, the 128 flip-flops for all 16 PLBs in partial configuration memory readback such that no the column are located in the same frame such that their additional logic is required to retrieve the BIST results. contents can be observed by reading a single frame. Retrieving BIST results via full configuration memory A final architectural feature is the ability to route all readback was originally used in BIST for Xilinx 4000 primary outputs of the PLB through the flip-flops. All series FPGAs [6] to avoid the need for additional logic of these architecture and operational features of the to form a shift register for scanning out ORA contents at Virtex-4 also play a major role in the architecture and the end of each BIST configuration [1]. Partial configu- operation of the BIST approach as will be discussed in ration memory readback was later used in [7] to reduce the subsequent sections. the time required to retrieve the contents of the ORAs and, in turn, the overall test time. As a result of the 3. BIST ARCHITECTURE Virtex-4 architecture and the use of partial configuration memory readback, one comparison-based ORA can be The basic BIST architecture is illustrated in Figure 2 implemented using a single LUT and flip-flop such that and is used for testing all programmable logic and two independent ORAs can be implemented in each memory resources in the Virtex-4 series FPGA includ- slice. This is illustrated in Figure 3 where each ORA ing PLBs, block RAMs, and DSPs. Multiple identically monitors one output from the BUT to the left and to the configured test pattern generators (TPGs) supply test right of the ORA. Therefore, the total number of slices patterns to identically configured blocks under test needed to implement ORAs, N , is given by: (BUTs) which can be PLBs, RAMs, or DSPs. The out- ORA puts of the BUTs are monitored by two output response NORA = N BUT × NOUT ÷ 2 (1) analyzers (ORAs) and compared with the outputs of two where NBUT is the total number of BUTs and NOUT is the different BUTs. This results in the circular comparison number of outputs per BUT. A single PLB can imple- based BIST architecture shown in Figure 2. ment a total of eight independent ORAs. This fine-grain ORA design also improves the diagnostic resolution by providing the ability to identify the faulty output of the BUT in addition to identifying the faulty BUT itself [2]. The ORAs are physically located in common columns = ORA = TPG of PLBs in the FPGA in order to minimize the number of frames that must be read when using partial configu- Figure 2. Basic BIST Architecture ration memory readback to obtain the BIST results. With the frame structure of the Virtex-4 and the fact that This circular comparison architecture was originally all flip-flops for a column of 16 PLBs are located in a developed for testing the 4K-bit block RAMs in Virtex I single frame, the total number of frames, NFRAME, that FPGAs as well as the 18K-bit block RAMs and 18×18- must be read to obtain the BIST results is given by: bit multipliers in Virtex II FPGAs [2].
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