Computer Architecture

Computer Communication Engineering 3rd Year

Al-Rafidain University College Introduction

A computer is a data processing machine which operates automatically under the control of a list of instructions (called a program) stored in its main memory. The architecture of a computer is the general layout of its major components, the principal features of these components and how they are connected together. Computer System Components

A computer system consists of four components:  The microprocessor (CPU)  Memory  Input units  Output units. All these components are connected together through a system bus. System Bus

System bus is a common group of wires that interconnect components in a computer system. In the microprocessor based computer system three buses exist for this transfer of information:  Address Bus.  Data Bus.  Control Bus. Input Unit Output Unit

Address Bus

CPU Data Bus

Control Bus

ROM RAM The Data Bus: transfers information between the microprocessor and its memory and I/O address space. Data transfers vary in size from 8-bit wide to 64-bit wide. The Data Bus is Bidirectional. speed in applications that use wide data. For example, if a 32-bit number is stored in memory, it takes the 8088 microprocessor 4 transfer operations to complete because its data bus is only 8-bit wide. The 80486 accomplishes the same task with 1 transfer because its data bus is 32-bit wide. Microprocessor Data Bus Address Bus Memory Size Width Width

8086 16 20 1 M 8088 8 20 1 M 80286 16 24 16 M 80386DX 32 32 4 G 80486DX 32 32 4 G Pentium I 64 32 4 G Pentium Pro 64 36 64 G

Table 1.1. The Intel family of microprocessor bus and memory sizes contains lines that select the memory or I/O and cause them to perform a read or write operation.

Control Signals Bus Cycle type IO/M RD/WR 0 1 Memory Read Memory Cycle 0 0 Memory Write 1 1 IO Read IO Cycle 1 0 IO Write

Table 1. 2. Control Signals used to specify bus cycle types. Main CPU Components

Any CPU must contain:

The ALU is the section of the processor that is involved with executing arithmetic or logical operations. It works in conjunction with the register array for many of these, in particular, the accumulator, general purpose registers and flag. Mostly, the accumulator holds the results of operations, while the flag register contains a number of individual bits that are used to store information about the last operation carried out by the ALU.

Figure 1.2 Simple CPU Model The control unit is the most complicated part of the CPU, and is responsible for controlling much of the operations of the rest of the processor. It does this by issuing control signals to the other areas of the processor, instructing them on what should be performed next. The control unit can be broken down into three main elements: is used to decode the instructions that make up a program when they are being processed, and to determine in what actions must be taken in order to process them. These decisions are normally taken by looking at the opcode of the instruction, together with the addressing mode used. ensures that all processes and instructions are carried out and completed at the right time. Pulses are sent to the other areas of the CPU at regular intervals (related to the processor clock speed), and actions only occur when a pulse is detected. This ensures that the operations of the CPU are synchronized. which are used to create the control signals themselves, which are then sent around the processor. These signals inform the arithmetic and logic unit and the register array what they actions and steps they should be performing, what data they should be using to perform actions, and what should be done with the results. contains the memory address of the instruction to be executed. During execution, the contents of the PC are updated to point to the next instruction. Every time that an instruction is to be executed, the program counter releases its contents to the internal bus and sends it to the memory address register. holds the address of the location to or from which data are to be transferred. As can be seen from the figure above, the connection of the MAR to the main memory is one-way or unidirectional. contains the data to be written or read out of the addressed location. During the fetch operation, the MDR contains the instruction to be executed or data needed during execution. In write operation, MDR contains the data to be written into the main memory.

contains the instruction that is being executed.  PC is set to point to the first instruction of the program (the operating system loads the memory address of the first instruction).  The contents of the PC are transferred to the MAR (which is automatically transmitted to the MM) and a Read signal is sent to the MM.

 The addressed word is read out of MM and loaded into the MDR.

 The contents of MDR are transferred to the IR. The instruction is ready to be decoded and executed.

 During execution, the contents of the PC are incremented or updated to point to the next instruction. Most modern processors work on fetch-decode-execute principle. This is also called Von Neumann Architecture. When a set of instructions is to be executed, the instructions and data are loaded into main memory. The address of the first instruction is copied into the program counter PC (IP in 8086 processor). The execution of an instruction by a processor is divided into three parts. These parts (shown in the following figure), are fetching, decode and execute

Fetch Cycle Decode Cycle Execute Cycle

Figure 1.3 Instruction Execution Cycle Get the next instruction from memory In this cycle, the processor fetches the instruction from the memory according to the following sequence:

 The CPU puts the address of the next instruction (contents of the PC) on the address bus.

 The CPU sends read control signal to memory (MEMR).

 The memory places the instruction on the data bus.

 Instruction is then transferred from data bus to instruction register (IR). Translate the instruction into a form that the CPU can understand. Here, the control unit checks the instruction that is now stored within the instruction register. It determines which opcode and addressing mode have been used, and as such what actions need to be carried out in order to execute the instruction in question.

The actual actions which occur during the execute cycle of an instruction depend on both the instruction itself, and the addressing mode specified to be used to access the data that may be required.

All the instruction in memory are coded in binary form. The bits of the instruction are divided into groups called fields. The most common fields found in instruction formats are:

Opcode Mode Address

Figure 1.4. Instruction format with mode field The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and number of bits in each field if the instruction is in one memory word.

 256K= 28 × 210 = 218  18 bits (Address field)  7 addressing modes, 2n = 7 ln 2n = ln 7  n ln 2 = ln 7

 n = (ln 7 / ln 2) = 2.80735  n = 3 bits (mode field)  60 registers, 2m = 60, ln 2m = ln 60  m ln 2 = ln 60  m = (ln 60 / ln 2) = 5.90689  m = 6 bits (register field)

 Since each instruction take one memory word (32 bits)  32 – (18+3+6) = 5 bits (opcode field)

Opcode Mode Reg Address 5 bits 3 bits 6 bits 18 bits

Input Unit Output Unit

Address Bus

Data Bus CPU

Control Bus

ROM RAM

Figure 1.1. Block diagram of a computer system