DOCSLIB.ORG

Computer Architecture

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Computer Architecture Computer Architecture Computer Communication Engineering 3rd Year Al-Rafidain University College Introduction A computer is a data processing machine which operates automatically under the control of a list of instructions (called a program) stored in its main memory. The architecture of a computer is the general layout of its major components, the principal features of these components and how they are connected together. Computer System Components A computer system consists of four components: The microprocessor (CPU) Memory Input units Output units. All these components are connected together through a system bus. System Bus System bus is a common group of wires that interconnect components in a computer system. In the microprocessor based computer system three buses exist for this transfer of information: Address Bus. Data Bus. Control Bus. Input Unit Output Unit Address Bus CPU Data Bus Control Bus ROM RAM The Data Bus: transfers information between the microprocessor and its memory and I/O address space. Data transfers vary in size from 8-bit wide to 64-bit wide. The Data Bus is Bidirectional. speed in applications that use wide data. For example, if a 32-bit number is stored in memory, it takes the 8088 microprocessor 4 transfer operations to complete because its data bus is only 8-bit wide. The 80486 accomplishes the same task with 1 transfer because its data bus is 32-bit wide. Microprocessor Data Bus Address Bus Memory Size Width Width 8086 16 20 1 M 8088 8 20 1 M 80286 16 24 16 M 80386DX 32 32 4 G 80486DX 32 32 4 G Pentium I 64 32 4 G Pentium Pro 64 36 64 G Table 1.1. The Intel family of microprocessor bus and memory sizes contains lines that select the memory or I/O and cause them to perform a read or write operation. Control Signals Bus Cycle type IO/M RD/WR 0 1 Memory Read Memory Cycle 0 0 Memory Write 1 1 IO Read IO Cycle 1 0 IO Write Table 1. 2. Control Signals used to specify bus cycle types. Main CPU Components Any CPU must contain: The ALU is the section of the processor that is involved with executing arithmetic or logical operations. It works in conjunction with the register array for many of these, in particular, the accumulator, general purpose registers and flag. Mostly, the accumulator holds the results of operations, while the flag register contains a number of individual bits that are used to store information about the last operation carried out by the ALU. Figure 1.2 Simple CPU Model The control unit is the most complicated part of the CPU, and is responsible for controlling much of the operations of the rest of the processor. It does this by issuing control signals to the other areas of the processor, instructing them on what should be performed next. The control unit can be broken down into three main elements: is used to decode the instructions that make up a program when they are being processed, and to determine in what actions must be taken in order to process them. These decisions are normally taken by looking at the opcode of the instruction, together with the addressing mode used. ensures that all processes and instructions are carried out and completed at the right time. Pulses are sent to the other areas of the CPU at regular intervals (related to the processor clock speed), and actions only occur when a pulse is detected. This ensures that the operations of the CPU are synchronized. which are used to create the control signals themselves, which are then sent around the processor. These signals inform the arithmetic and logic unit and the register array what they actions and steps they should be performing, what data they should be using to perform actions, and what should be done with the results. contains the memory address of the instruction to be executed. During execution, the contents of the PC are updated to point to the next instruction. Every time that an instruction is to be executed, the program counter releases its contents to the internal bus and sends it to the memory address register. holds the address of the location to or from which data are to be transferred. As can be seen from the figure above, the connection of the MAR to the main memory is one-way or unidirectional. contains the data to be written or read out of the addressed location. During the fetch operation, the MDR contains the instruction to be executed or data needed during execution. In write operation, MDR contains the data to be written into the main memory. contains the instruction that is being executed. PC is set to point to the first instruction of the program (the operating system loads the memory address of the first instruction). The contents of the PC are transferred to the MAR (which is automatically transmitted to the MM) and a Read signal is sent to the MM. The addressed word is read out of MM and loaded into the MDR. The contents of MDR are transferred to the IR. The instruction is ready to be decoded and executed. During execution, the contents of the PC are incremented or updated to point to the next instruction. Most modern processors work on fetch-decode-execute principle. This is also called Von Neumann Architecture. When a set of instructions is to be executed, the instructions and data are loaded into main memory. The address of the first instruction is copied into the program counter PC (IP in 8086 processor). The execution of an instruction by a processor is divided into three parts. These parts (shown in the following figure), are fetching, decode and execute Fetch Cycle Decode Cycle Execute Cycle Figure 1.3 Instruction Execution Cycle Get the next instruction from memory In this cycle, the processor fetches the instruction from the memory according to the following sequence: The CPU puts the address of the next instruction (contents of the PC) on the address bus. The CPU sends read control signal to memory (MEMR). The memory places the instruction on the data bus. Instruction is then transferred from data bus to instruction register (IR). Translate the instruction into a form that the CPU can understand. Here, the control unit checks the instruction that is now stored within the instruction register. It determines which opcode and addressing mode have been used, and as such what actions need to be carried out in order to execute the instruction in question. The actual actions which occur during the execute cycle of an instruction depend on both the instruction itself, and the addressing mode specified to be used to access the data that may be required. All the instruction in memory are coded in binary form. The bits of the instruction are divided into groups called fields. The most common fields found in instruction formats are: Opcode Mode Address Figure 1.4. Instruction format with mode field The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and number of bits in each field if the instruction is in one memory word. 256K= 28 × 210 = 218 18 bits (Address field) 7 addressing modes, 2n = 7 ln 2n = ln 7 n ln 2 = ln 7 n = (ln 7 / ln 2) = 2.80735 n = 3 bits (mode field) 60 registers, 2m = 60, ln 2m = ln 60 m ln 2 = ln 60 m = (ln 60 / ln 2) = 5.90689 m = 6 bits (register field) Since each instruction take one memory word (32 bits) 32 – (18+3+6) = 5 bits (opcode field) Opcode Mode Reg Address 5 bits 3 bits 6 bits 18 bits Input Unit Output Unit Address Bus Data Bus CPU Control Bus ROM RAM Figure 1.1. Block diagram of a computer system .
Load more

Recommended publications
  • The Intel Microprocessors: Architecture, Programming and Interfacing Introduction to the Microprocessor and Computer
    Microprocessors (0630371) Fall 2010/2011 – Lecture Notes # 1 The Intel Microprocessors: Architecture, Programming and Interfacing Introduction to the Microprocessor and computer Outline of the Lecture Evolution of programming languages. Microcomputer Architecture. Instruction Execution Cycle. Evolution of programming languages: Machine language - the programmer had to remember the machine codes for various operations, and had to remember the locations of the data in the main memory like: 0101 0011 0111… Assembly Language - an instruction is an easy –to- remember form called a mnemonic code . Example: Assembly Language Machine Language Load 100100 ADD 100101 SUB 100011 We need a program called an assembler that translates the assembly language instructions into machine language. High-level languages Fortran, Cobol, Pascal, C++, C# and java. We need a compiler to translate instructions written in high-level languages into machine code. Microprocessor-based system (Micro computer) Architecture Data Bus, I/O bus Memory Storage I/O I/O Registers Unit Device Device Central Processing Unit #1 #2 (CPU ) ALU CU Clock Control Unit Address Bus The figure shows the main components of a microprocessor-based system: CPU- Central Processing Unit , where calculations and logic operations are done. CPU contains registers , a high-frequency clock , a control unit ( CU ) and an arithmetic logic unit ( ALU ). o Clock : synchronizes the internal operations of the CPU with other system components using clock pulsing at a constant rate (the basic unit of time for machine instructions is a machine cycle or clock cycle) One cycle A machine instruction requires at least one clock cycle some instruction require 50 clocks. o Control Unit (CU) - generate the needed control signals to coordinate the sequencing of steps involved in executing machine instructions: (fetches data and instructions and decodes addresses for the ALU).
    [Show full text]
  • Unit 8 : Microprocessor Architecture
    Unit 8 : Microprocessor Architecture Lesson 1 : Microcomputer Structure 1.1. Learning Objectives On completion of this lesson you will be able to : ♦ draw the block diagram of a simple computer ♦ understand the function of different units of a microcomputer ♦ learn the basic operation of microcomputer bus system. 1.2. Digital Computer A digital computer is a multipurpose, programmable machine that reads A digital computer is a binary instructions from its memory, accepts binary data as input and multipurpose, programmable processes data according to those instructions, and provides results as machine. output. 1.3. Basic Computer System Organization Every computer contains five essential parts or units. They are Basic computer system organization. i. the arithmetic logic unit (ALU) ii. the control unit iii. the memory unit iv. the input unit v. the output unit. 1.3.1. The Arithmetic and Logic Unit (ALU) The arithmetic and logic unit (ALU) is that part of the computer that The arithmetic and logic actually performs arithmetic and logical operations on data. All other unit (ALU) is that part of elements of the computer system - control unit, register, memory, I/O - the computer that actually are there mainly to bring data into the ALU to process and then to take performs arithmetic and the results back out. logical operations on data. An arithmetic and logic unit and, indeed, all electronic components in the computer are based on the use of simple digital logic devices that can store binary digits and perform simple Boolean logic operations. Data are presented to the ALU in registers. These registers are temporary storage locations within the CPU that are connected by signal paths of the ALU.
    [Show full text]
  • HOW FAST? the Current Intel® Core™ Processor Has 43,000,000% More Transistors Than the 4004 Processor
    40yrs of Intel® microprocessor innovation Following Moore’s Law the whole way Intel co-founder Gordon Moore once made a famous prediction that transistor The world’s first microprocessor count for computer chips would —the Intel® 4004—was “born” in 1971, double every two years. 10 years before the first PC came along. Using Moore’s Law as a guiding principle, Intel has provided ever-increasing functionality, performance and energy efficiency to its products. Just think: What if the world had followed this golden rule the last 40 years? HOW FAST? The current Intel® Core™ processor has 43,000,000% more transistors than the 4004 processor. If a village with a 1971 population of 100 had grown as quickly, it would now be by far the largest city in the world. War and Peace? Wait a second. The 4004 processor executed 92,000 instructions per second, while today’s Intel® Core™ i7 processor can run 92 billion. If your typing had accelerated at that rate, you’d be able to type Tolstoy’s classic in just over 1 second. 0101010101010101… You would need 25,000 years to turn a light switch on and off 1.5 trillion times, but today’s processors can do that in less than a second. A PENNY SAVED… When released in 1981, the first well- equipped IBM PC cost about $11,250 in inflation-adjusted 2011 dollars. Today, much more powerful PCs are available in the $500 range (or even less). Fly me to the moon If space travel had come down in price as much as transistors have since 1971, the Apollo 11 mission, which cost around $355 million in 1969, would cost about as much as a latte.
    [Show full text]
  • Trends in Processor Architecture
    A. González Trends in Processor Architecture Trends in Processor Architecture Antonio González Universitat Politècnica de Catalunya, Barcelona, Spain 1. Past Trends Processors have undergone a tremendous evolution throughout their history. A key milestone in this evolution was the introduction of the microprocessor, term that refers to a processor that is implemented in a single chip. The first microprocessor was introduced by Intel under the name of Intel 4004 in 1971. It contained about 2,300 transistors, was clocked at 740 KHz and delivered 92,000 instructions per second while dissipating around 0.5 watts. Since then, practically every year we have witnessed the launch of a new microprocessor, delivering significant performance improvements over previous ones. Some studies have estimated this growth to be exponential, in the order of about 50% per year, which results in a cumulative growth of over three orders of magnitude in a time span of two decades [12]. These improvements have been fueled by advances in the manufacturing process and innovations in processor architecture. According to several studies [4][6], both aspects contributed in a similar amount to the global gains. The manufacturing process technology has tried to follow the scaling recipe laid down by Robert N. Dennard in the early 1970s [7]. The basics of this technology scaling consists of reducing transistor dimensions by a factor of 30% every generation (typically 2 years) while keeping electric fields constant. The 30% scaling in the dimensions results in doubling the transistor density (doubling transistor density every two years was predicted in 1975 by Gordon Moore and is normally referred to as Moore’s Law [21][22]).
    [Show full text]
  • What Is a Microprocessor?
    Behavior Research Methods & Instrumentation 1978, Vol. 10 (2),238-240 SESSION VII MICROPROCESSORS IN PSYCHOLOGY: A SYMPOSIUM MISRA PAVEL, New York University, Presider What is a microprocessor? MISRA PAVEL New York University, New York, New York 10003 A general introduction to microcomputer terminology and concepts is provided. The purpose of this introduction is to provide an overview of this session and to introduce the termi­ MICROPROCESSOR SYSTEM nology and some of the concepts that will be discussed in greater detail by the rest of the session papers. PERIPNERILS EIPERI MENT II A block diagram of a typical small computer system USS PRINIER KErBOARD INIERfICE is shown in Figure 1. Four distinct blocks can be STDRIGE distinguished: (1) the central processing unit (CPU); (2) external memory; (3) peripherals-mass storage, CONTROL standard input/output, and man-machine interface; 0111 BUS (4) special purpose (experimental) interface. IODiISS The different functional units in the system shown here are connected, more or less in parallel, by a number CENTKll ElIEBUL of lines commonly referred to as a bus. The bus mediates PROCESSING ME MOil transfer of information among the units by carrying UN IT address information, data, and control signals. For example, when the CPU transfers data to memory, it activates appropriate control lines, asserts the desired Figure 1. Block diagram of a smaIl computer system. destination memory address, and then outputs data on the bus. Traditionally, the entire system was built from a CU multitude of relatively simple components mounted on interconnected printed circuit cards. With the advances of integrated circuit technology, large amounts of circuitry were squeezed into a single chip.
    [Show full text]
  • Chapter 1: Microprocessor Architecture
    Chapter 1: Microprocessor architecture ECE 3120 – Fall 2013 Dr. Mohamed Mahmoud http://iweb.tntech.edu/mmahmoud/ [email protected] Outline 1.1 Computer hardware organization 1.1.1 Number System 1.1.2 Computer hardware organization 1.2 The processor 1.3 Memory system operation 1.4 Program Execution 1.5 HCS12 Microcontroller 1.1.1 Number System - Computer hardware uses binary numbers to perform all operations. - Human beings are used to decimal number system. Conversion is often needed to convert numbers between the internal (binary) and external (decimal) representations. - Octal and hexadecimal numbers have shorter representations than the binary system. - The binary number system has two digits 0 and 1 - The octal number system uses eight digits 0 and 7 - The hexadecimal number system uses 16 digits: 0, 1, .., 9, A, B, C,.., F 1 - 1 - A prefix is used to indicate the base of a number. - Convert %01000101 to Hexadecimal = $45 because 0100 = 4 and 0101 = 5 - Computer needs to deal with signed and unsigned numbers - Two’s complement method is used to represent negative numbers - A number with its most significant bit set to 1 is negative, otherwise it is positive. 1 - 2 1- Unsigned number %1111 = 1 + 2 + 4 + 8 = 15 %0111 = 1 + 2 + 4 = 7 Unsigned N-bit number can have numbers from 0 to 2N-1 2- Signed number %1111 is a negative number. To convert to decimal, calculate the two’s complement The two’s complement = one’s complement +1 = %0000 + 1 =%0001 = 1 then %1111 = -1 %0111 is a positive number = 1 + 2 + 4 = 7.
    [Show full text]
  • Powerpc 620™ RISC Microprocessor Technical Summary
    SA14-2069-01 MPC620/D (IBM Order Number) (Motorola Order Number) 7/96 REV 1 ™ Advance Information PowerPC 620™ RISC Microprocessor Technical Summary This document provides an overview of the PowerPC 620 microprocessor. It includes the following: • Part 1, “PowerPC 620 Microprocessor Overview,” provides a summary of 620 features. • Part 2, “PowerPC 620 Microprocessor Hardware Implementation,” provides details about the 620 hardware implementation. This includes descriptions of the 620’s execution units, cache implementation, memory management units (MMUs), and system interface. • Part 3, “PowerPC 620 Microprocessor Execution Model,” provides a description of the 620 execution model. This section includes information about the programming model, instruction set, exception model, and instruction timing. • Part 4, “Performance Monitor,” discusses the performance monitor facility of the 620. In this document, the term ‘620’ is used as an abbreviation for ‘PowerPC 620 microprocessor’. The PowerPC 620 microprocessors are available from IBM as PPC620 and from Motorola as MPC620. To locate any published errata or updates for this document, refer to the website at http://www.mot.com/powerpc/ or at http://www.chips.ibm.com/products/ppc. 620 Technical Summary 620 Technical The PowerPC name, the PowerPC logotype, and PowerPC 620 are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. © Motorola Inc., 1996. All rights reserved Portions hereof © International Business Machines Corporation, 1991–1996. All rights reserved Part 1 PowerPC 620 Microprocessor Overview This section describes the features of the 620, provides a block diagram showing the major functional units, and describes briefly how those units interact.
    [Show full text]
  • V850e/Ms1 , V850e/Ms2
    User’s Manual V850E/MS1TM, V850E/MS2TM 32-Bit Single-Chip Microcontrollers Architecture V850E/MS1: V850E/MS2: µPD703100 µPD703130 µPD703100A µPD703101 µPD703101A µPD703102 µPD703102A µPD70F3102 µPD70F3102A Document No. U12197EJ6V0UM00 (6th edition) Date Published November 2002 N CP(K) 1996 Printed in Japan [MEMO] 2 User’s Manual U12197EJ6V0UM NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry.
    [Show full text]
  • Intel® Itanium™ Processor Microarchitecture Overview
    Itanium™ Processor Microarchitecture Overview Intel® Itanium™ Processor Microarchitecture Overview Harsh Sharangpani Principal Engineer and IA-64 Microarchitecture Manager Intel Corporation ® Microprocessor Forum October 5-6, 1999 Itanium™ Processor Microarchitecture Overview Unveiling the Intel® Itanium™ Processor Design l Leading-edge implementation of IA-64 architecture for world-class performance l New capabilities for systems that fuel the Internet Economy l Strong progress on initial silicon ® Microprocessor Forum 2 October 5-6, 1999 Itanium™ Processor Microarchitecture Overview Itanium™ Processor Goals l World-class performance on high-end applications – High performance for commercial servers – Supercomputer-level floating point for technical workstations l Large memory management with 64-bit addressing l Robust support for mission critical environments – Enhanced error correction, detection & containment l Full IA-32 instruction set compatibility in hardware l Deliver across a broad range of industry requirements – Flexible for a variety of OEM designs and operating systems Deliver world-class performance and features for servers & workstations and emerging internet applications ® Microprocessor Forum 3 October 5-6, 1999 Itanium™ Processor Microarchitecture Overview EPIC Design Philosophy ì Maximize performance via EPICEPIC hardware & software synergy ì Advanced features enhance instruction level parallelism ìPredication, Speculation, ... ì Massive hardware resources for parallel execution VLIW OOO / SuperScalar ì High performance
    [Show full text]
  • Chapter 29 Itanium Architecture
    Chapter 29 Itanium Architecture Chapter 29 - Itanium Architecture July 2003 Chapter 29 / Page 1 Chapter 29 Itanium Architecture INDEX Introduction 3 Overview of the Itanium Architecture 3 Main features of EPIC....................................................................................................... 3 The Itanium processor family (IPF) 5 HP-UX Itanium Releases 6 Differences between HP-UX for PA and IPF ................................................................... 6 What needs to be considered on an IPF system 8 How an IPF system boots.................................................................................................. 8 Boot disk layout and EFI................................................................................................... 8 How to configure the Console input/output devices....................................................... 10 The boot process ............................................................................................................. 13 How to mirror the root disk............................................................................................. 18 How to replace a failed disk............................................................................................ 21 The ARIES emulator 22 IPF vs. PA-RISC Terminology 22 Additional Information 23 July 2003 Chapter 29 / Page 2 Chapter 29 Itanium Architecture Introduction When PA-RISC was released, HP began designing the architecture to replace it. Several years into the project, HP determined that the economics
    [Show full text]
  • ARM Processor Family
    ARM Processor family ● General Introduction of ARM A general overview about this processor family. The section is divided into: ○ Advanced Reduced-instruction-set-computer Machine ○ ARM registers ○ ARM instruction sets ○ ARM programmers’ model ○ ARM exceptions ○ ARM Memory architecture ● Set of ARM processors Widest range of microprocessor cores to address the performance, power and cost requirements for almost all application markets. Processors grouped as follows: ○ Cortex - A: Highest performance, optimized for rich operating systems ○ Cortex - R: Fast response, optimized for high-performance, hard real-time applications ○ Cortex - M: Smallest/lowest power, optimized for discrete processing and microcontroller ○ SecurCore: Tamper resistant, optimized for security applications ARM FAmily Handout Gobbato Simone - Torkar Chris 08.01.2017 ● Embedded vs Application processor This comparison will focus on the two most spread groups on the market. ARM M processors and ARM A processor: ARM M core ARM A core Single Core Multi Core capable < 550MHz < 2.5Ghz Single Application targeted Operating System targeted Low Power focused High computational Power focused Several low power operating mods MMU & MPU Power consumption optimized External Memory interface with 64bit peripherals Address Space Dhrystone performance difference: Processor Speed Dhrystone MIPS TI KeyStone 2 ARM A15 Quad Core 1.4 GHz 19600 ST STM32F217 ARM Cortex M3 120 MHz 150 As those two tables show the application field for the processor target different market segments: ARM M
    [Show full text]
  • 60 Years of the Transistor: 1947 – 2007
    60 YEARS OF THE TRANSISTOR: 1947 – 2007 2005 – Dual-core technology 1947 – When it comes to 2000 – The 42-million transistor debuts. If was introduced. helping jumpstart innovation 1976 – An operator in an early automobile speed increased similarly over 1960 – Sony introduces the rst 1982 – Within six years of its release, an and technology, no invention is bunnysuit shows how a 4-inch that same period, you could drive from New portable, transistorized TV, the estimated 15 million 286-based The Revolution Begins more important than the wafer is prepared for a positive York City to San Francisco in 13 seconds. transistor created 60 years ago TV8-301. It has a modest 5-inch acid spin. personal computers were installed at Bell Labs. screen and uses 23 silicon and around the world. germanium transistors. 1981 – The Intel® 8088 microprocessor was selected to Invented 60 years ago, the transistor is a key power the IBM PC. 1983 – Mobile communication building block of today’s digital world. changes forever when Motorola introduces the rst 2006 – The dual core Intel® Itanium® 2 1965 – Moore’s Law, which states that the Perhaps the most important invention of the commercial mobile phone – processor launches with the world’s most The Revolution Continues number of transistors on a chip doubles about the DynaTAC 800X – powered intricate product design to date, utilizing every two years, is born when Intel’s Gordon by transistors and costing a more than 1.72 billion transistors. 20th century, transistors are found in many Moore made a prediction about the 1972 – Intel’s rst microprocessor, mere $3,995.
    [Show full text]