A PLL Frequency Multiplier for LVDS Transmitter

Zhang Tao1,2, Zou Xuecheng1,3, Shen Xubang1 (1. Inst. of Patt. Recog. and Artif . Intellig., Wuhan, Hubei 430074; 2. Inst. of Info., Wuhan Univ. of Sci. & Technol., Wuhan, Hubei 430073 , P. R. China; 3. Dept. of Elec. Sci. and Technol., Huazhong Univ. of Sci. and Technol. , Wuhan, Hubei 430074.)

Abstract-A 3.5 times PLL clock frequency multiplier for LVDS signals (Udetect, Ddetect). The lock detecting signals enter driver is presented. A novel adaptive charge pump can lock detection circuit [2] which is used to detect the loss of automatically switch the loop bandwidth, and a VCO is designed lock condition. When the loop goes out of lock, the output of with the aid of frequency ranges reuse technology. The circuit is the detect circuit is high, controlling to switch charge pump implemented using 1st Silicon 0.25µm mixed-signal CMOS process. Simulation results show that the PLL clock frequency current to 2I cp . When the loop is under lock conduction, the multiplier has very low phase noise and very short capture time. output of lock detection circuit is low, the output of lock detection circuit control to switch charge pump current to I. INTRODUCTION or 1 I . So an adaptive charge pump (CP) which can I cp 2 cp Low voltage different signal (LVDS) has extensively automatically change current value is demanded. By means of applications especially in such as high-speed transmission adaptive CP, the loop bandwidth can be switched to a higher system of digital video due to its high speed, low noise and value when lock is lost, which helps minimize the capture low power dissipation [1]. The transmitter complying with the time, and the loop bandwidth under lock condition is kept low LVDS standard converts 7 bits CMOS parallel data into 1 bit to suppress input noise. In the block diagram of Fig. 1, a LVDS signal for serial transfer. In order to hold the data regulating amplifier between the loop filter and VCO is transmission speed, the rate of the output data is as 7 times as implanted to decrease the gain of VCO. Thus, the noise of the rate of the input data. So in theory synchronous clock for control voltage is suppressed, and the gain of VCO exhibits converting parallel signal to serial signal should be as 7 times good linearity [3]. as the input clock, but in practice it is as 3.5 times as the input Regarding with the reuse frequency circuit, the control clock because of using rising edge and falling edge of clock at circuit for reuse of VCO frequency range is used to determine the same time. the ratio of P divider is 4 or 2 according to the control voltage To meet the need of the clock of the LVDS transmitter, a of VCO, and to determine the output current of the charge 1 3.5 times charge pump PLL multiplier is presented, which has pump is I cp or I cp corresponding to the divider ratio. As st 2 already been implemented by using 1 Silicon 0.25µm what we raised in the forepart of this paper, the output mixed-signal CMOS process. The input clock of the 3.5 times frequency of the PLL ranges from 87.5MHz to 315MHz charge pump PLL multiplier is 25MHz to 90MHz and the which could be divided into two parts centered at 157.5MHz. output clock ranges from 87.5 MHz to 315MHz. Applying a If the output frequency of the PLL varies from 87.5MHz to dynamic current matching charge pump and frequency range 157.5MHz, the ratio P divider is 4, and the output frequency reuse of voltage controlled oscillator (VCO), the bandwidth of of VCO is ∗ to ∗ MHz. If the the loop can also be adaptively changed to quicken the )45.87(350 )45.157(630 capture speed and to reduce noise of the loop circuit. So the output frequency of the PLL varies from 175.5MHz to performance of PLL clock frequency multiplier is improved 315MHz, the ratio P divider is 2, and the output frequency of drastically. VCO is ∗ )25.157(315 to ∗ )2315(630 MHz. The analysis above demonstrates that the operate frequency of the II. SYSTEM DESIGN VCO is reused in the range of 350 to 630MHz, which reduces

The system block diagram of the PLL clock frequency operate range of the VCO and hence approaching better gain multiplier is shown in Fig. 1. The external reference clock linearity of the VCO. At the same time, the control voltage Refclk of 25MHz to 90MHz is divided by two with the aid of range of the VCO is decreased to the original half, which Φ provides a condition to match the charge and discharge a divider M (M=2), which results in the phase i , and then current of the CP. Finally the performance of the PLL circuit Φ is improved. the phase i enters phase/frequency detector (PFD). The Φ To reach the performance demand of the PLL system, the phase o of internal feedback clock from divider N (N=7) charge pump is designed in this paper, which can adaptively is compared to Φ by the PFD. The PFD generates two change CP current and can simultaneously perform high CP i current accuracy. The CP current is provided by bandgap 1 types of signals: (1) error signal (UP ，UP , DN , DN ) current source and is 2 I cp , I cp , 2 I cp , respectively. It is which is used by charge pump and loop filter to control known to all, the free oscillation frequency of the loop is voltage-controlled oscillator (VCO), and (2) lock detecting given by [4]:

Fig. 1. The block diagram of PLL clock frequency multiplier

KI current of charge pump must be of perfect matching in order ω = op to the output voltage of the loop filter remains constant. n (1) π ⋅ )(2 CPN ⋅ where K o , I p , PN represent the gain of VCO, the current of CP, the total divider ratio of loop respectively. It could be noted from the equation (1) that the condition of I keeping ω constant is actually to keep the ratio of p n P constant. Therefore if the loop circuit is locked and the ratio 1 of P divider is 2, the output current of CP is 2 I cp , and if the loop circuit is locked and the ratio of P divider is 4, the output current is I . However, when the loop is not locked, the CP cp current is 2 I to reduce the capture time by controlling the Fig. 2 Phase/Frequency Detector implementation cp lock detection circuit. As a result, when the loop circuit is not locked, the loop bandwidth is large, and when the loop is B. Adaptive Charge Pump (CP) under lock, the loop bandwidth is half less than that under In order to make the current of CP accurate and matching, unlock condition, resulting in suppressing input noise of PLL. an adaptive charge pump with perfect current matching is

presented, as shown in figure 3。The circuit of the CP consists II. BLOCK DESIGN of three parts. The top left corner is the production circuit of A. Phase/Frequency Detector current source and controlled circuit for current change, the The PFD design is based on a three state machine structure top right corner is the main charge pump which performs [5], as depicted in figure 2. The PFD consists of two R-S charge and discharge of the loop filter to produce controlled voltage of VCO, and the bottom is the auxiliary charge flip-flops, five NAND gates and four inverters. In order to Vctrl meet the demand of charge pump, the clock tree consisting of pump which achieves accurate I up and I dn dynamic inverters generates three pairs of different charge-up (UP ， matching. UP ), a pair of different charge-down ( DN , DN ). The The charge current generated by bandgap current reference signals of Udetect and Ddetect are used for the lock detection is mirrored to M9 of the main CP and the auxiliary CP, which circuit. The advantage of this circuit is of small dead zone. forms current source for charge. Thought the switches K1 and The reason is that the dead zone is eliminated by the K2, the current mirrored to M9 can adjusted. If switch K1 is propagation delay of four-input NAND gate, which produces off and switch K2 is on, the drain current from M9 is 2I (In a minimum pulse width at the PFD output even when the figure 3, the drain current of M18 and M20 are I , phase error is zero. The narrow pulse results in the charge and respectively); if switch K1 and K2 are off, the drain current of discharge switches of CP to be on simultaneously. So the M9 is I ; if switch K1 is on and switch K2 is off, then M14

0-7803-9335-X/05/$20.00 ©2005 IEEE 1411 and M15 are in parallel. Assume that the channel width and remains constant. On the other hand, if < , current II dnup channel length of M14 are the same with these of M15, so the − II flows out the capacitor C, which cause voltage of drain current of M9 is 1 . It is obvious the adaptive change dnup 2 I of CP current is provided as long as switch K1 and K2 can be node N descend, and the drain current of M10 must also digitally controlled. descend. Upon the current mirroring effect, the drain current flowing in M11, M12 and M13 also descend, and finally = . Obviously, the current matching in the II dnup proposed structural CP is dynamic matching. However, for the traditional CP, it is static matching, which implies that the static current matching of the traditional CP is = in the II dnup direct current operation state. Once the voltage changes, Vctrl

current source Iup may not be equal to current sink Idn . The proposed CP circuit not only overcomes this shortcoming, but also solves current mismatching because of the variances of the processes, temperature and voltage of power supply. Especially, this CP is suitable for wide-band RF PLL applications. In figure 3, two differential pairs consisting of transistors M5, M6 and M7, M8 will convert full-swing signals of PFD output into low voltage signals to make transistors M1, M2, M3 and M4 operate in their saturation or cut-off region, intuitively leading to a faster operation of transistors M1, M2, M3 and M4. The spikes of output current will be reduced and low harmonics level at the input of VCO is achieved. At the same time, the output impedance of current source and current sink is increased by the casecode connection of M9, M3 and

M1, M12. Fig. 3 Proposed design for charge pump

Moreover, the accurate dynamic matching of I and I C. Voltage Controlled Oscillator (VCO) up dn In order to improve the PLL jitter performance, Figure 4 is achieved by an auxiliary CP. The current sink consisting of M12 does not derive directly from current mirror formed by illustrates the proposed gain compensation VCO, which has a transistors M14~M21, but from an auxiliary CP in the bottom low gain and nicer linear V-f characteristics. The VCO is of figure 3, which induces discharge current of current sink following the charge current of current source. In other words, composed of two parts: regulating amplifier and coupled if drain voltage of M3 and M9 varies respectively with the single-ended ring oscillator. By the regulating amplifier [6], voltage , current source will change and current sink Vctrl I up the control voltage Vctrl is converted into virtual supply Vc . Idn will vary with current source Iup and eventually resulting in = II , which is dynamically equal. In detail, if dnup In figure 4, the voltage Vc is regard as power supply of > II and UP signal is low, transistors M1 and M3 of the dnup coupled single-ended ring oscillator, and controls the auxiliary CP are on at the same time. According to Kirchhoff’s current law, current − flows to the oscillation frequency of the VCO. Therefore, the proposed II dnup capacitor C, causing voltage of node N rise, and the drain VCO achieves low gain and nicer linear V-f characteristics. current of M10 must also rise. According to the current Figure 4 shows a coupled ring oscillator structure that mirroring effect, the same drain current flow in M11, M12 consists of two single-ended ring oscillators coupled together and M13. Finally, the charge current of the current source is by weak inverters that keep the two structure 180 degrees out followed by the discharge current of current sink, of phase. This structure somewhat reduces the sensitivity to namely, =− , and the voltage on the capacitor C II dnup 0 supply and substrate noise, while enjoying some of the

benefits of differential oscillators. At the same time, it has low III. SIMULATION RESULTS AND LAYOUT phase noise due to device thermal noise and 1/f noise as st single-ended ring oscillator. In addition, a small capacitance is The PLL clock frequency multiplier is designed in 1 added to every delay stage output node to suppress supply Silicon 0.25µm 2.5V mixed-signal CMOS process. With noise despite reducing oscillation frequency. Hspice simulation is done in three conditions which 25℃, 2.5V, tntp model, 75℃, 2.25V, snsp model and 0℃, 2.75V, fnfp model. The results show PLL clock frequency multiplier output frequency is as 3.5 times as input frequency. The waveforms of input 50MHz and output 175MHz are shown in figure 6. The curves of control voltage in 25MHz and 50MHz input condition are in figure 7 (a) and (b), respectively. In figure 7, stable control voltage is equal to 0.6V, and the operating frequency of VCO is 350MHz. Dividing by 4 and 2, the output frequency of PLL are 87.5MHz and 175MHz, respectively. Obviously the frequency point is reused. Figure 8 shows FFT noise analysis. The layout of the PLL clock frequency multiplier shows in figure 9.

Fig. 4 gain compensation VCO

D. Frequency Range Reuse Circuit for VCO As described in section 2, in order to reduce the operate range of the VCO control voltage, the oscillation frequency of the VCO is reused in the range of 350 to 630MHz. The reuse Fig. 6 The waveforms of input 50MHz and output 175MHz control circuit is shown in figure 5. The comparator A compares control voltage with sample voltage . If Vc V1 > c VV 1 , the output of the comparator A is high, which makes

(a) The curves of control voltage in 25MHz input condition

Fig. 5 Frequency range reuse control circuit for VCO (b) The curves of control voltage in 50MHz input condition the ratio of the divider P to 2 and the current of charge pump Fig. 7 The curves of control voltage of PLL to 1 I . The output frequency of the PLL is 157.5-315MHz. 2 cp At the same time, transistor M1 is on, and the negative port − voltage of comparator A changes from V1 to VV 21 . If −< c VVV 21 , the output of comparator A is low, which makes the ratio of the divider P to 4 and the current of charge pump to I . The output frequency of the PLL is cp 87.5-157.5MHz. At the same time, transistor M1 is off, and the negative port voltage of comparator A comes back to V1 . − Thus, the range of the control voltage is VV 21 to V1 , and the output frequency range of the VCO is 350-630MHz. The output frequency range of the PLL is 87.5-157.5MHz and

157.5-315MHz, respectively. Obviously the frequency range Fig.８ FFT noise analysis of the VCO is reused.

of VCO is reused by detecting the value of control voltage. The circuit is implemented using 1st silicon 0.25µm mixed signal CMOS process and simulated with Hspice. The results show that the PLL clock frequency multiplier has lower noise and short capture time, and performs 3.5 times frequency relation between input clock and output clock.

REFRERENCES

[1] LVDS owner’s manual[S], National Semiconductor, version 2.0. [2] Shariatdoust R., Nagaraj K. and Saniski M. et al, A Low Jitter 5MHz to 180MHz Clock Synthesizer for Video Graphics[A]. IEEE CICC, 1992: 24.2.1-24.2.5. Fig. 9 The layout of the PLL [3] Mansuri M. and Yang C. Jitter Optimization Based on Phase-Lock Loop Design Parameters[J], IEEE Journal of Solid-State Circuits, 2002; 37(11): 1375-1382. [4] Pacmel M. V. Analysis of a Charge Pump PLL: A New Model. IEEE Trans. on Communications, 1994, 42: 2490-2498. V. CONCLUSIONS [5] Best R. E., Phase-Locked Loops Design, Simulation, and Application[M], 5th edition, 2003, The McGraw-Hill Companies, Inc., A PLL clock frequency multiplier is designed in this paper, pp.19-23. whose input clock is 25 to 90MHz and output clock is 87.5 to [6] ZhangTao, Zou Xue-cheng，et al, Design of Low Noise Single Ended CMOS Ring Voltage controlled Oscillators [J]. Microelectronics and 315MHz. In design, a novel adaptive charge pump is used to Computer，2004, （7）, 164-167.. switch automatically the loop bandwidth, and frequency range