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A PLL Frequency Multiplier for LVDS Transmitter

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A PLL Frequency Multiplier for LVDS Transmitter A PLL Frequency Multiplier for LVDS Transmitter Zhang Tao1,2, Zou Xuecheng1,3, Shen Xubang1 (1. Inst. of Patt. Recog. and Artif . Intellig., Wuhan, Hubei 430074; 2. Inst. of Info., Wuhan Univ. of Sci. & Technol., Wuhan, Hubei 430073 , P. R. China; 3. Dept. of Elec. Sci. and Technol., Huazhong Univ. of Sci. and Technol. , Wuhan, Hubei 430074.) Abstract-A 3.5 times PLL clock frequency multiplier for LVDS signals (Udetect, Ddetect). The lock detecting signals enter driver is presented. A novel adaptive charge pump can lock detection circuit [2] which is used to detect the loss of automatically switch the loop bandwidth, and a VCO is designed lock condition. When the loop goes out of lock, the output of with the aid of frequency ranges reuse technology. The circuit is the detect circuit is high, controlling to switch charge pump implemented using 1st Silicon 0.25µm mixed-signal CMOS process. Simulation results show that the PLL clock frequency current to 2I cp . When the loop is under lock conduction, the multiplier has very low phase noise and very short capture time. output of lock detection circuit is low, the output of lock detection circuit control to switch charge pump current to I. INTRODUCTION or 1 I . So an adaptive charge pump (CP) which can I cp 2 cp Low voltage different signal (LVDS) has extensively automatically change current value is demanded. By means of applications especially in such as high-speed transmission adaptive CP, the loop bandwidth can be switched to a higher system of digital video due to its high speed, low noise and value when lock is lost, which helps minimize the capture low power dissipation [1]. The transmitter complying with the time, and the loop bandwidth under lock condition is kept low LVDS standard converts 7 bits CMOS parallel data into 1 bit to suppress input noise. In the block diagram of Fig. 1, a LVDS signal for serial transfer. In order to hold the data regulating amplifier between the loop filter and VCO is transmission speed, the rate of the output data is as 7 times as implanted to decrease the gain of VCO. Thus, the noise of the rate of the input data. So in theory synchronous clock for control voltage is suppressed, and the gain of VCO exhibits converting parallel signal to serial signal should be as 7 times good linearity [3]. as the input clock, but in practice it is as 3.5 times as the input Regarding with the reuse frequency circuit, the control clock because of using rising edge and falling edge of clock at circuit for reuse of VCO frequency range is used to determine the same time. the ratio of P divider is 4 or 2 according to the control voltage To meet the need of the clock of the LVDS transmitter, a of VCO, and to determine the output current of the charge 1 3.5 times charge pump PLL multiplier is presented, which has pump is I cp or I cp corresponding to the divider ratio. As st 2 already been implemented by using 1 Silicon 0.25µm what we raised in the forepart of this paper, the output mixed-signal CMOS process. The input clock of the 3.5 times frequency of the PLL ranges from 87.5MHz to 315MHz charge pump PLL multiplier is 25MHz to 90MHz and the which could be divided into two parts centered at 157.5MHz. output clock ranges from 87.5 MHz to 315MHz. Applying a If the output frequency of the PLL varies from 87.5MHz to dynamic current matching charge pump and frequency range 157.5MHz, the ratio P divider is 4, and the output frequency reuse of voltage controlled oscillator (VCO), the bandwidth of of VCO is ∗ to ∗ MHz. If the the loop can also be adaptively changed to quicken the )45.87(350 )45.157(630 capture speed and to reduce noise of the loop circuit. So the output frequency of the PLL varies from 175.5MHz to performance of PLL clock frequency multiplier is improved 315MHz, the ratio P divider is 2, and the output frequency of drastically. VCO is ∗ )25.157(315 to ∗ )2315(630 MHz. The analysis above demonstrates that the operate frequency of the II. SYSTEM DESIGN VCO is reused in the range of 350 to 630MHz, which reduces The system block diagram of the PLL clock frequency operate range of the VCO and hence approaching better gain multiplier is shown in Fig. 1. The external reference clock linearity of the VCO. At the same time, the control voltage Refclk of 25MHz to 90MHz is divided by two with the aid of range of the VCO is decreased to the original half, which Φ provides a condition to match the charge and discharge a divider M (M=2), which results in the phase i , and then current of the CP. Finally the performance of the PLL circuit Φ is improved. the phase i enters phase/frequency detector (PFD). The Φ To reach the performance demand of the PLL system, the phase o of internal feedback clock from divider N (N=7) charge pump is designed in this paper, which can adaptively is compared to Φ by the PFD. The PFD generates two change CP current and can simultaneously perform high CP i current accuracy. The CP current is provided by bandgap 1 types of signals: (1) error signal (UP ，UP , DN , DN ) current source and is 2 I cp , I cp , 2 I cp , respectively. It is which is used by charge pump and loop filter to control known to all, the free oscillation frequency of the loop is voltage-controlled oscillator (VCO), and (2) lock detecting given by [4]: 0-7803-9335-X/05/$20.00 ©2005 IEEE 1410 Fig. 1. The block diagram of PLL clock frequency multiplier KI current of charge pump must be of perfect matching in order ω = op to the output voltage of the loop filter remains constant. n (1) π ⋅ )(2 CPN ⋅ where K o , I p , PN represent the gain of VCO, the current of CP, the total divider ratio of loop respectively. It could be noted from the equation (1) that the condition of I keeping ω constant is actually to keep the ratio of p n P constant. Therefore if the loop circuit is locked and the ratio 1 of P divider is 2, the output current of CP is 2 I cp , and if the loop circuit is locked and the ratio of P divider is 4, the output current is I . However, when the loop is not locked, the CP cp current is 2 I to reduce the capture time by controlling the Fig. 2 Phase/Frequency Detector implementation cp lock detection circuit. As a result, when the loop circuit is not locked, the loop bandwidth is large, and when the loop is B. Adaptive Charge Pump (CP) under lock, the loop bandwidth is half less than that under In order to make the current of CP accurate and matching, unlock condition, resulting in suppressing input noise of PLL. an adaptive charge pump with perfect current matching is presented, as shown in figure 3。The circuit of the CP consists II. BLOCK DESIGN of three parts. The top left corner is the production circuit of A. Phase/Frequency Detector current source and controlled circuit for current change, the The PFD design is based on a three state machine structure top right corner is the main charge pump which performs [5], as depicted in figure 2. The PFD consists of two R-S charge and discharge of the loop filter to produce controlled voltage of VCO, and the bottom is the auxiliary charge flip-flops, five NAND gates and four inverters. In order to Vctrl meet the demand of charge pump, the clock tree consisting of pump which achieves accurate I up and I dn dynamic inverters generates three pairs of different charge-up (UP ， matching. UP ), a pair of different charge-down ( DN , DN ). The The charge current generated by bandgap current reference signals of Udetect and Ddetect are used for the lock detection is mirrored to M9 of the main CP and the auxiliary CP, which circuit. The advantage of this circuit is of small dead zone. forms current source for charge. Thought the switches K1 and The reason is that the dead zone is eliminated by the K2, the current mirrored to M9 can adjusted. If switch K1 is propagation delay of four-input NAND gate, which produces off and switch K2 is on, the drain current from M9 is 2I (In a minimum pulse width at the PFD output even when the figure 3, the drain current of M18 and M20 are I , phase error is zero. The narrow pulse results in the charge and respectively); if switch K1 and K2 are off, the drain current of discharge switches of CP to be on simultaneously. So the M9 is I ; if switch K1 is on and switch K2 is off, then M14 0-7803-9335-X/05/$20.00 ©2005 IEEE 1411 and M15 are in parallel. Assume that the channel width and remains constant. On the other hand, if < , current IIup dn channel length of M14 are the same with these of M15, so the II− flows out the capacitor C, which cause voltage of drain current of M9 is 1 . It is obvious the adaptive change up dn 2 I of CP current is provided as long as switch K1 and K2 can be node N descend, and the drain current of M10 must also digitally controlled.
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