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Crystal Oscillator Circuit

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Crystal Oscillator Circuit Tutorial Introduction PURPOSE - To explain how to configure and use the Clock Generator Module in typical applications OBJECTIVES: - Describe the main components of the Clock Generator Module. - Describe the uses and features of the crystal oscillator circuit. - Describe the uses and features of the PLL. - Identify the base clock source for a specific application. - Identify the steps to calculate the PLL programmable values. - Write a program to configure the PLL to generate a desired bus frequency. CONTENT: - 38 pages - 4 questions - 1 off-line programming exercise LEARNING TIME: - 60 minutes PREREQUESITE: - 68HC08 CPU training module Welcome to this tutorial on the 68HC08 Clock Generator Module (CGMC). This tutorial describes the features and configuration of the CGMC. Please note that on subsequent pages, you will find reference buttons in the upper right of the content frame that access additional content. Upon completion of this tutorial, you’ll be able to describe the main components of the CGMC. You’ll also be able to select an appropriate base clock source, calculate the different values required to program the phase-locked loop (PLL), and configure the PLL to generate a specific bus frequency. The recommended prerequisite for this tutorial is the 68HC08 CPU training module. Click the Forward arrow when you’re ready to begin the tutorial. 1 CGMC Features • PLL with programmable output frequency • Low-frequency crystal operation • Programmable prescaler • VCO for low-jitter operation • Automatic bandwidth control mode • Automatic frequency lock detector • CPU interrupt on entry or exit from locked condition • CGMC operation can be enabled during stop mode Let’s begin this tutorial with a discussion of the CGMC features. The CGMC includes an integrated PLL that is capable of generating frequencies at integer multiples of the crystal reference. For example, using the PLL can provide up to an 8.2Mhz bus frequency while using a much lower cost 32 Khz crystal. An additional benefit of the PLL is reduced noise generation since high speed crystals and oscillators are not necessary. The module has two programmable prescalers that provide power-of-two increases in frequency. Also included is a programmable hardware voltage-controlled oscillator, VCO, for low-jitter operation. The CGMC Module can automatically switch from acquisition mode to tracking mode, depending on how far the output is from the reference. The PLL automatically detects when the output frequency is close enough to the desired frequency and locks. The CPU can be configured to generate an interrupt when the desired frequency is locked or exits from the locked condition. In the CONFIG register, you can set the OSCSTOPENB bit to enable the oscillator to operate during stop mode. 2 CGMC Block Diagram OSC2 OSC1 CGMXCLK CGMRDV Reference Divider RDS3-RDS0 VDDA CGMXFC VSSA VPR1-VPR0 CGMOUT Internal ÷2 Phase Loop Clock Bus VCO ÷2 Detector Filter Select Frequency PLL Analog BCS SIMDIV2 VRS7-VRS0 Lock Automatic Interrupt Detector Mode Control Control CGMVCLK LOCK AUTO ACQ PLLIE PLLF Frequency Frequency CGMVDV Divider Divider MUL11-MUL0 PRE1-PRE0 The CGMC consists of three major sub-modules: the crystal oscillator circuit, the PLL, and the base clock selector circuit. The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the amplifier input and the OSC2 pin is the output. The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK, which runs at a rate equal to the crystal frequency. CGMXCLK is also buffered to produce the PLL reference clock. The PLL is a fully functional frequency generator that is designed for use with crystals or ceramic resonators. The PLL generates the programmable VCO frequency clock, CGMVCLK. The VCO frequency will be an integer multiple of the reference frequency. The base clock selector circuit is a software-controlled circuit that selects the base clock, CGMOUT. You can set the base clock to either CGMXCLK divided by two or CGMVCLK divided by two. The System Integration Module (SIM) derives the system clocks from CGMOUT or CGMXCLK with an additional divide by two circuits to produce the internal bus frequency. This will be discussed further in the training. Let’s take a closer look at each CGMC sub-module, beginning with the crystal oscillator circuit. 3 Crystal Oscillator Circuit Features • Used by other MCU modules for precise timing. • Duty cycle is not guaranteed to be 50%. • Can take crystal or external oscillator as source. • Crystal sources must be between 30 kHz to 100 kHz. • External oscillator with PLL enabled must be between 30 kHz and 1.5 MHz. • External oscillator with PLL disabled must be between DC and 32.8 MHz. The CGMXCLK can be used by modules that require precise timing for operation. Note that the duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. You can also use an externally generated clock to feed the OSC1 pin of the crystal oscillator circuit. To use this configuration, connect the external clock to the OSC1 pin and let the OSC2 pin float. The crystal oscillator circuit can take two different frequency sources, a crystal or an external oscillator. If you choose to use a crystal, the crystal frequency must be between 30 kHz and 100 kHz, typically 32.768 kHz. The oscillator has not been designed take crystal frequencies outside this range. If you choose to use an external oscillator as the clock source, you can choose to have the PLL enabled or disabled. With the PLL enabled, the external oscillator frequency must be between 30 kHz and 1.5 MHz. With the PLL disabled, the external oscillator frequency can go from direct current, or DC, up to 32 MHz. Let’s look at the circuit for each of these configurations. 4 Crystal Oscillator Circuit C2 RS OSC2 X 1 RB OSC1 CGMXCLK C1 The crystal frequency PLL must be between 30 kHz and 100 kHz (enabled or disabled) to guarantee proper operation When using a crystal as the clock source, the frequency can be selected as the base clock or as a reference clock for the PLL. In this configuration, the PLL may be enabled or disabled. 5 External Oscillator OSC2 Oscillator OSC1 CGMXCLK PLL The oscillator frequency (enabled) must be between 30 kHz and 1.5 MHz to guarantee proper operation With the external oscillator configuration, you can operate with the PLL enabled or disabled depending on the oscillator frequency. With the PLL enabled, you can use an external oscillator with a frequency between 30Khz and 1.5 Mhz. With the PLL disabled, you can use an external oscillator with a frequency between DC and 32.8 MHz. 6 PLL Features • Generates programmable VCO, CGMVCLK. • Operates in acquisition or tracking mode. • Acquisition mode makes large corrections to VCO. • Tracking mode makes fine adjustments to VCO. • Switches between modes automatically or manually. • Advantages of using a PLL: – Achieve a high bus-frequency using a low-cost crystal – Low-frequency crystals consume less power – Low-frequency crystals provide higher noise immunity Next, let’s take a look at the PLL sub-module. As discussed earlier, the PLL generates the programmable VCO frequency. The PLL can filter the VCO frequency using two modes: acquisition mode and tracking mode. The mode selection depends on the accuracy of the output frequency. In acquisition mode, the filter can make large frequency corrections to the VCO frequency. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. To select this mode, select the ACQ bit in the PLL bandwidth control register. In tracking mode, the filter makes small corrections to the VCO frequency. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. The PLL can change between acquisition and tracking modes either automatically or manually. Automatic mode is recommended for most applications. There are many advantages to including a PLL in the MCU. You can achieve a high bus frequency using a low-cost crystal, since low-frequency crystals are cheaper. Low-frequency crystals also consume less power and provide higher noise immunity. 7 PLL Circuits CGMXCLK CGMRDV Reference Divider RDS3-RDS0 VDDA CGMXFC VSSA VPR1-VPR0 Phase Loop VCO Base Clock Detector Filter PLL Analog Select Circuitry VRS7-VRS0 Lock Automatic Interrupt Detector Mode Control Control LOCK AUTO ACQ PLLIE PLLF ModuloFrequency VCO Frequency FrequencyDivider Divider PrescalerDivider CGMVDV CGMVCLK MUL11-MUL0 PRE1-PRE0 The PLL is basically an oscillator whose frequency is locked onto a frequency component of an input signal. In this example, the PLL acts as a frequency multiplier to achieve high-output frequency resolution using a low frequency crystal that minimizes cost, power consumption, and noise generation. Let’s take a detailed look at how the PLL works. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency f RCLK and is fed to the PLL through a programmable modulo reference divider, which divides the frequency by a factor R. The divider’s output is the final reference clock, CGMRDV. The VCO output clock, running at a frequency, f VCLK , is fed back through a programmable prescaler divider and a programmable modulo divider. The prescaler divides the VCO clock by a power-of-two factor, P, and the modulo divider reduces this frequency by a factor N. The output is the VCO feedback clock, CGMVDV, which runs at a frequency fVDV. The phase detector then compares CGMVDV with CGMRDV and generates a correction pulse based on the phase difference of the two signals.
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