Compiler and Integrated Development Environment for Embedded Software Design
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Fundamentals of Compiler and Integrated Development Environment for Embedded Software Design Max Mauro Dias Santos [email protected] Ponta Grossa, Paraná - Brazil January 23, 2021 What and where are the compiler and IDE? January 23, 2021 2 January 23, 2021 3 Outline 1. Introduction 2. Central Processing Unit 3. Memory 4. Embedded Programmig Languages 5. Compiler 6. GCC – GNU Compiler Collection 7. Integrated Development Environment 8. Embedded Systems Software Development Tools 9. Integrated Development Environment Tools 10.IDE - CodeBlocks Obs.: This material has been done based on several materials available and I reference the original owners throughout and in the end of this presentation. January 23, 2021 4 What will you learn in the end of this Lesson? 1. Understand about the features hardware: Central Processing Unit and Memory 2. The workflow for embedded programming languages 3. How works the compiler which is able to translate from source to machine code 4. Undertand about the compiler GCC – GNU Compiler Collection 5. Undestand, identify and how to use the IDE 6. Know the most used IDE tools 7. Build C programs using CodeBlock. It’s not yet for embedded over a hardware 8. We have to know identify a compiler for IBM-PC and Microcontroller. Is it a tough task? 9. Understand to build a simple application and test it’s quality. January 23, 2021 5 Introduction We have as a goal, learn how to setup and use tools for develop an embedded software. We have to understand what are the difference between source and machine codes. Moreover, what is the CISC and RISC architecture and Anyway, let’s try to introduce the fundamentals memory. of Compiler, na example of GCC and well know IDE or Integrated Development Environment. Is there a guideline to develop embedded software for embedded systems? We will show some of them. I hope to show you some compilers and IDEs available which will help you to work on properly toward become a beginner developer of embedded system. I have a dream. My goal is teach you a little bit more about software tools to develop embedded software based on ARM architecture. ARM has a bunch of resources and support RTOS. Finally, in the end of this lesson you will be able to select and use the most suitable toolchain for build embedded systems – hardware & software January 23, 2021 6 Computer Architecture The computer architecture is the programmer's view of a computer. It is defined by the instruction set (language) and operand locations (registers and memory). There are many different architectures, such as ARM, x86, MIPS, SPARC, and PowerPC. Question-1: What is the difference between architecture and organization? Question-2: Have you ever heard about RISC-V? January 23, 2021 7 Central Processing Unit Motivation On the right is a diagram representing the storage scheme for a generic computer. The main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 6: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the six registers (A, B, C, D, E, or F). Let's say we want to find the product of two numbers - one stored in location 2:3 and another stored in location 5:2 - and then store the product back in the location 2:3. The CISC Approach The RISC Approach MULT 2:3, 5:2 LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/ January 23, 2021 8 Central Processing Unit CISC x RISC Almost all modern CPU has different sorts of architecture. It utilizes the capacity to work from “Instruction Set Architecture”. There are two types of this architectural design. First one is RISC (Reduced instruction set computing). The second one is CISC (Complex instruction set computing). However, both differ in various ways. RISC is a design of Central Processing Unit that has the basis of basic instruction set. It gives good performance along with a microprocessor system. In short, it has the ability to execute the commands with the help of some microprocessor cycles per command. https://microcontrollerslab.com/difference-between-risc-and-cisc/ January 23, 2021 9 Central Processing Unit RISC Architecture There are a lot of characteristics related to the RISC architecture, some of them are as follows: 1. Simple set of instructions which are easy to decode and implement. 2. The size of one instruction comes under the size of a single word. 3. Only one clock cycle is required to execute a single instruction, so it is a fast process. 4. The quantity of general purpose register is greater. 5. The addressing modes are quite simple. 6. The variable data types are very less. 7. Its main idea is to achieve pipelining. https://microcontrollerslab.com/difference-between-risc-and-cisc/ January 23, 2021 10 Central Processing Unit CISC Architecture There are a lot of characteristics related to the CISC architecture, some of them are as follows: 1. The instruction set is complex. Hence, it’s decoding. 2. Instructions are normally large due to their complexity. Instructions are normally bigger than one word size. 3. Usually, the compound instructions take greater time than a single clock cycle in their execution. 4. The number of general purpose registers are less. Because this, it performs most operations in the memory itself. 5. The addressing modes are normally complex. 6. The data types are numerous. https://microcontrollerslab.com/difference-between-risc-and-cisc/ January 23, 2021 11 Central Processing Unit RISC x CISC This equation is normally used to check the performance of any computer: This formula clearly tells that the performance of a RISC based architecture is way better than the one operating using CISC architecture. CISC and RISC are two entirely different types of computer architectures. Some of their differences are as follows: https://microcontrollerslab.com/difference-between-risc-and-cisc/ January 23, 2021 12 Central Processing Unit RISC x CISC CISC RISC ADD Ma,Mb LOAD Ra, Ma LOAD Rb, Mb ADD Ra, Rb STORE Ma, Ra Ra, Rb : Register, Ma, Mb : Memory Block http://www.sharetechnote.com/html/EmbeddedSystem_CISC_RISC.html January 23, 2021 13 Central Processing Unit RISC x CISC https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de January 23, 2021 14 Central Processing Unit RISC x CISC https://www.geekfail.net/2013/06/arquitetura-cisc-vs-risc.html January 23, 2021 15 Central Processing Unit The importance of Mnemonic, Operation, Byte and Time https://www.youtube.com/watch?app=desktop&v=xOCjCA3kNgc January 23, 2021 16 Central Processing Unit High Tech Technology Artificial Neural Network to run over Neural Processing Unit Artificial Neural Network Neural Processing Unit https://www.researchgate.net/figure/The-hardware-architecture-of-the-neural-processing-engine-The-left-part-is-the-neural_fig4_336514386 January 23, 2021 17 Central Processing Unit High Tech Technology https://blogs.gartner.com/paul-debeasi/2019/02/14/training-versus-inference/ January 23, 2021 18 Central Processing Unit FSD Chip - Tesla Full Self-Driving Chip (FSD Chip, previously Autopilot Hardware 3.0) is an autonomous driving chip designed by Tesla and introduced in early 2019 for their own cars. Tesla claims the chip is aimed at autonomous levels 4 and 5. Fabricated on Samsung's 14 nm process technology, the FSD Chip incorporates 3 quad-core Cortex-A72 clusters for a total of 12 CPUs operating at 2.2 GHz, a Mali G71 MP12 GPU operating 1 GHz, 2 neural processing units operating at 2 GHz, and various other hardware accelerators. The FSD supports up to 128-bit LPDDR4-4266 memory. https://en.wikichip.org/wiki/tesla_(car_company)/fsd_chip January 23, 2021 19 Central Processing Unit FSD Chip - Tesla The 14 nm process refers to the MOSFET technology node that is the successor to the 22 nm (or 20 nm) node. 14 nm process Timeline MOSFET scaling (process nodes) . 10 µm – 1971 . 6 µm – 1974 . 3 µm – 1977 . 1.5 µm – 1981 Semiconductor . 1 µm – 1984 NVIDIA is secretly device . 800 nm – 1987 . 600 nm – 1990 working on a 5 nm chip fabrication . 350 nm – 1993 . 250 nm – 1996 . 180 nm – 1999 . 130 nm – 2001 . 90 nm – 2003 . 65 nm – 2005 . 45 nm – 2007 . 32 nm – 2009 . 22 nm – 2012 . 14 nm – 2014 . 10 nm – 2016 Kirin 9010 3 nm will be . 7 nm – 2018 Huawei's next flagship . 5 nm – 2020 . Future processor . 3 nm – ~2022 . 2 nm – >2023 https://en.wikichip.org/wiki/tesla_(car_company)/fsd_chip January 23, 2021 20 Central Processing Unit FSD Chip - Tesla Jim Keller, Tesla’s former head of Autopilot hardware and the designer of Tesla’s Self-Driving Computer chip, says that he is confident about solving autonomous driving after working at Tesla. Bio - James B. Keller (born 1958/1959) is a microprocessor engineer best known for his work at AMD and Apple. He was the lead architect of the AMD K8 microarchitecture (including the original Athlon 64) and was involved in designing the Athlon (K7) and Apple A4/A5 processors. He was also the coauthor of the specifications for the x86-64 instruction set and HyperTransport interconnect. From 2012 to 2015, he returned to AMD to work on the AMD K12 and Zen microarchitectures. https://electrek.co/2020/02/07/tesla-self-driving-computer-designer-jim-keller-confident-solving-autonomous-driving/ January 23, 2021 21 Central Processing Unit FSD Chip - Tesla Component GPU NPU Amount 1 2 Model S, Model 3, and Model X 600 GFLOPS 36.86 TOPS Peak Performance (FP32, FP64) (Int8) Total Peak Performance 600 GFLOPS 73.73 TOPS https://en.wikichip.org/wiki/tesla_(car_company)/fsd_chip January 23, 2021 22 Central Processing Unit FSD Chip - Tesla Where is the LIDAR? https://www.quora.com/Why-did-Tesla-develop-their-own-chip-for-self-driving January 23, 2021 23 Central Processing Unit RISC – Reduced Instruction Set Computing .