MOS 6509 DATASHEET REVISION 10/86

WARNING

This datasheet contains an error in the pinout: pins 38 and 40 are swapped. Pin 38 should be ^2 and Pin 40 should be ^1. For verification, see the CBM-II schematics. The error was discovered by Jim Brain on Feb 27, 2018. 59 IRPOESR IH EOY MANAGEMENT MEMORY WITH 6509 C o m m o d o re Semiconductor Gro u p o division of Commodore Business Machines, Inc. 950 Rirrenhouse Rood. Norristown PA 19400 • 215/666-7950 • TWX 510-660-4168 IMMOS

6509 MICROPROCESSOR WITH MEMORY MANAGEMENT

DESCRIPTION The 6509 is a low-cost microprocessor capable of solving a broad range of small-systems and memory management problems at minimum cost to the user.

A memory management system allows for up to One Mega- of memory for ease in down loading languages, operating systems or other data.

The Three-State sixteen-bit Address allows Direct Memory Accessing (DMA) and multi­ processor systems sharing a common memory while the Four-bit Extended Address Register allows for up to one Mega-byte of data storage.

The internal processor architecture is identical to the Commodore Semiconductor Group 6502 to provide software compatibility.

FEATURES OF THE 6509 PIN CONFIGURATION ■ Memory management ■ On board clock logic READY C= 1 40 Z> 02 IN ■ Addressable memory range of up to 1 M IRQ c z 2 39 ZD RESET ■ Single +5 volt supply SYNC cz 3 38 3 0, IN ■ N channel, silicon gate, depletion load nm T cz 4 37 ZJ R/W ■ Eight bit parallel processing AEC cz 5 36 =3 DO ■ 56 Instructions VDD cz 6 35 ZJ D1 ■ Decimal and binary arithmetic A0 c z 7 34 3 D2 ■ Thirteen addressing modes A1 cz 8 33 3 D3 ■ True indexing capability A2 cz 9 32 3 D4 ■ Programmable stack pointer A3 cz 10 6509 31 D5 ■ Variable length stack A4 cz 11 30 D6 ■ Interrupt capability A5 cz 12 29 D7 ■ 8 Bit Bi-Directional Data Bus A6 cz 13 28 SO ■ Program Addressable memory range of up to 65K bytes A7 cz 14 27 PO ■ Direct memory access capability A8 cz 15 26 P1 ■ Bus compatible with M6800 A9 c z 16 25 P2 ■ Pipeline architecture A10 cz 1 7 24 P3 ■ 1 MHz, 2 MHz, and 3 MHz operation A 11 cz 18 23 A15 ■ Use with any type or speed memory A12 cz 19 22 A14 A13 cz 20 21 VSS

10/86 6509 BLOCK DIAGRAM

2 6509 CHARACTERISTICS

MAXIMUM RATINGS

RATING SYMBOL VALUE UNIT This device contains input protection against

SUPPLY VOLTAGE < —0.3 to + 7.0 Vdc O o damage due to high static voltages or electric fields; however, precautions should INPUT VOLTAGE Vin -0 .3 to + 7.0 Vdc be taken to avoid application of voltages higher than the maximum rating. OPERATING TEMPERATURE ta 0 to + 70 C

STORAGE TEMPERATURE t stg -5 5 to + 150 C

ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ± 5%, Vss = 0,T a - 0 to + 70 C)

CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT

Input High Voltage

0 .. 0 2(in) VIH V cc-0.2 Vcc + 1,0 V Vdc Input High Voltage Vdc RES, P0-PriRQ. Data 2.0 —-

Input Low Voltage

. 02(in) VIL 0.2 Vdc RES. P0-P? IRQ. Data —— 0.8 Vdc

Input Leakage Current (Vjn = 0 to 5.25V, Vcc = 5.25V) Logic I in 2.5 /UA 0>02tin) — — 100

Three State (Off State) Input Current (V,n = 0.4 to 2.4V. Vcc = 5.25V)

Data Lines ITSI ■ 10 a*a

Output High Voltage (lOH = -1 OO/uAdc, Vcc = 4.75V) Data. A0-A1 5, R/W, P0-Pr VOH 2.4 Vdc

Out Low Voltage (lOL = 1 SmAdc. Vcc = 4.75V) Data. A0-A15. R/W. P0-P; VOL +0.60 Vdc

Power Supply Current ICC — 125 mA

Capacitance C pF Vjn = 0, Ta = 25 C. 1 = 1 MHz) Logic, P0-P7 Cm 10

Data - 15 A0-A1 5, R/W Cout — 12

0. C0! — 30 50 0 , C 02 — 50 80

3 4 CLOCK TIMING

TIMING FOR WRITING DATA TO MEMORY OR PERIPHERALS

5

1 MHz TIMING 2 MHz TIMING 3 MHz TIMING

ELECTRICAL CHARACTERISTICS (VCC = 5V + 5%, VSS = OV, T4 = 0° -70° C) Clock Timing

CHARACTERISTICSYMBOL MIN. MAXMINMAX MIN.MAX UNITS

_ C ycle Tim e TCYC tooo 500 — 333 — ns

Clock Pulse Width 181 PW H 0, 430 215 145 ns (M easured at VCC - 0 2V) 02 PW H02 470 _ 235 165 — ns

Fall Time, Rise Time _ _ (Measured from 0 2V to VCC - 0.2V) T F. T r 25 15 15 ns

Delay Time between Clocks (M easured at 0.2V) _ _ _ T d 0 0 ns Read/Write Timing (Load = 1 TTL)

CHARACTERISTIC SYM80L MINMAX MINMAXMIN. MAX. UNITS

Read- Write Setup Time from 6509 TRWS - 300 - 150 - 125 ns

Address Setup Timefrom 6509 t ADS - 300 - 150 125 ns

250 ns Memory Read Access Time t a c c - 575 - 300 -

Data Stability Time Period t DSU 100 - 50 - 50 - ns

Data Hold Time-Read t HR 10 - 10 - 10 - ns

Data Hold Time-Wrne T h w 10 - 10 - 10 - ns

Data Setup Time from 6509 t M DS - 200 - 100 - 100 ns h- Address Hold Time I < 10 - 10 - 10 - ns

R/W Hold Time t h r w 10 - 10 - 10 - ns

Port Output Data Valid _ _ _ (Memory Managements t p d w 300 150 125 /JS

RDY Setup Time t r d y 100 - 50 - 15 - ns _ S.O Setup Time r s .o . to o - 50 50 - ns

120 ns SYNC Setup Time from 6509 t s y n c - 350 - 175 -

Address Enable Setup Time t a e s - 75 - 75 - 75 ns

_ 120 ns Data Enable Setup Time t d e s - 120 120 -

Address Disable ’ See Note 1 t a e d - 120 - 120 - 120 ns

Data Disable ’See Note 1 t d e d - 130 - 130 - 130 ns

’ Note 1 — 1TTL Load

C L = 30pf

. SIGNAL DESCRIPTION Clocks (^ ,02) The 6509 requires a two phase non-overlapping clock is held low, writing to or from the microprocessor is that runs at the Vcc voltage level. inhibited. When a positive edge is detected on the input, the microprocessor will immediately begin the reset Address Bus (Ag-A-ig) sequence. The tri-state outputs are TTL compatible, capable of After a system initialization time of six clock cycles, the driving one standard TTL load and 1 30 pf. mask interrupt flag will be set and the microprocessor will load the program counter from the memory vector Data Bus (DQ-D7) locations FFFC and FFFD. This is the start location for Eight pins are used for the data bus. This is a Bi­ program contro' Directional bus. transferring data to and from the device After Vcc reaches 4.75 volts in a power up routine, reset and peripherals. The outputs are tri-state buffers capable must be held low for at least two clock cycles. At this time of driving one standard TTL load and 130 pf. the R/W signal will become valid. Reset When the reset signal goes high following these two This input is used to reset or start the microprocessor clock cycles, the microprocessor will proceed with the from a power down condition. During the time that this line normal reset procedure detailed above.

6 Interrupt Request (IRQ) This TTL level input requests that an interrupt sequence NMI also requires an external 3K resistor to Vcc for begin within the microprocessor. The microprocessor will proper wire-O R operations. complete the current instruction being executed before Inputs IRQ and NMI are hardware interrupt lines that recognizing the request. At that time, the interrupt mask are sampled during 02 (phase 2) and will begin the bit in the Status Code Register will be examined. If the appropriate interrupt routine on the 01 (phase 1) following interrupt mask flag is not set, the m icroprocessor will the completion of the current instruction. begin an interrupt sequence. The Program Counter and Processor Status Register are stored in the stack. The Set Overflow Flag (.S.O.) microprocessor will then set the interrupt mask flag high A NEGATIVE going edge on this input sets the overflow so that no further interrupts may occur. At the end of this bit in the Status Code Register. This signal is sampled on cycle, the program counter low will be loaded from the trailing edge of 01. address FFFE. and program counter high from location FFFF, therefore transferring program control to the SYNC memory vector located at these addresses. This output line is provided to identify those cycles in which the microprocessor is doing an OP CODE fetch. Address Enable Control (AEC) The SYNC line goes high during0i of an OP CODE fetch The Address Bus, Data Bus, and R/W signal are valid and stays high for the remainder of that cycle. If the RDY only when the Address Enable Control line is high. When line is pulled low during the 01 clock pulse in which SYNC low, the Address Bus is in a high-impedance state. This went high, the processor will stop in its current state and feature allows easy DMA and multiprocessor systems. will remain in the state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to Read/Write (R/W) cause single instruction execution. This signal is generated by the microprocessor to control the direction of data transfers on the Data Bus. Memory Management Control (P0-P3) This line is high except when the microprocessor is The four extended address pins, P0-P3, enable the writing to memory or a peripheral device. processorto align to one of sixteen banks of 64K memory space. The use of the instructions: Load A indirect Y Ready (RDY) (B116) and Store A indirect Y (9116), transfers the This input signal allows the user to single cycle the processor from the normal execute mode to the indirect microprocessor on all cycles except write cycles. A mode. In the execute mode, the processor is aligned to a negative transition to the low state during or coincident particular memory bank. The indirect mode aligns the with phase one (0 -|) and up to 100ns after phase two (0 2 ) processor to a predetermined memory block. The will halt the microprocessor with the output address lines contents of the extended address registers is controlled reflecting the current address being fetched. This by software with the execute register at location 0000 and condition will remain through a subsequent phase two indirect register at 0001. (02) in which the Ready signal is low. This feature allows During fetch and execution of the indirect mode microprocessor interfacing with low speed PROMS as instructions, the processor remains in execute mode until well as fast (max. 2 cycle) Direct Memory Access (DMA). data transfer is to occur. At this time the processor If Ready is low during a write cycle, it is ignored until the switches to the indirect mode aligning itself to the new following read operation. memory block. After one cycle the processor returns to the execute mode. Non-Maskabfe Interrupt (NMI) The upper four bits of the data bus are logic “0"s during A negative going edge on this input requests that a a read/write to the extended address registers. Also, non-maskable interrupt sequence be generated within these registers are set to logic “ 1 "s during reset. the microprocessor. The extended address pins are not under control of NMI isan unconditional interrupt. Following completion AEC and are not tri-statable. of the current instruction, the sequence of operations defined for IRQ will be performed, regardless of the interrupt mask flag status. The vector address loaded into the program counter, low and high, are locations FFFA and FFFB respectively, thereby transferring program control to the memory vector located at these addresses. The instructions loaded at these locations cause the microprocessor to branch to a non-maskable interrupt routine in memory.

7 ADDRESSING MODES

Accumulator Addressing Implied Addressing This form of addressing is represented with a one byte In the implied , the address containing the instruction, implying an operation on the accumulator. operand is implicitly stated in the operation code of the instruction. Immediate Addressing In immediate addressing, the operand is contained in the Relative Addressing second byte of the instruction, with no further memory addressing Relative addressing is used only with branch instructions and required. establishes a destination for the conditional branch. The second byte of the instruction becomes the operand Absolute Addressing which is an "Offset" added to the contents of the lower eight bits In absolute addressing, the second byte of the instruction of the program counter when the counter is set at the next specified the eight low order bits of the effective address while instruction. The range of the offset is -128 to +127 bytes from the the third byte specifies the eight high order bits Thus, the next instruction. absolute addressing mode allows access to the entire 65K bytes of addressable memory. Indexed Indirect Addressing In indexed indirect addressing (referred to as [Indirect, X]), the Zero Addressing second byte of the instruction is added to the contents of the X The zero page instructions allow for shorter code and index register, discarding the carry The result of this addition execution times by only fetching the second byte of the points to a memory location on page zero whose contents is the instruction and assuming a zero high address byte. Careful use low order eight bits of the effective address. The next memory of the zero page can result in significant increase in code location in page zero contains the high order eight bits of the efficiency. effective address. Both memory locations specifying the high and low order bytes of the effective address must be in page Indexed Zero Page Addressing zero. (X, Y indexing). Thisform of addressing is used in conjunction with the index register and is referred to as “Zero Page, X" or Indirect Indexed Addressing "Zero Page, Y.” The effective address is calculated by adding In indirect indexed addressing (referred to as [Indirect. Y]), the second byte to the contents of the index register Since this the second byte of the instruction points to a memory location in is a form of "Zero Page" addressing, the content of the second page zero. The contents of this memory location is added to the byte references a location in page zero. Additionally, due to the contents of the Y index register, the result being the low order "Zero Page" addressing nature of this mode, no carry is added eight bits of the effective address. The carry from this addition is to the high order 8 bits of memory and crossing of page added to the contents of the next page zero memory location, boundaries does not occur. the result being the high order eight bits of the effective address.

Indexed Absolute Addressing Absolute Indirect (X, Y indexing). Thisform of addressing is used in conjunction The second byte of the instruction contains the low order with X and Y index register and is referred to as "Absolute, X." eight bits of a memory location The high order eight bits of that and "Absolute, Y." The effective address is formed by adding memory location is contained in the third byte of the instruction. the contents of X and Y to the address contained in the second The contents of the fully specified memory location is the low and third bytes of the instruction. This mode allows the index order byte of the effective address. The next memory location register to contain the index or count value and the instruction to contains the high order byte of the effective address which is contain the base address. This type of indexing allows any loaded into the sixteen bits of the program counter. location referencing and the index to modify multiple fields resulting in reduced coding and execution time INSTRUCTION SET—ALPHABETIC SEQUENCE

ADC Add Memory to Accumulator with Carry LDA Load Accumulator with Memory AND "AND" Memory with Accumulator LDX Load Index X with Memory ASL Shift Left One Bit (Memory or Accumulator) LDY Load Index Y with Memory Shift One Bit Right fMemory or Accumulator) BCC Branch on Carry Clear LSR 8CS Branch on Carry Set NOP No Operation 8EQ Branch on Result Zero ORA "OR" Memory with Accumulator BIT Test Bits in Memory with Accumulator BMI Branch on Result Minus PHA Push Accumulator on Stack BNE Branch on Result not Zero P HP Push Processor Status on Stack BPL Branch on Result Plus PLA Pull Accumulator from Stack BRK Force Break PL P Pull Processor Status from Stack BVC Branch on Overflow Clear ROL Rotate One Bit Left (Memory or Accumulator) BVS Brancn on Overflow Set ROR Rotate One Bit Right (Memory or Accumulator) CLC Clear Carry Flag RTI Return from Interrupt CLD Clear Decimal Mode RTS Return from Subroutine CLI Clear interrupt Disable Bit SBC Subtract Memory from Accumulator with Borrow CLV Clear Overflow Flag SEC Set Carry Flag CMP Comoare Memory ana Accumulator SED Set Decimal Mode CPX Compare Memory ana Index X SEI Set Interrupt Disable Status CPY Compare Memory and index Y STA Store Accumulator m Memory DEC Decrement Memory Oy One STX Store Index X in Memory DEX Decrement Index X Oy One STY Store Index Y m Memory DEY Decrement Index Y by One TAX Transfer Accumulator to Index X EOR 'Exc!usive-or' Memory with Accumulator TAY Transfer Accumulator to Index Y TSX Transfer Stack Pointer to Index X INC increment Memory by One TXA Transfer Index X to Accumulator INX Increm eni Inoex X by One TXS Transfer Index X to Stack Register INY increment tnaex Y by One TY A Transfer Index Y to Accumulator JMP Jump to New Location JSR Jump to New Location Saving Return Address PROGRAMMING MODEL 7 0 LZ A ACCUMULATOR - EEH PROCESSOR STATUS REG "P" 7 0 IND£ x REGiS'ER CARRY 1 = TRUE ( Y Z E R O 1 = RESULT ZERO IRQ DISABLE : = DISABLE !__ X IN OF a Rf Gi^'fU DECIMAL MODE 1 = TRUE 15 7 u BRK COMMAND 1 PCH I..... PCL PROGRAM CuU'. 8 7 0 O V E R F L O W 1 = T R U E LI ... S STAi...* POiP.it R NEGATIVE 1 = N E G

INSTRUCTION SET — OP CODES, Execution Time, Memory Requirements A A NDD c A-V-C-»AA *. M -> - ,! ,4; E CS c C —\ 7 flh-0 B c s BRANCH ON C = 0’ -2 -2 3 RA?CH ON Z = ' A M BRANCH ON N - '

5RAN'CH ON Z t * BRANCH ON U - d

SRAf.CH CN V - BPAf ;r> ON v -

JUMP T0 NEW LOG JUMP SUE ‘.1 -* A

9 6509 MEMORY MAP

FFFF

ADDRESSABLE EXTERNAL MEMORY

STACK 0200 01 FF POINTER 01 FF INITIALIZED

s t a c k

P age 1

0100 OOFF

. P age 0

0001 ON CHIP REGISTERS INDIRECT REGISTER 0000 0000 EXECUTE REGISTER

COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

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