HARDWARE ACCELERATOR for ELIAS GAMMA CODE by Karuna
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HARDWARE ACCELERATOR FOR ELIAS GAMMA CODE by Karuna Ranganathapura Chandrai Gowda A thesis submitted to the Graduate Council of Texas State University in partial fulfillment of the requirements for the degree of Master of Science with a Major in Engineering August 2017 Committee Members: Semih Aslan, Chair Dan Tamir Stan McClellan COPYRIGHT by Karuna Ranganathapura Chandrai Gowda 2017 FAIR USE AND AUTHOR’S PERMISSION STATEMENT Fair Use This work is protected by the Copyright Laws of the United States (Public Law 94-553, section 107). Consistent with fair use as defined in the Copyright Laws, brief quotations from this material are allowed with proper acknowledgment. Use of this material for financial gain without the author’s express written permission is not allowed. Duplication Permission As the copyright holder of this work I, Karuna Ranganathapura Chandrai Gowda, authorize duplication of this work, in whole or in part, for educational or scholarly purposes only. DEDICATION To my Advisor and Mentor, thank you for your valuable guidance and support, without which, this work would not have been possible. To my Family, thank you for your unconditional love and tremendous support. ACKNOWLEDGEMENTS I would first like to thank my thesis advisor Dr. Semih Aslan of the Ingram School of Engineering at Texas State University. Dr. Aslan always was available to provide his valuable inputs whenever I ran into a trouble spot or had a question about my research or academics. He always enabled me with industry standard tool suite, which enhanced this research work and exposed me to the latest technology. He consistently allowed this thesis to be my work but steered me in the right direction whenever I needed it. I would also like to express my sincere gratitude to my thesis committee member Dr. Dan Tamir of the Computer Science Department at Texas State University. Amidst his busy schedule, he always supported my work with his insightful inputs. His valuable ideas unblocked me at critical junctures of this thesis work. Thank you for your kind and invaluable support. I would like to thank Dr. Stan McClellan, Director Ingram School of Engineering at Texas State University for his continued support through this research. I would like to express my sincere gratitude to Dr. Vishu Viswanathan, Graduate Advisor at Ingram School of Engineering at Texas State University. He was always available to support with all the degree related processes and enabled me to maintain focus at school work. He always provided his valuable advice at difficult times, which enabled me to see opportunities amidst the challenges. I immensely thank Dr. Hamid Mahmoodi at San Francisco State University. He taught me everything I know about the HDL design. This knowledge was crucial in v developing and implementing the experiments. I would like to thank my friend Ilya Wagner at Intel Corporation, who answered my HDL design questions that helped in resolving issues in the experiments. Finally, I must express my profound gratitude to my husband and children for providing me with unfailing support and continuous encouragement throughout my years of study and through the process of researching and writing this thesis. This accomplishment would not have been possible without them. Thank you. vi TABLE OF CONTENTS Page 1. INTRODUCTION ...................................................................................................1 2. BACKGROUND .....................................................................................................5 3. LITERATURE REVIEW ......................................................................................19 4. METHODOLOGY ................................................................................................21 5. EXPERIMENTAL SETUP ....................................................................................26 6. DESIGN IMPLEMENTATION ............................................................................37 7. DESIGN VALIDATION .......................................................................................53 8. RESULT EVALUATION AND COMPARISON.................................................60 9. CONCLUSION AND FURTHER RESEARCH .................................................105 vii LIST OF TABLES Table Page 1. Examples of Elias Gamma Encoding ............................................................................7 2. Example of Data Packing...............................................................................................8 3. Example of Data Packing with MSB First ...................................................................10 4. Encode Engine – FSM State Transition Table .............................................................39 5. Pack Engine – FSM State Transition Table .................................................................42 6. Fundamental Design: Decode Engine – FSM State Transition Table .........................46 7. Interconnect Design: EncodePack Engine - FSM State Transition Table ...................50 8. Software Implementation: Best and Worst Case Compression Latencies ...................61 9. Software Implementation: Summary of Compression Efficiency Metrics ..................62 10. Software Implementation: Best and Worst-Case Decompression Latencies ...............63 11. Software Implementation: Summary of Decompression Efficiency Metrics ..............64 12. Expr01: Fundamental Design: Best and Worst Case Compression Latencies ............67 13. Expr01: Fundamental Design: Summary of Compression Efficiency Metrics ...........68 14. Compression Data Comparison: HW Implementation in Expr01 vs Software Implementation .....................................................................................71 15. Expr01: Fundamental Design: Best and Worst Case Decompression Latencies .........72 16. Expr01: Fundamental Design: Summary of Decompression Efficiency Metrics ........73 17. Decompression Data Comparison: HW Implementation in Expr01 vs Software Implementation .....................................................................................76 18. Expr02: Interconnected Design: Best and Worst Case Latencies ................................79 viii 19. Expr02: Interconnected Design: Summary of Compression Efficiency Metrics .........79 20. Compression Data Summary: SW vs Expr01 vs Expr02.............................................85 21. Expr03: Best and Worst Case Latencies ......................................................................90 22. Expr03: Summary of Compression Efficiency Metrics ...............................................91 23. Compression Data Summary: SW vs Expr01 vs Expr02 vs Expr03 ...........................96 24. Performance Summary: Latency and Throughput .....................................................101 25. Performance Summary: Cost and Power ...................................................................101 26. Other Authors' Work: Comparative Perspective .......................................................104 ix LIST OF FIGURES Figure Page 1. Hardware Accelerator Block Diagram ...........................................................................5 2. Top-down Design Hierarchy ........................................................................................11 3. Bottom-up Design Hierarchy .......................................................................................12 4. ASIC Design and Implementation Flow ......................................................................13 5. FPGA Design Flow ......................................................................................................17 6. Hardware Accelerator Block Diagram .........................................................................22 7. Hardware Accelerator Design Validation Methodology .............................................24 8. Hardware accelerator Test Setup .................................................................................26 9. Test Bench Components ..............................................................................................27 10. 0.5 Gaussian Probability Distribution Data Plot ..........................................................29 11. Poisson Distribution Data Plot .....................................................................................29 12. Vivado™ Design Suite ................................................................................................31 13. Vivado Project Manager ..............................................................................................32 14. Vivado Simulation Environment .................................................................................33 15. Vivado™ RTL Analysis Tool ......................................................................................34 16. Vivado Synthesis Tool .................................................................................................35 17. Vivado Implementation Tool .......................................................................................36 18. Fundamental Design – Block Diagram ........................................................................38 19. Fundamental Design – Finite State Machine (FSM) ...................................................39 x 20. Fundamental Design: Encode Engine: Architectural Diagram ....................................41 21. Pack Engine – FSM .....................................................................................................42 22. Fundamental Design: Pack Engine: