United States Patent (19) 11 Patent Number: 4.942,519 Nakayama 45 Date of Patent: Jul. 17, 1990 54 HAVING ASLAVE Motorola, MC 68881 Floating-Point Coprocessor CAPABLE OF CHECKING User's Manual, 1985, 1-6, 1-7, 5–2. ADDRESS MAPPNG Primary Examiner-Gary V. Harkcom 75) Inventor: Takashi Nakayama, Tokyo, Japan Assistant Examiner-Michael A. Jaffe 73) Assignee: NEC Corporation, Tokyo, Japan Attorney, Agent, or Firm-Foley & Lardner, Schwartz, 21 Appl. No.: 947,344 Jeffery, Schwaab, Mack, Blumenthal & Evans (57 ABSTRACT (22 Filed: Dec. 29, 1986 A coprocessor device having a virtual storage system (30) Foreign Application Priority Data comprises a master , a slave micro Dec. 25, 1985 JP Japan ...... 60-294.285 processor controlled by the master microprocessor to 51) Int. Cl...... G06F 15/16; G06F 13/00 execute an operation designated by instructions for the 52 U.S. C...... 364/200; 364/230.4; slave microprocessor, a main storage for storing infor 364/228.6 mation and data for the master microprocessor and the 58) Field of Search ...... 364/132, 200 MS File, slave microprocessor, and an external storage coupled 364/900 MS File, 200,900 to the main storage for storing information and data for the master microprocessor and/or the slave micro (56) References Cited processor. The master microprocessor has a circuit for U.S. PATENT DOCUMENTS detecting whether or not the memory location required 4,041,471 8/1977 Krossa et al...... 364/200 by a certain instruction is physically present in the main 4,099,236 7/1978 Goodman et al...... 364/200 storage. This detecting circuit operates to enable access 4,149,244 4/1979 Anderson et al...... 364/200 to the main storage or to generate an interrupt to trans 4,270,167 5/1981 Koehler et al...... 364/200 fer information and/or data from the external storage to 4,509,116 4/1985 Lackey et al...... 364/200 4,547,849 10/1985 Louie et al...... 364/200 the main storage, in accordance with the content of the 4,700,292 10/1987 Campanini...... 364/200 instruction. There is also provided a circuit for feed 4,750,110 6/1988 Mothersole et al...... 364/200 backing to the master microprocessor the decoded in 4,763,242 8/1988 Lee et al...... 364/200 struction for the slave microprocessor which includes address which is not physically present in the main OTHER PUBLICATIONS storage, so that it is processed by the detecting circuit. Motorola, MC68020 32-Bit Microprocessor User's Manual, 1984, 1985, 1-2, 1-7, 8-3, 8-7. 19 Claims, 2 Drawing Sheets

EFFECTIVE STORAE ADDRESS MANAGEMENT INSTRUCTION OPERATION DECODER EXECUTION r UNIT FEEDBACK COMMAND PORT PORT

Ext. 31 STORAGE U.S. Patent Jul.17, 1990 Sheet 1 of 2 4.942,519

JAWTS HOSS300}}d

HBISWW HOSS300}}d U.S. Patent 4.942,519

HOSS300\ldBAVIS

N0|1003X3 LINÍT 4.942,519 1 . 2 simultaneously with the master processor in response to COPROCESSOR HAVING ASLAVE PROCESSOR the decode condition signal and executes the same. CAPABLE OF CHECKING ADDRESS MAPPNG Operation of the master processor and the slave pro cessor with the instructions for slave processor depends BACKGROUND OF THE INVENTION 5 on the presence of memory operand and on whether the 1. Field of the Invention memory operand is to be read or written. The present invention relates to a microprocessor (1) In case the memory operand exists: device having a virtual storage system therein, more The master processor does not execute the instruc specifically to a control system for controlling a slave tions. The slave processor executes the operation desig processor which is connected to the external part of a 10 nated by the instruction for the internal register oper microprocessor to execute a portion of an instruction and. (2) In case there exists memory operand set. The master processor calculated the operand address 2. Description of the related art and drives the bus cycle to read one word of a first There exists a limit on the number of devices which address (for example 16 bits) out of the main storage. can be integrated in a one-chip microprocessor com 15 The slave processor supervises the address/data com mon bus and the control bus, and reads the first address posed of a large scale (LSI). It is, of the operand and data by one word and stores them therefore, difficult for a single one-chip microprocessor when the master processor drives the read bus cycle. to execute high level instructions such as floating point The operation of the slave processor thereafter is classi arithmetic at high speed. This is why an instruction set 20 fied into three cases depending on the reading and writ is classified into two kinds, each of which is executed in ing conditions. a master processor and a slave processor respectively. (2-1) In the case of reading the memory operand of A master processor is a processor which can operate one word: as a (CPU) independently of the The slave processor executes the operation desig slave processor. A slave processor is a processor which 25 nated by the instruction for the memory operand of one executes instructions in place of a processor under con word read in and the internal register operand if neces trol thereof. Such a slave processor executes mainly sary, and stores the operation result in the internal regis high level instructions such as floating point arithmetic. ter. By connecting a slave processor to a computer system (2-2) In the case of reading the memory operand of in which a master processor operates as CPU, a user can 30 more than two words: expand the institution set. Intel 8086 and Intel 8087 are The slave processor obtains the right to use the ad used as the master processor and slave processor com dress/data bus and the control bus from the master posed of a one-chip LSI respectively. processor in response to the handshake signal. The slave A conventional microprocessor device comprises a processor drives the read bus cycle by itself to read the master processor, a slave processor and a main storage. 35 remainder of the memory operand. Then the slave pro The master processor and the slave processor share an cessor executes the operation designated by the instruc address/data common bus and a control bus to access tion for the read out memory operand and the internal the main storage. Addresses and data by which the register operand if necessary, and stores the operation master processor or slave processor accesses the main result in the internal register. storage are transmitted in time division through the (2-3) In the case of writing to the memory operand: address/data common bus. A handshake signal line is The slave processor executes the operation desig connected between the master processor and the slave nated by the instruction for the internal register oper processor. The master processor, moreover, supplies an and. Then the slave processor obtains the right to use instruction decode condition signal to the slave proces the address/data bus and the control bus from the mas sor so that instructions can be decoded simultaneously 45 ter processor in response to the signal, and writes the in both processors. operation result to the memory operand. Instruction sets executed by the above microproces The above-mentioned conventional microprocessor sor system are classified into instructions for the master system does not support the virtual storage. As a micro processor and instructions for the slave processor. processor becomes of higher performance, demand for Instructions for the master processor are the instruc 50 the virtual storage which provides virtually bulk stor tions by which the processor executes operation and age by using the external storage besides the main stor accesses the main storage The slave processor super age of the limited memory is raised, especially the vir vises the address/data common bus and the control bus, tual storage of paging method. and fetches instructions simultaneously with the master In the Virtue storage of the paging method, the ad processor. The slave processor, furthermore, decodes 55 dress space which the programmer imagines (virtual the instructions for the master processor simultaneously address space) is divided into of several thousand bytes, with the master processor, in response to the decode and the address space is mapped to the address space of condition signal from the master processor. The slave the main storage (real address space) page after page. processor, however, does not execute the operation. The page which is mapped to the real address space is a Instructions for the slave processor are the instruc portion of all the pages in the virtual space, and the tions by which the slave processor executes operation. remainder is undefined or exists in an external storage. The master processor deals with a group of instructions In the virtual storage of the paging method, memory is for the slave processor as a single instruction (hereinaf protected by adding an attribute indicating whether ter referred to as "ESC instruction”). The slave proces reading out of or writing to the storage can be or cannot sor supervises the address/data common bus and the 65 be executed to every page. control bus, and fetches instructions simultaneously In a microprocessor supporting the virtual storage of with the master processor. The slave processor, further the paging method, the following three checks are thus more, decodes the instructions for the slave processor required in case of accessing the memory operand. 4,942,519 3 4. memory protect system inside the master processor in (I) Paging over check case the memory operand is included over two succes In the paging over check, a check is made as to sive pages. whether the memory operand is included in a single page, or included over two successive pages. In case the Disadvantage 3 memory operand is included over two successive pages Once it is clarified that the memory operand does not (paging over), address mapping check and memory exist in the main storage, but in the external storage protect check described hereinafter are carried out on through the address mapping check executed, the mas the second page as well. In carrying out the paging over ter processor stops execution of the instruction and check, information is required on the first address and 10 transmits the page including the memory operand from the data length of the memory operand. the external storage to the main storage. Then the mas ter processor has to execute again the instruction (II) Address mapping check stOpped on the way. The slave processor has, however, In the address mapping check, a check is made as to already started execution of instructions for the slave whether the page indicated by the virtual address exists 5 processor just after the master processor finishes decod in the main storage (real address space) or in the exter ing ESC instructions in the conventional system. It is nal storage after the address mapping from the virtual not, therefore, possible to carry out the correct address address to the real address is executed. In carrying out mapping check. the address mapping check, information is required on The above disadvantages are all concerned about the the virtual address of the page including the memory 20 virtual storage, but there still exist some other disadvan operand. tages. (III) Memory protect check Disadvantage 4 In the memory protect check, a check is made as to In the case of using a master processor having an whether or not it is allowed to access the including the 25 address bus and a data bus independent to each other memory operand. In carrying out the memory protect instead of a common bus transmitting addresses and check, information is required on the virtual address of data in time division, the number of the external pins Of the page including the memory operand and on the slave processor LSI increases because an address whether reading or writing takes place for the memory bus and a data bus are provided independently to each operand. 30 other in the slave processor as well. To utilize the property of software executed by the master processor and slave processor which do not Disadvantage 5 support the virtual storage effectively, the master pro As mentioned above, the slave processor supervises cessor and slave processor supporting the virtual stor the address/data common bus and control bus, and age have to be able to execute the same instruction set as 35 executes instruction fetching and instruction decoding the conventional one. In forming a master processor in simultaneously with the master processor. It is, how which the above address mapping system and memory ever, necessary to supply instruction decode condition protect system are incorporated in a LSI chip in order signals to the slave processor, in the master processor in to support the virtual storage of paging method, the which the multistage pipelining is executed The number conventional control system has the following disad 40 of the external pins, therefore, increases furthermore vantages and cannot control the slave processor in a both in the master processor LSI and the slave proces right way. sor LSI. Disadvantage 1 SUMMARY OF THE INVENTION It is necessary for the master processor to recognize 45 The present invention has an object to provide a whether the memory operand is to be read or written in microprocessor device which has dissolved the above order to execute the memory protect check using a mentioned drawbacks of the conventional microproces memory protect system incorporated in the master pro sor device. cessor. In case of executing instructions for the slave Accordingly, it is an object of the present invention processor by the conventional system, the slave proces 50 to provide a microprocessor device in which a master sor can judge whether the memory operand is to be processor can execute a memory protection check. read or written through decoding, but the master pro Another object of the present invention is to provide cessor does not decode such instructions and thus can a microprocessor in which a master processor can exe not execute the memory protection check. cute a paging over check and a slave processor can 55 execute a address mapping check and protection check Disadvantage 2 on the second page in case of paging over. To carry out the paging over check for the memory Still another object of the present invention is to operand, information is required not only on the first provide a microprocessor device in which a slave pro virtual address of the operand but also on the data cessor can execute address mapping check properly length of the operand. In case of executing instructions even after the slave processor starts to execute instruc for the slave processor by the conventional system, the tions for the slave processor. master processor cannot execute the paging over check Still another object of the present invention is to because the master processor cannot recognize the data provide a microprocessor device in which a master length of the memory operand. On the contrary, the processor LSI and a slave processor LSI have a small slave processor can execute the paging over check but 65 number of the external pins. does not have means for executing the address mapping According to the present invention, there is provided check and memory protect check on the second page a control system for a microprocessor device, said mi making use of the address mapping system and the croprocessor device including a first microprocessor, a 4,942,519 5 6 second microprocessor being controlled by the first microprocessor, so that the instruction decoder of the microprocessor to execute the operation of a portion of second microprocessor being adapted to receive the instruction sets, a main storage for storing information output of the command port and operative to decode and data for the first microprocessor and the second only the instructions for the second microprocessor; microprocessor, an external storage associated to the and main storage for storing information and data for the a feedback port being coupled to the instruction de first microprocessor and/or the second microprocessor, coder of the second microprocessor to receive the de and a bus coupling the first microprocessor, the second coded instructions for the second microprocessor, and microprocessor and the main storage to each other so as operative to store the information out of the instruction to transfer data and information to each other; 10 decoder temporarily and feedback the stored informa the first microprocessor including a bus unit for con tion to the first microprocessor in response to a control trolling the status of the bus with respect to the second signal given by the first microprocessor. microprocessor, the main storage and the external stor The feedback means may further include: age, an instruction decoder for decoding instructions a decoder being coupled to the address decoder and for the first microprocessor and an operation execution 15 unit for executing instructions for the first microproces operative to decode the select signal and output a con sor with data and/or information stored in the memory trol signals for controlling the second microprocessor location indicated by the instruction; and the feedback means. Such control signals outputted the second microprocessor including an instruction from the decoder may include: decoder for decoding the instructions for the second 20 a starting signal to an operation of the microprocessor and an operation execution unit for second microprocessor; executing the same with data and/or information store a read control signal to the feedback port; and in the memory location indicated by the instruction; a write control signal to the command port. the control system comprising According to a embodiment of the present invention, means for detecting whether or not the memory loca 25 the first microprocessor is composed of a one-chip large tion required by a certain instruction is physically pres scale integrated circuit in which the detecting means is ent in the main storage, said detecting means being incorporated. mounted in the first microprocessor and associated to The second microprocessor is preferably composed the bus for enabling access to the main of a one-chip large scale integrated circuit in which the storage or for generating an interrupt to transfer infor 30 feedback means is incorporated. mation data from the external storage to the main stor According to the present invention, there is also pro age, in accordance with the content of the instruction; vided a microprocessor device having a virtual storage and system and comprising: means for feedbacking to the first microprocessor the a master microprocessor including a bus control unit decoded instruction for the second microprocessor 35 for controlling the status of a bus, an instruction de which includes address which is not physically present coder for decoding instructions for the master micro in the main storage, so as to be processed by the detect processor and an operation execution unit for executing ing means. operation designated by the instructions for the master According to an preferred embodiment of the present microprocessor with data and/or information stored in invention, the whole memory locations of the main the memory location indicated by said instructions; storage and the external storage are mapped into a vir a slave microprocessor being controlled by the mas tual memory of the paging method, and the instructions ter microprocessor to execute the operation designated are assigned with a virtual address. by instructions for the slave microprocessor, and in According to an embodiment of the present inven cluding an instruction decoder for decoding the instruc tion, the detecting means comprises: 45 tions for the slave microprocessor and an operation an effective address calculation unit coupled to the execution unit for executing the operation designated bus control unit and for calculating the effective address thereby with data and/or information stored in the of the memory location required by the instruction and memory location indicated by said instructions for the executing the paging over check; slave microprocessor; a store management unit coupled to the effective 50 a main storage for storing information and data for address calculation unit and for mapping the memory the master microprocessor and the slave microproces location required by the instruction into physicladdress SOr; in the main memory or I/O address. an external storage associated to the main storage for The control system of the present invention may storing information and data for the master micro comprise an address decoder coupled between the bus 55 processor and/or the slave microprocessor; and control unit and the second microprocessor and for a bus coupling the master microprocessor, the slave generating a select signals in response to the status of microprocessor and the main storage to each other so as the signal outputted from the bus control unit. to transfer data and information to each other; According to embodiment present invention, the the microprocessor device further comprising: address decoder is adapted to receive from the bus 60 means for detecting whether or not the memory loca control unit a signal indicating the effective address of tion required by a certain instruction is physically pres the main storage or I/O address and to output a select ent in the main storage, said detecting means being signal in response to the I/O address. mounted in the master microprocessor and associated to On the other hand, the feedbacking means may in the bus control unit for enabling access to the main clude: 65 storage or for generating an interrupt to transfer infor a command port coupled to the bus and operative to mation and/or data from the external storage to the read instructions for the second microprocessor out of main storage, in accordance with the content of the the bus in response to a control signal given by the first instruction; and 4.942,519 7 8 means for feedbacking to the master microprocessor ter processor 10 and the slave processor 20. An external the decoded instruction for the slave microprocessor storage 31 is provided and associated to the main stor which includes address which is not physically present age 30. The main storage 30 is necessarily accessed by in the main storage, so as to be processed by the detect the master processor 10. The microprocessor device ing means. further includes an address decoder 50 which executes The above and other objects, features and advantages I/O mapping of the slave processor 20 to the master of the present invention will be apparent from the fol processor 10 so that data and status information are lowing description of preferred embodiment of the transferred to the slave processor 20. invention with reference to the accompanying drawings The master processor 10 includes an instruction de BRIEF DESCRIPTION OF THE DRAWINGS 10 coder 11. The instruction decoder 11 is coupled to an effective address calculation unit 12 which receives the FIG. 1 is a block diagram of a conventional micro output of the instruction decoder 11 and executes ad processor device, and dress calculation therefrom. The effective address cal FIG. 2 is a block diagram of a control system for a culation unit 12 is coupled to a storage management unit microprocessor device in accordance with the present 15 13. The storage management unit 13 the virtual address invention. from the effective address calculation unit 12 and exe DESCRIPTION OF THE PREFERRED cutes mapping thereof to the real address and simulta EMBODIMENT neously executes the memory protection check. The storage management unit 13 thus supports the virtual Referring to FIG. 1, a conventional microprocessor 20 device will be explained. storage of the paging method. The instruction decoder The microprocessor device shown in FIG. 1 com 11 is coupled also to an operation execution unit 14. The prises a master processor 1, a slave processor 2 and a operation execution unit 14 executes the operation des main storage 3, which are coupled to each other by ignated by the instruction for the master processor. The address/data common bus 4 and a control bus 5. Ad 25 storage control unit 13 is coupled to a bus control unit dresses and data by which the master processor 1 or the 15. The bus control unit 15 drives an address bus 41 and slave processor 2 accesses the main storage 3 are trans a control bus 42, and executes sending data to and re mitted in time division through the address/data com ceiving data from the slave processor 20 or the main mon bus 4. A handshake signal line 6 is connected be storage 30 through a data bus 40. tween the master processor 1 and the slave processor 2 30 Thus the data bus 40 is shared by the master proces so that the slave processor 2 operates in response to the sor 10 and the slave processor 20 to access the main handshake signal. The master processor 1, moreover, storage 30. The address bus 41 couples bus control unit supplies an instruction decode condition signal 7 to the 15 with an address decoder 50, and transmits the real slave processor 2 so that instructions can be decoded address or the I/O address to the address decoder 50. simultaneously in both processors. 35 The control bus 42 couples the bus control unit 15, the The microprocessor system executes an instruction main storage 30 and the address decoder 50 to each set including instructions for the master processor and other. The control bus 42 transmits information indicat instructions for the slave processor. ing the data sender and the data receiver on the data bus Instructions for the master processor are the instruc 40 and information indicating the timing of the bus tions by which the master processor 1 executes opera cycle. The address decoder 50 outputs a select signal 43 tion and accesses to the main storage 3. The slave pro to the slave processor 20 in response to the control bus cessor 2 supervises the address/data common bus 4 and signal. the control bus 5, and fetches instructions simulta The slave processor 20 includes a decoder 25 which neously with the master processor 1. The slave proces receives the select signal 43 and decodes the same. The sor 2, furthermore, decodes the instructions for the 45 decoder 25 outputs at least a write control signal 26 to master processor simultaneously with the master pro the command port 21, a read control signal 27 to the cessor 1 in response to the decode condition signal 7 feedback port 23 and a starting signal 28 to the opera from the master processor. For these instructions, how tion execution unit 24. ever, the slave processor 2 does not execute operation. The slave processor 20 includes a command port 21. Instructions for the slave processor are the instruc 50 The command port 21 is coupled to the data bus 40 so tions by which the slave 2 executes operation. The that instructions for the slave processor are written to master processor 1 deals with a group of instructions for the command port 21 under the instruction of the mas slave processor as "ESC instruction'. The slave proces ter processor 10 as described hereinafter. The command sor 2 supervises the address/data common bus 4 and the port 21 is associated to an instruction decoder 22. The control bus 5, and fetches instructions simultaneously 55 instruction decoder 22 is an executive instruction de with the master processor 1. The slave processor 2, coder for instructions for slave processor. The instruc furthermore, decodes and executes instructions for the tion decoder 22 is coupled to an feedback port 23 to slave processor in response to the handshake signal 6. output the decoded instruction. The feedback port 23 Turning to FIG. 2, there is shown a microprocessor temporarily stores the information indicating the data device in accordance with the present invention. length of the memory operand outputted by the instruc The microprocessor device shown in FIG. 2 com tion decoder 22 and the information on reading or writ prises a master processor 10 including hardware for ing. The feedback port 23 is coupled to the data bus 40 supporting the virtual storage and a slave processor 20 so that the stored information is transmitted to the mas which is controlled by the master processor 10. Both ter processor 10 through the data bus 40. The instruc processors 10 and 20 are composed of one-chip LSI and 65 tion decoder 22 is also coupled to an operation execu execute high level operations jointly with one another. tion unit 24 to output the decoded instruction thereto. The microprocessor device further includes a main The operation execution unit 24 is coupled to the data storage 30 which stores programs and data for the mas bus 40 and executes instructions for the slave processor. 4,942,519 9 10 The processing process for executing instructions for cycle. As a result, the starting signal 28 of the operation the master processor and for slave will be described execution unit 24 becomes active. The operation execu hereinafter with reference to FIG. 1. tion unit 24 starts execution in response to the active starting signal 28 with the internal register operand (a) Execution of instructions for the master processor thereof (b-2) In case a memory operand exists: The instruction for the master processor read out of The operation execution unit 14 controls the bus the main storage 30 is decoded by the instruction de control unit 15 so that the master processor 10 reads out coder 11 in the master processor 10. The operation is the I/O address to which the feedback port 23 is executed by the operation execution unit 14. In case a mapped. Thus the master processor 10 recognizes the memory operand is included in the instruction, the vir- 10 data length of the memory operand and whether the tual address is calculated by the effective address calcu memory operand is to be read or written. The virtual lation unit 12 and the calculated virtual address is address calculation and paging over check are executed mapped to the real address by the storage management by the effective address calculation unit 12. Address 13. The real address is outputted and transmitted to the mapping check and memory protection check (on the main storage 30 through the bus control unit 15, Thus 15 second page as well in case of paging over) are executed sending and receiving operand is exchanged between by the storage management unit 13. In case the memory the operation execution unit 14 and the main storage 30 operand exists in the main storage and it is possible to to execute the instruction. The paging over check is access the memory operand, the master processor 10 executed by the effective address calculation unit 12 drives the I/O bus cycle again and the starting signal 28 simultaneously with execution of the virtual address 20 of the operation execution unit 24 is turned active. calculation. On the other hand, address mapping check In case the page including the memory operand exists and memory protection check are executed by the stor in the external storage, the master processor 10 executes age management unit 13 simultaneously with execution an exception to transmit the page to the main storage of mapping to the real address. In this case, the above from the external storage. The operation execution unit checks are executed on the second page if the memory 25 24 of the slave processor 20, however, has not yet operand is included over two successive pages. Thus started the operation because the starting signal 28 re executing of address mapping check and memory pro mains inactive. The instruction for slave processor thus tection check clarifies whether or not it is possible to can be executed again in a right way. access the main storage. Read/write to the main storage The processing of the master processor 10 and the can be executed if it is possible to access the main stor 30 slave processor 20 after the above processing is classi age. If it is not possible to access the main storage, no fied into two forms. operation is executed in the operation execution unit 14 and the internal interruption (exception) occurs in the (b-2-1) In the case of reading the memory operand master processor 10. If the page including the memory The master processor 10 drives the bus cycle in operand exists in an external storage (not shown in the 35 which the memory operand is transmitted from the drawings), the page is transmitted to the main storage main storage 30 to the slave processor 20. The operation by the exception processing program. Then the instruc execution unit 24 of the slave processor 20 starts the tion decoding operation on the instruction concerned operation in response to the starting signal 28 The oper about the above exception will be executed again. Dur ation execution unit 24 executes the operation desig ing this period, the slave processor 20 starts no process nated by the instruction with the memory operand read ing at all because the select signal 43 of the slave proces out and if necessary the internal register operand sor 20 is not effective. thereof, and stores the operation result in the internal register. (b) Instruction for the slave processor The master processor 10 deals with a group of in- 45 (b-2-2) In the case of writing to the memory operand structions defined as instructions for the slave processor The Operation execution unit 24 of the slave proces as a single instruction (ESC instruction). If the instruc sor 20 executes the operation designated by the instruc tion decoder 11 of the master processor 10 finds the tion with the internal register operand in response to the given instruction the ESC instruction by decoding, the starting signal 28. The master processor 10 drives the operation execution unit 14 controls the bus control unit 50 bus cycle in which the operation result is transmitted 15 to write an instruction code of the ESC instruction to from the slave processor 20 to the main storage 30. the I/O address in which the command port of the slave As above described, the control system for the micro processor 20 is mapped. The select signal 43 from the processor device according to the present invention address decoder 50 and the command port write control comprises, signal 26 from the decoder 25 are turned active, and 55 means for feedbacking the of the instruction decoder then the instruction code on the data bus 40 is written of the slave processor to the master processor; and tO the command port 21 and the instruction decoder 22 means for controlling the start of instruction decod decodes the instruction for the slave processor. The ing of the slave processor and the start of the operation operation execution unit 24 of the slave processor 20, executing respectively by the master processor. On this however, has not started its execution yet at this point 60 viewpoint, the microprocessor device has the following of time. three advantages. (1) The virtual storage can be sup The processing of the master processor 10 and the ported with instructions for slave processor in the mas slave processor 20 after the above-mentioned process ter processor including the virtual storage of the paging ing depends on the presence of the memory operand. method. 65 (2) The scale of the instruction decoder in the master. (b-) In case no memory operand exists: processor and the slave processor becomes smaller. It is In the master processor 10, the operation execution not necessary to decode the data length of the memory unit 14 controls the bus control unit 15 to drive I/O bus operand and whether the memory operand is to be read 4,942,519 11. 12 or written because the master processor can deal with a instruction for said second microprocessor and a group of instructions for slave processor as a single second operation execution unit for executing said instruction. On the other hand, it is not necessary to second decoded instruction for said second micro decode instructions for master processor in the slave processor with data stored in a memory location processor. indicated by said second decoded instruction; and (3) The slave processor capable of executing different wherein groups of instructions can be associated to the master all memory locations of said main storage and said processor. It is possible to define the data length of the external storage being mapped into a virtual mem memory operand and the read/write condition in the ory with a paging method, and instructions being slave processor, if the instructions are conformed to the 10 assigned with virtual addresses, instruction format as the group of instructions for the said control system comprising: slave processor. feedback means provided in said second micro In the microprocessOr device of the present inven processor and including a feedback port re tion, the slave processor operates under control of the sponding to a command from said first micro master processor only and does not execute data trans 15 processor for temporarily holding said second mitting. The following two advantages are obtained decoded instruction for said second micro from the above feature of the device. processor including an address required for vir (4) The number of the external pins of the master tual memory management by said first micro processor LSI and the slave processor LSI can be de processor; and creased. 20 Since the decode condition is not required in the means provided in said first microprocessor for master processor, the number of the external pins for reading a content of said feedback port for de the address bus is decreased to a great extent in the slave tecting whether or not a memory location re processor. quired by said second decoded instruction for (5) The scale of the hardware of the slave processor 25 said second microprocessor is physically present can be made smaller. in said main storage, said detecting means being The slave processor needs not drive the address bus coupled with said bus control unit for enabling and the control bus, and does not execute the instruc access to said main storage and generating an tion fetching and instruction decoding simultaneously input/output bus cycle signal for allowance of with the master processor. 30 instruction execution of said second micro The invention has thus been shown and described processor when said memory location required with reference to the specific embodiments. It should by said second decoded instruction for said sec be, however, noted that the invention is in no way lim ond microprocessor is physically present in said ited to the details of the illustrated structures but main storage and can be accessed, said detecting changes and modifications may be within the scope of 35 means operating to generate an interrupt to the appended claims. transfer programs and data from said external I claim: storage to said main storage when said memory 1. A control system for a microprocessor device, said location required by said second decoded in microprocessor device comprising: struction is physically present in said main stor a first microprocessor, a second microprocessor con 40 age, and thereafter to generate said input/output trolled by said first microprocessor to execute an bus cycle signal for allowance of instruction operation of a portion of instruction sets, execution of said second microprocessor, a main storage for storing programs and data for said said feedback means also including a third decoder first microprocessor and said second microproces receiving said input/output bus cycle signal for SOr, 45 allowance of instruction execution of said second an external storage coupled to said main storage for microprocessor for generating an internal start storing programs and data for said first micro signal to said second operation execution unit of processor and said second microprocessor, and said second microprocessor so that said second a bus coupling said first microprocessor, said second operation execution unit of said second micro microprocessor and said main storage to each other 50 processor starts its instruction execution only so as to transfer data and instructions to each other, after said start signal is generated. said instructions including instructions for said first 2. A control system as claimed in claim 1, wherein microprocessor and instructions for said second said detecting means comprises: microprocessor; an effective address calculation unit coupled to said said first microprocessor including a bus control unit 55 bus control unit and for calculating an effective for controlling a status of said bus with respect to address of a memory location required by a given said second microprocessor, said main storage and instruction and executing a paging over check; said external storage, a first instruction decoder for a coupled to said effective decoding an instruction for said first microproces address calculation unit and for mapping said mem sor into a first decoded instruction and a first oper 60 ory location required by said given instruction into ation execution unit for executing said first de an address in said main memory or an I/O address. coded instruction for said first microprocessor with 3. A control system as claimed in claim 1, further data stored in a memory location indicated by said comprising an address decoder provided externally of first decoded instruction for said first microproces said first and second and coupled be sor; 65 tween said bus control unit and said second micro said second microprocessor including a second in processor and for generating a select signal in response struction decoder for decoding an instruction for to a status of a signal outputted from said bus control said second microprocessor into a second decoded unit. 4.942,519 13 14 4. A control system as claimed in claim3 wherein said a main storage for storing programs and data for said address decoder is configured to receive from said bus master microprocessor and said slave microproces control unit a signal indicating an effective address of sor; said main storage or an I/O address and output a select an external storage coupled with said main storage signal to said second microprocessor in response to said 5 for storing programs and data for said master mi I/O address. croprocessor and said slave microprocessor; and 5. A control system as claimed in claim 1, wherein a bus coupling said master microprocessor, said slave said feedback means includes a command port coupled microprocessor and said main storage to each other to said bus and operative to read said instructions for so as to transfer programs and data to each other; said second microprocessor out of said bus in response 10 said microprocessor device further comprising: to a control signal given by said first microprocessor, so feedback means provided in said slave micro that said second instruction decoder of said second processor and including a feedback port re microprocessor operates to receive an output from said sponding to a command from said master micro command port and to decode only said instructions for processor for temporarily holding said second said second microprocessor; wherein 15 decoded instruction for said slave microproces said feedback port is coupled to said second instruc sor including an address required for virtual tion decoder of said second microprocessor to memory management by said master micro receive said second decoded instruction for said processor; and second microprocessor from said instruction de means provided in said master microprocessor for coder for said second microprocessor, and opera 20 reading a content of said feedback port for de tive to store an output of said second instruction tecting whether or not a memory location re decoder temporarily and feedback said stored out quired by said second decoded instruction for put of said second instruction decoder to said first said slave microprocessor is physically present in microprocessor in response to a control signal said main storage, said detecting means being given by said first microprocessor. w 25 coupled with said bus control unit for enabling 6. A control system as claimed in claim 5, wherein access to said main storage and generating an said third decoder of said feedback means is coupled to input/output bus cycle signal for allowance of said address decoder and operative to decode a select instruction execution of said slave microproces signal and output control signals for controlling said sor when said memory location required by said second microprocessor and said feedback means. 30 second decoded instruction for said slave micro 7. A control system as claimed in claim 5, wherein processor is physically present in said main stor said control signals outputted from said third decoder age and can be accessed, said detecting means include: operating to generate an interrupt to transfer said internal start signal to said second operation programs and data from said external storage to execution unit for said second microprocessor; 35 said main storage when said memory location a read control signal to said feedback port; and required by said second decoded instruction for a write control signal to said command port. said slave microprocessor is physically present in 8. A control system as claimed in claim 1 wherein said said main storage, and thereafter to generate said first microprocessor is composed of a one-chip large input/output bus cycle signal for allowance of scale integrated circuit in which said detecting means is instruction execution of said slave microproces incorporated. SO. 9. A control system as claimed in claim 1 wherein said said feedback means also including a third decoder second microprocessor is composed of a one-chip large receiving said input/output bus cycle signal for scale integrated circuit in which said feedback means is allowance of instruction execution of said slave incorporated. 45 microprocessor for generating an internal start 10. A microprocessor device having a virtual storage signal to said second operation execution unit of system and comprising: said slave microprocessor so that said second a master microprocessor including a bus control unit operation execution unit of said slave micro for controlling a status of a bus, a first instruction processor starts instruction execution only after decoder for decoding an instruction for said master 50 said start signal is generated. microprocessor into a first decoded instruction for 11. A microprocessor device as claimed in claim 10, said master microprocessor and a first operation wherein said detecting means comprises: execution unit for executing an operation desig an effective address calculation unit coupled to said nated by said first decoded instruction for said bus control unit and for calculating an effective master microprocessor with data stored in a mem 55 address of a memory location required by a given ory location indicated by said first decoded instruc instruction and executing a paging over check; tion for said master microprocessor; a memory management unit coupled to said effective a slave microprocessor being controlled by said mas address calculation unit and for mapping said mem ter microprocessor to execute an operation desig ory location required by said given instruction into nated by instructions for said slave microprocessor, 60 a physical address in said main memory or an I/O and including a second instruction decoder for address. decoding an instruction for said slave microproces 12. A microprocessor device as claimed in claim 10, sor into a second decoded instruction for said slave further comprising an address decoder provided exter microprocessor and a second operation execution nally of said master and slave microprocessors and cou unit for executing an operation designated thereby 65 pled between said bus control unit and said slave micro with data stored in a memory location indicated by processor and for generating a select signal in response said second decoded instruction for said slave mi to a status of a signal outputted from said bus control croprocessor; unit. 4,942,519 15 16 13. A microprocessor device as claimed in claim 12, cute address calculation from an output of said wherein said address decoder is configured to receive instruction decoder; from said bus control unit a signal indicating an effec a memory management unit being coupled to said tive address of said main storage or an I/O address and effective address calculating unit and operative output a select signal to said slave microprocessor in to execute mapping a virtual address outputted response to said I/O address. by said effective address calculation unit into a 14. A microprocessor device as claimed in claim 10, real address and simultaneously execute a mem wherein said feedback means includes a command port ory protection check; coupled to said bus and operative to read said instruc an operation execution unit being coupled to said tions for said slave microprocessor out of said bus in 10 instruction decoder and operative to execute an response to a control signal given by said master micro operation designated by an instruction for said processor, so that said second instruction decoder of master microprocessor; and said slave microprocessor receives an output of said a bus control unit being coupled to said bus and command port and operates to decode only said instruc said memory management unit, and operative to tions for said slave microprocessor; and 15 output control signals; wherein said feedback port is coupled to said second an address decoder being provided externally of instruction decoder of said slave microprocessor to said master and slave microprocessors and cou receive said second decoded instruction from said pled between said bus control unit and said slave second instruction decoder for said slave micro microprocessor for generating a select signal in processor and operative to store an output of said 20 response to a status of a signal outputted from second instruction decoder temporarily and feed said bus control unit; back said stored output to said master microproces said slave microprocessor including: sor in response to a control signal given by said a third decoder coupled to said address decoder master microprocessor. and operative to decode said select signal and 25 output a starting signal; 15. A microprocessor device as claimed in claim 14, an operation execution unit coupled to said bus wherein said third decoder of said feedback means is and connected at its input to an output of said coupled to said address decoder and operative to de third decoder and operative to execute an code a select signal and output control signals for con operation in response to said starting signal; trolling said slave microprocessor and said feedback 30 a command port coupled to said bus and opera eaS. tive to read an instruction for said slave micro 16. A microprocessor device as claimed in claim 15, processor out of said bus in response to a con wherein said control signals outputted from said de trol signal given by said third decoder; coder include: a second instruction decoder coupled to said said internal start signal to said second operation 35 command port and operative to decode only execution unit of said slave microprocessor; an instruction for said slave microprocessor a read control signal to said feedback port; and and output a second decoded instruction for a write control signal to said command port. said slave microprocessor; and 17. A microprocessor device as claimed in claim 10 a feedback port coupled to said second instruc wherein said master microprocessor is composed of a tion decoder and operative to respond to a one-chip large scale integrated circuit in which said control signal generated by said third decoder detecting means is incorporated. in response to a command from said master 18. A microprocessor device as claimed in claim 10 microprocessor, so as to temporarily store said wherein said slave microprocessor is composed of a second decoded instruction for said slave mi one-chip large scale integrated circuit in which said 45 croprocessor output from said second instruc feedback means is incorporated. tion decoder including an address which is 19. A microprocessor device having a virtual storage required for virtual memory management by system and comprising: said master microprocessor, said feedbackport a master microprocessor, being coupled to said bus so that said bus con a slave microprocessor being controlled by said mas 50 trol unit of said master microprocessor reads a ter microprocessor to execute an operation of a content of said feedback port through said bus, portion of instruction sets, whereby said effective address calculation unit a main storage for storing programs and data for said and said memory management unit cooperate master microprocessor and said slave microproces for detecting whether or not a memory loca SOr, 55 tion required by said second decoded instruc an external storage coupled to said main storage for tion for said slave microprocessor is physically storing programs and data for said master micro present in said main storage, and said bus con processor and said slave microprocessor, and trol unit operating for enabling access of said a bus coupling said master microprocessor, said slave main storage and generating an input/output microprocessor and said main storage to each other bus cycle signal for allowance of instruction so as to transfer programs and data to each other; execution of said slave microprocessor when said master microprocessor being composed of a said memory location required by said second one-chip large scale integrated circuit including: decoded instruction for said slave micro a first instruction decoder to decode instructions processor is physically present in said main for said master microprocessor and instructions 65 storage and can be accessed, for said slave microprocessor; said bus control unit operating to generate an an effective address calculation unit being coupled interrupt to transfer programs and data from to said instruction decoder and operative to exe said external storage to said main storage 4,942,519 17 18 when said memory location required by said sor for generating said select signal and said second decoded instruction for said processor second decoder of said slave microprocessor is physically present in said main storage, and responding to said select signal to generate thereafter to generate said input/output bus said start signal to said operation execution cycle signal for allowance of instruction exe unit of said slave microprocessor so that said cution of said slave microprocessor, and said operation execution unit of said slave micro second address decoder receiving said input processor starts its instruction execution only /output bus cycle signal for allowance of in after said start signal is generated. struction execution of said slave microproces k sk k k 10

15

20

25

30

35

45

50

55

65