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Area Efficient Full Subtractor Design Using CMOS Technology

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Area Efficient Full Subtractor Design Using CMOS Technology ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE) ________________________________________________________________________________________________ Area efficient Full Subtractor design using CMOS Technology 1Monikashree T.S, 2Divya A, 3Kesthara V, 4Nithya Shree S 1Assistant Professor, Department of ITE, Dr.AIT Bangalore, Karnataka, India 2,3,4 Assistant Professor, Department of ECE, Dr.AIT Bangalore, Karnataka, India Email: [email protected] will be large. The need in optimising 1 bit full subtractor Abstract — Full Subtractor is a combinational digital circuit that performs 1 bit subtraction with borrow-in. The using cadence is that, the CMOS gpdk180nm package Main objective of this project is to design a 1-bit Full incorporates the “Cadence Schematic Editor and Analog Subtractor by using CMOS180nm technology with reduced Environment” software used to create a schematic number of transistors, and hence it efficiency in area, speed diagram and a simulation of our implementation. and power consumption. Two types of simulation or test Moreover, it contains the Cadence Virtuoso Editor which bench will be performed in order to ensure that the will allows us to design the layout of the 1-bit subtractor, implementation is fully functional. First, a schematic as well as to perform the assessment of several simulation will be performed by means of the “Cadence performance parameters for the circuit. In addition, Schematic Editor and Analog Environment” software. transient analysis will be performed. The proposed Second, the 1-bit subtractor layout model will be emulated by the “Cadence Virtuoso Editor”. Performing the specifications offered a wide selection varying between simulation will mainly consist in evaluating the quality of two types of implementations, each with an analogous the output signals in terms of voltage levels, to assess the kind of difficulty. We chose the design of a 1-bit performance of the circuit in terms of speed, area and subtractor in order to minimize while trying to maintain power usage. the area as much as possible. Keywords: Cadence, 1-bit Half Subtractor, 1-bit full II. SUBTRACTOR subtractor, logic gate, Virtuoso, A subtractor performs subtraction which is one of the I. INTRODUCTION four basic binary operations. In many computers and Arithmetic circuits are important part of Digital circuits. other kinds of device processors, subtractors are used not In the digital, circuits subtractor is one of the most critical only for the arithmetic calculations, but are also components used in the processor of portable devices [3]. frequently used in other parts of the processor. The Hence the area and power efficient design of 1-bit subtractors can be constructed to operate on binary Subtractor is necessary for design of small size portable numbers and represents many binary numbers. devices. There are various possible logic styles that can Depending upon the application of the device or upon the give better performance as compared to the basic CMOS purpose of the application to be performed, the inputs to logic style. The performance estimation of 1- Bit full the circuit device may vary from two to three. We could Subtractor is based on area, delay and power possibly use a Half-Subtractor if we have two inputs consumption. The purpose of this work is [5],[6]. while for three inputs, a Full-Subtractor can be used. 1. To perform the design, full custom implementation 2.1 1 Bit Half Subtractor and simulation of a 1-bit subtractor at the transistor level by means of CMOS180nm technology. Subtractor at the A conventional Half-subtractor circuit is a combinational transistor level by means of CMOS 180nm technology. circuit that can be used to subtract one binary digit from another to produce a Difference output and a Borrow 2. To verify if the circuit can perform with all the possible output. Functionally, the half subtractor consists of single combinations of the inputs alongside the logic function 2 inputs XOR Gate, INVERTOR Gate and single 2 inputs which it is designed for. AND gate. 3. To evaluate the quality of the output signals in terms of The Borrow output here specifies whether a „1‟ has been voltage levels. borrowed to perform the subtraction. The Half-Subtractor 4. To assess the performance of the circuit in terms of at the gate-level and truth table are shown in Fig 1 and speed, area table 1. In the recent, various approaches of CMOS 1- Bit full Subtractor design by using various different logic styles has presented and unified into an integrated design methodology. The Conventional 1 bit full subtractor diagram is shown in fig1 and its truth table in Table 1.The number of logic gates required are more, it leads in increasing number of transistors, hence the area, delay ________________________________________________________________________________________________ ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 25 ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE) ________________________________________________________________________________________________ The Truth table and Boolean expression for the two output variables are given by the equations: . Fig1: Gate Level 1 bit Conventional Half Subtractor The Truth table and Boolean expression for the two output variables are given by the equations: A B Bout Diff Comment Table 2: Truth Table of 1 Bit Full Subtractor 0 0 0 0 0-0=0,No borrow 0 1 1 1 0-1=-1,borrow 2, so:2-1=1 Bout= AB+ ABin+BBin 1 0 1 0 1-0=1, No borrow III. PROPOSED 1 BIT FULL SUBTRACTOR 1 1 0 0 1-1=0, No borrow DESIGN Table 1: Truth Table of 1 bit half subtractor Here the primary goal is to reduce the area and the transistor count in order to reduce area, power, delay parameters. The proposed full subtractor implemented by cascading two 1-bit half subtractor. In order to build 2.2 1 Bit Full Subtractor reduced transistor 1-bit subtractor, the idea has to begin with the basic gates. Each individual logic gates used in A 1- Bit full Subtractor is a combinational circuit that the circuit is constructed by minimum no transistors so as performs a subtraction between two binary bits and 1 may to reduce the circuit area, the performance criteria‟s of have been borrowed by a lower significant stage. This each gates are individually investigated, analyzed and circuit has three inputs and two outputs. Let the three their interaction to develop main design. inputs are A, B and Bin and Borrow and Difference are two outputs of the 1-bit Subtractor and denoted by Bout 3.1 Logic Gates Design and Diff respectively. Logic diagram of 1-bit full The implementation consists of four types of logic Subtractor has been shown in fig.2. components such as such as inverters, 2-input AND gates, 2-input OR gates and 2-input XOR gate. 3.1.1 Invertor An inverter gate usually output signals either representing a “true” or “false”. In this case, the inverter‟s output OUT is true when the input IN is “false”. OUT=IN, where IN is the inverted input and OUT the output. Moreover, the truth table below shows the function of the inverter logic gate: Input IN Output OUT 0 1 Fig. 2 Logic Diagram of conventional 1 bit Full 1 0 Subtractor Table 3: Truth Table of an Inverter In subtraction process on two bits, a minuend and a 3.1.2 2 Inputs AND Gate subtrahend, and also takes into consideration whether a „1‟ has been borrowed by the previous adjacent lower A 2-input AND gate usually output signals as “true” minuend bit or not. As a result, there are three bits to be when inputs A and B are both “true”. Therefore, we can handled at the input of a Full-Subtractor, namely the two write the 2-input AND logic equation which is simply bits to be subtracted and a borrow bit designated as Bin. provided by the following equation below: There are two outputs, namely the Difference output D Vout= A X B where A and B the inputs and vout the and the Borrow output Bout. The Borrow output bit tells output. Moreover, the truth table below shows the whether the minuend bit needs to borrow a „1‟ from the operation of the 2-input AND logic gate: next possible higher minuend bit. ________________________________________________________________________________________________ ISSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 26 ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE) ________________________________________________________________________________________________ Input A Input B Output vout In this section we presented the transistor level 0 0 0 implementation of both 1 bit Half Subtractor and 1 bit Full Subtractor. The pmos and nmos transistors used to 0 1 0 construct the subtractor are has their own specification, 1 0 0 and those are not altered. 1 1 1 3.2.1 1 Bit Half subtractor Table 4: Truth Table of 2 inputs AND Gate The Schematic of 1 Bit Half subtractor with one XOR, 3.1.3 2 Inputs OR Gate Inverter, AND are implemented at transistor level using Cadence Tool is shown in below fig. A 2-input OR gate usually output signals as “true” when any one inputs A, B or both are “true”, Therefore, we can write the 2-input AND logic equation which is simply provided by the following equation below: Vout= A + B where A and B the inputs and vout the output. Moreover, the truth table below shows the operation of the 2-input OR logic gate: Input A Input B Output vout 0 0 0 0 1 1 1 0 1 1 1 1 Fig 4: Schematic of transistor level 1 bit Half Subtractor Table 5: Truth Table of 2 inputs OR Gate 3.2.2 1 Bit Full Subtractor 3.1.4 2 Inputs XOR Gate Here we presented both conventional and proposed full subtractor to show the reduced transistor count.
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