RISC-V Poster Preview
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RISC-V Poster Preview 7th RISC-V Workshop End-to-end formal ISA verification of RISC-V processors with riscv-formal ● Framework for formally verifying RISC-V processor cores ● Only requires Open Source tools (Yosys, ABC, Yices2, etc.) ● Every core that implements the RVFI trace port is supported (can easily be added to existing cores) ● End-to-end ISA verification is hard. We break the problem down into 100+ small problems that can be proven independently. This yields a tractable formal verification problem. ● Monitor core for tandem verification using same formal spec and RVFI trace port is available. ● Is being used to formally verify real-world processors right now (not vapourware, not just for “academic toy processors”) − https://github.com/cliffordwolf/riscv-formal Results, Status, Future Work ● Found bugs in ● Future Work − RISC-V Rocket − Atomics − PicoRV32 − F/D/Q support − Spike (riscv-isa-sim) − Priv. Spec, CSRs − The prose ISA Spec − Better support for non-free flows − Verification of other ● Currently supports RISC-V formal specs − RV32 / RV64 − More cores − C extension − M extension Power Matters.TM MicroPython Port for RISC-V soft Processor Badal Nilawar © 2015 Microsemi Corporation. 4 MicroPython (RISCV) Software Architecture ▪ Microsemi ported MicroPython on RISCV ▪ Porting activity involves ▪ Startup code ▪ RISCV HAL integration ▪ Tool chain ▪ Driver porting ▪ Features ▪ Machine modules like Pin, mtime ▪ REPL ▪ Advanced Math Library ▪ Soft Float ▪ Features Planned ▪ SPI, I2C, Ethernet ▪ Multi Threading ▪ File system support ▪ Distributing on Github TM © 2015 Microsemi Corporation. Power Matters. 5 Century Gothic Slide Title – 36pt Century Gothic Subhead – 24pt Century Gothic Content Title – 24pt Century Gothic Content Text – 20pt Century Gothic Compare Heading – 18pt Century Gothic Image Caption – 16pt Century Gothic Table Text & Caption Text – 14pt Micriµm The larger text sizes have condensed spacing, between 1.5 and 0.5 pt. Presentation Colors Jean J. Labrosse R:137 G:137 B:137 Founder and Chief Software Architect R:88 G:88 B:88 [email protected] R:244 G:146 B:45 R:17 G:59 B:149 R:12 G:35 B:83 Century Gothic Slide Title – 36pt Century Gothic Subhead – 24pt Leading Embedded RTOS and Century Gothic Content Title – 24pt Century Gothic Content Text – 20pt Stacks Century Gothic Compare Heading – 18pt Tools Century Gothic Image Caption – 16pt RTOS IAR, Keil, GNU, Other Century Gothic Table Text & Caption Text – 14pt µC/OS-II or µC/OS-III The larger text sizes have condensed spacing, between 1.5 and 0.5 pt. µC/Probe Stacks µC/FS Presentation Colors µC/TCP-IP (IPv4 and IPv6) µC/CAN R:137 G:137 B:137 SystemView µC/USB-H and µC/USB-H µC/GUI R:88 G:88 B:88 µC/Modbus R:244 G:146 B:45 Tracealyzer R:17 G:59 B:149 R:12 G:35 B:83 Century Gothic Slide Title – 36pt Century Gothic Subhead – 24pt Century Gothic Content Title – 24pt RTOS (µC/OS-II and µC/OS-III) Century Gothic Content Text – 20pt Century Gothic Compare Heading – 18pt • Professional Grade, Fully Supported Century Gothic Image Caption – 16pt • Ported to over 45 CPU architectures Century Gothic Table Text & Caption Text – 14pt • Certified in numerous verticals: The larger text sizes have condensed – Avionics spacing, between 1.5 and 0.5 pt. – Medical – Industrial – Nuclear Presentation Colors • µC/OS-II on Mars Curiosity Rover R:137 G:137 B:137 • Books by MicriµmPress: R:88 G:88 B:88 – 7 on µC/OS-III – 5 on µC/TCP-IP R:244 G:146 B:45 – 1 on µC/USB-D R:17 G:59 B:149 R:12 G:35 B:83 Century Gothic Slide Title – 36pt Century Gothic Subhead – 24pt Century Gothic Content Title – 24pt µC/OS-II / µC/OS-III and the RISC-V Century Gothic Content Text – 20pt Century Gothic Compare Heading – 18pt • Ported onto the Microsemi Creative Board Century Gothic Image Caption – 16pt – SoftConsole Century Gothic Table Text & Caption Text – 14pt The larger text sizes have condensed spacing, between 1.5 and 0.5 pt. Presentation Colors R:137 G:137 B:137 R:88 G:88 B:88 • Available soon on: – Digilent ARTY Artix-7 FPGA Dev Board with Segger Embedded Studio and R:244 G:146 B:45 J-Link R:17 G:59 B:149 R:12 G:35 B:83 Power Matters.TM Enabling Safe Crypto Using RISC-V Soft Processor Sathish Odiga © 2017 Microsemi Corporation. Company Proprietary 10 Introduction ▪ Microsemi PolarFire® FPGAs represent the industry’s most advanced secure programmable FPGAs. • Built-in Athena's TeraFire® crypto processor supports the CNSA suite and beyond, and includes side-channel analysis resistant countermeasures. ▪ RISC-V soft processor is a perfect complement to the PolarFire FPGAs for building secure and reliable systems. • Open-source RISC-V ISA enables application-specific processor implementations • Unlike competing processors, the RISC-V processors allow inspection of the RTL to build trust on the processor implementation. ▪ Secure boot is the starting point for implementing secure systems • Process of guaranteeing that the boot code and all subsequent codes are authentic is called Secure Boot. • PolarFire FPGAs have built-in security capabilities to support secure boot of soft RISC-V processor TM © 2017 Microsemi Corporation. Company Proprietary Power Matters. 11 Secure Boot RISC-V Processor PolarFire FPGA 1. At power-up, System Controller copies authenticated bootloader reset from sNVM to SRAM. reset MiV_RV32IMA_L1_AHB init_done (RISC-V CPU) AHB_MST_MEM AHB_MST_MMIO 2. Processor executes the bootloader from SRAM. AXI Interconnect Bus 3. Bootloader fetches the application keys from sNVM. AHBL Bus SPI System DDR SRAM Slash Controller Controller 4. Bootloader commands Crypto (Encrypted and Processor for application signed Application) Crypto Processor authentication and decryption. sNVM System Services 5. Bootloader copies the (Trusted Bootloader and Keys) (Protected by SRAM-PUF) authenticated application from SPI Flash to DRAM and DDR executes it. Memory TM © 2017 Microsemi Corporation. Company Proprietary Power Matters. 12 Power Matters.TM RISC-V based Lockstep Processor Implementation Sathish Odiga © 2017 Microsemi Corporation. Company Proprietary 13 Motivation ▪ Increasing levels of automation driving broader adoption of safety-critical systems • Systems must function correctly in order to avoid hazardous situations • Faults must be detected and controlled ▪ Safety-critical systems heavily rely on embedded processors • Need methodologies for fault detection due to random faults in the embedded processor. ▪ Lockstep processor provides real-time diagnostics using an additional slave processor and a comparator. • Two identical processors run in lockstep with address, data and controls compared for consistency. • Temporal and spatial separation of cores increases reliability ▪ Flash FPGAs are attractive in safety-critical applications • Flexibility to implement custom hardware • Built-in security and reliability features TM Power Matters. 14 © 2017 Microsemi Corporation. Company Proprietary Dual-core Lockstep Processor Demo TM © 2017 Microsemi Corporation. Company Proprietary Power Matters. 15 An Engines Extension for RISC-V Eric L. McCorkle Overview of the Extension Provides a mechanism for fast access to specialized functional units and (some) devices without crossing privilege levels ● Allows interaction with engine resources by the regular pipeline ● Can be used for specialized functional units, also devices ● Engines bound to engine handles prior to use ● Engines have states to control resource usage, aid virtualization ● Virtualization through suspend/resume capability ● Security through ownership/access masks History of the Extension ● Originated as an attempt to design a crypto extension ● “Crypto engines” envisioned as special functional units to decouple instructions from specific algorithms ● States and transitions emerged as a way to allow for automation injection of pseudo-ops to “fuzz” side-channels ● Discussions on the isa-dev list led to improvements ● DMA capabilities accounted for (no modification needed) ● At this point, the extension could potentially function as an I/O instruction set Cloud-Based RISC-V SoC design and Co-simulation Mohamed Shalan, American University Cairo (Presented by Sam Steffl, Brown Univ) Mohamed Shalan, Ph.D., Ahmed Agiza, Ahmed ElShafey, Karim Hasebou, Mohamed Gaber, Veronia Bahaa The American University in Cairo Sherief Reda, Ph.D. -- Brown University Presenter: Samuel Steffl – Brown University • • • An online digital design platform with RISC-V at the core. dwarfRV32: A small footprint RV32I CPU SoC Editor: An online rule-based editor using dwarfRV32 Beekeeper: A bus functional model/debugger leveraging the Verilog Procedural Interface DBT-RISE: Addressing the RISC-V VP Challenge Eyck Jentzsch Wolf-Ekkehard Matzke DBT-RISE RISC-V Start SW development even before having RTL or silicon Dynamic Binary Translation - Retargetable ISS Environment VM ARCH ADAPTER GDB SERVER HiFive1 UARTUART GPIO SPI PWM RAM PLIC Available as Open Source system environment/test bench Professional Services on request th Page ▪ 26 7 RISC-V Workshop – Eyck Jentzsch, Wolf-Ekkehard Matzke DBT-RISE Focus on Development driven by real-world • Performance customer requirements • Easy integration • Straightforward generation of • Accuracy ISSs • Adaptability & Extensibility • Convenient VP authoring • Considerable flexibility Applied to RISC-V to foster VP development ➔ Demo: HiFive 1 th Page ▪ 27 7 RISC-V Workshop – Eyck Jentzsch, Wolf-Ekkehard Matzke contact address phones online MINRES Technologies GmbH phone +49-89-67807688 www.minres.com Keltenhof 2 fax +49-89-67807689 github.com/minres/