Bruce D. Lightner 3/3/16, 5:07 PM
Total Page:16
File Type:pdf, Size:1020Kb

Load more
Recommended publications
-
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Section 2. Worldwide IC Vendors
2 WORLDWIDE IC MANUFACTURERS OVERVIEW Analysis of worldwide integrated circuit (IC) sales by region from 1975 through 1996 provides a perspective to the increasingly global importance of semiconductor manufacturing (Figure 2-1). Historically, sales by North American companies were dominant in the mid-1970s. By the mid- 1980s IC sales were evenly split between North American and Japanese companies. By 1990, the Japanese had increased their share of worldwide IC sales to a leading 48 percent, mainly at the expense of North American companies. Then, in 1992 Japan’s economy weakened causing their share to drop; a persistent economic slump in the following years coupled with Korean IC manu- facturers’ success in the memory market caused the Japanese share to continue dropping. The Japanese share fell further in 1996 primarily because of the yen to dollar exchange rate and the decline in the dynamic random access memory (DRAM) market. While market shares for North American and Japanese IC manufacturers have fluctuated over the past 22 years, European IC companies have continued to capture a relatively steady seven to ten percent of worldwide IC sales. The share belonging to ROW companies, which is dominated by Korean and Taiwanese manufacturers, surpassed that of European companies in 1992, reaching 15 percent in 1995, and 14 percent in 1996. A ranking of the world’s top ten merchant semiconductor sales leaders in 1996, and ICE’s estimate for 1997, is given in Figure 2-2. The estimated sales for these companies as a group increased 10 percent during 1997. The 1996 top fifteen worldwide IC sales leaders are listed in Figure 2-3. -
United States Patent [19J [11] Patent Number: 6,112,019 Chamdani Et Al
Illlll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111 US006112019A United States Patent [19J [11] Patent Number: 6,112,019 Chamdani et al. [45] Date of Patent: Aug. 29, 2000 [54] DISTRIBUTED INSTRUCTION QUEUE "An Efficient Algorithm for Exploring Multiple Arithmetic Units," Tomasulo IBM Journal, Jan. 1967, pp. 25-33. [75] Inventors: Joseph I. Chamdani, Marietta; Cecil 0. Alford, Lawrenceville, both of Ga. "Implementation of Precise Interrupts In Pipelined Proces sors," James E. Smith Andrew R. Pleszkun,© 1985 IEEE, [73] Assignee: Georgia Tech Research Corp., Atlanta, pp. 36-44. Ga. "Instruction Issue Logic in Pipelined Supercomputers", [21] Appl. No.: 08/489,509 Shlomo Weiss & James E. Smith,© 1984 IEEE, Transac [22] Filed: Jun. 12, 1995 tions on Computers, vol. c-33, No. 11, pp. 1012-1022 Nov. 1984. [51] Int. CI.7 ........................................................ G06F 9/22 [52] U.S. Cl. .............................................................. 395/390 "The Metafiow Architecture", Popescu et al, IEEE Micro,© [58] Field of Search ..................................... 395/376, 378, 1991 IEEE, pp. 10-13, 63-73. 395/381, 382, 391, 393, 390 [56] References Cited Primary Examiner-David Y. Eng Attorney, Agent, or Firm-Thomas, Kayden, Horstemeyer U.S. PATENT DOCUMENTS & Risley, L.L.P. 3,924,245 12/1975 Eaton et al. ....................... 395/421.09 4,725,947 2/1988 Shonai et al. ........................... 395/585 [57] ABSTRACT 4,736,288 4/1988 Shintani et al. .. ... ... ... .... ... ... ... 395 /395 4,752,873 6/1988 Shonai et al. ...................... 395/800.23 A distributed instruction queue (DIQ) in a superscalar 4,780,810 10/1988 Torii et al. .... ... ... ... ... .... ... ... ... 395 /800 microprocessor supports multi-instruction issue, decoupled 4,896,258 1/1990 Yamaguchi et al. -
AES Candidate C
Public Comments Regarding The Advanced Encryption Standard (AES) Development Effort Round 1 Comments [in response to a notice in the September 14, 1998 Federal Register (Volume 63, Number 177; pages 49091-49093)] From: "Yasuyoshi Kaneko" <[email protected]> To: <[email protected]> Subject: AES Candidate Comments Date: Tue, 25 Aug 1998 11:43:28 +0900 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 4.72.2106.4 X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2106.4 Messrs. Information Technology Laboratory I am Y.Kaneko belonging Telecommunications Advancement Organization of Japan(TAO). I have found the specifications of all AES candidate Algolizums on web and begun to read. In my opinion, these 15 ciphers are classified to 4 groups. Namely 'DES-type' , 'IDEA-type' , 'SAFER-type' and 'other-type' are found out from these specifications. 'DES-type' ciphers are 'DEAL', 'DFC', 'E2' and 'LOKI97' , these ciphers have feistel structures with a F-function. 'IDEA-type' ciphers are 'CAST-256', 'MARS', 'RC6' and 'TWOFISH', these ciphers have paralell 4 inputs and 4 outputs with some (F-) functions. 'SAFER-type' ciphers are 'CRYPTON', 'MAGENTA', 'RIJENDA', 'SAFER+' and 'SERPENT', these ciphers have a kind of Pseude-Hadamard Transform structure with invertible functions per same bits-length input/output. 'other-type' ciphers are 'HPC' and 'FLOG' these ciphers have particular structures with original algolithms. The differences of the first three types are summarized as followings: 1) Differential and Linear cryptanalysis From the viewpoint of the differential and linear cryptanalysis, supposing that r-round cipher (which round numbers would be logically and experimentaly obtained) gives an enough strong ciphers for each types then 'DES-type' ciphers need r+3 or r+2 round to keep security, because (r-2)-round or (r-3)-round differential or linear attacks are possible for the feistel structure, 'IDEA-type' ciphers and 'SAFER-type' ciphers need r+1 round to keep security in general meaning.