High Voltage SOI Stacked Switch with Varying Periphery FETs

Yu Zhu, Oleksiy Klimashov, Ambarish Roy, Guillaume Blin, David Whitefield, and Dylan Bartle Skyworks Solutions, Inc. 20 Sylvan Rd. Woburn, MA 01801 USA

Abstract-The breakdown voltage of a FET stack is limited by respectively. It can be seen that no matter how many FETs are the unequally divided voltage drop among the stacked FETs. A stacked, the maximum breakdown voltage can be achieved is novel stack composed of varying periphery FETs is proposed. Uniform voltage distribution, and thus much higher breakdown [5] voltage, can be achieved by carefully designing the periphery of each FET. A FET stack with varying periphery was designed and Cds += BVmax )5.0( BVFET (3) fabricated. Significant improvement in breakdown voltage was Cgnd experimentally confirmed. Unlike the approach of inserting feed- forward capacitance, the breakdown voltage increase is achieved Feed-forward capacitances have been used to increase the without isolation degradation. stack breakdown voltage via reducing the uneven distribution of the voltage drop [6]. However, the feed-forward I. INTRODUCTION capacitances inserted inevitably increases the off state A high-quality microwave switch is a key block of an RF capacitance. The increase in breakdown voltage is achieved at front end of time division duplexing (TDD) wireless the expense of isolation degradation. communication system. The power handling capability is the A novel stack composed of varying periphery FETs is most stringent specification of antenna switches. Among proposed in this paper. A uniform voltage distribution can be various process technologies, silicon-on-insulator (SOI) achieved by carefully designing the periphery of each FET CMOS process has become a promising technology [1, 2]. stacked. The stack breakdown voltage can thus be increased The antenna switch is designed with each branch being able with no extra capacitance, and thus no isolation degradation. to support the maximum voltage seen at the antenna. In SOI This paper is organized in the following way. The analysis technology, where the FET breakdown is much lower than the of the voltage distribution inside FET is performed with peak RF voltage, stacking FETs into a cascade configuration electromagnetic (EM) simulation and equivalent circuit in II. is a straightforward way to withstand the voltage [3]. It was The stack with varying periphery is proposed in III, the design believed that the voltage across the stack is equally divided procedure and measurement results are also provided. A among the stacked FETs [4]. For a shunt branch of stacked conclusion is given in IV. FETs, the breakdown voltage can thus be written as = nBVBV , (1) FET where BVFET is the breakdown voltage of a single FET, and the n is the number of stacked FET, namely the stack height. 120 Because of the capacitive coupling between off state FET 100 and the ground, however, the voltage drop across the FET (1) stack is not equally divided. The voltage drop decreases gradually from the signal input side to the grounded side. The 80 FET at the input side sees the biggest voltage drop, which 60 limits the stack breakdown voltage. The breakdown voltage of FET stack can be expressed as (2) 40 [5]. Breakdown Voltage (V) Voltage Breakdown C nα)2sinh( 20 BV = ds BV (2) − α FET Cgnd n )12cosh( 0 0 5 10 15 20 25 30 35 40 45 50 where C and C are the drain-source capacitance and the Stack Height ds gnd capacitance to the ground, respectively, and Figure 1. Dependence of breakdown voltage on stack height α = depicted by (1) and (2) , respectively. sinh2 / CC dsgnd . Fig. 1 shows the stack height dependence of breakdown voltage depicted by (1) and (2)

978-1-4799-8766-5 II. VOLTAGE DISTRIBUTION INSIDE STACK proposed in this paper. The periphery of each FET inside the EM simulation can be a powerful tool for investigating the stack is carefully designed to achieve uniform voltage drop. voltage distribution inside a FET stack. Since MOSFET, being The stack breakdown voltage can therefore be increased considered as an active device, actually works in its passive without degrading the isolation. states in a switch, EM simulation was performed on the entire Since the current changes along the stack, the uniform MOSFET including both the metal electrodes and the voltage drop can be achieved by adjusting the impedance. semiconductor channels [7]. Unlike the approach of inserting feed forward capacitance, the In order to find the internal voltage distribution, ports are impedance is changed by changing the periphery of each FET. attached at both drain and source sides of each FET. N+1 FET periphery can be changed either by changing finger ports are needed for a stack with n FETs. The simulated S number or by changing the unit gate width. parameter was then imported into a circuit simulator and A stack with varying unit gate width FETs is investigated in represented with an n+1 port black box. The stack is this study. The design procedure is as follows connected between a signal source and the ground. The 1) EM simulation is at first performed on a stack voltage distribution can easily be obtained with an AC composed of the same periphery FETs. simulation at desired frequency. The simulated voltage drop 2) The equivalent circuit, as shown in Fig. 3, is then inside stack, shown in Fig. 2, is believe to be accurate, since extracted from the simulated S parameter. all of the coupling and distributed effects were taken into 3) Optimization of the equivalent circuit is then performed account. to achieve uniform voltage drop with each C ds set as An equivalent circuit, shown in Fig. 3, is then generated to optimal variable. gain more insight into the voltage distribution. There are three 4) The optimized FET peripheries can easily be kinds of capacitances, the C , C , and C , the coupling determined based on extracted C ds values. ds gnd cp capacitance among FETs. All of the capacitances can be 5) The voltage distribution is confirmed by performing accurately extracted from the Y parameters, which was EM simulation on a stack composed of FETs with converted from simulated S parameters, as optimized peripheries.

= − ω Cds _ i imag (Yii +1 /) , (4)

n = ω Cgnd _ i imag (∑ Yij /) , (5) j=1

= − ω Ccp _ ij imag (Yij /) . (6)

As shown in Fig. 2, the voltage drop distribution from the EM simulation can be accurately reproduced with the equivalent circuit.

III. STACK WITH VARYING PERIPHERY FET S

The FET stacks reported so far are composed of FETs with the same periphery, which lead to unequally divided voltage Figure 3. Equivalent circuit of off state FET stack. drop as shown in II. A stack with varying periphery FETs is

EM simulation Stack with same periphery FETs Equivalent circuit Stack with varying periphery FETs

Drop Voltage Normalized

Drop Voltage Normalized

Stacked FET Stacked FET Figure 2. Simulated voltage drop inside FET stack. Figure 4. Improvement in voltage drop inside FET stack. 120 of voltage drop. The design procedure is then described. Significant improvement in voltage drop distribution has been

100 achieved in the simulation. A 35-FETs stack is designed and (1) Measured fabricated. Breakdown voltage of 100V is achieved 80 experimentally with no isolation degradation.

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Breakdown Voltage (V) (V) Breakdown Voltage 20 2010. [2] T. Mckay, M. Carroll, D. Kerr, and J. Costa, “Advances in 0 0 5 10 15 20 25 30 35 40 45 50 silicon-on-insulator cellular antenna switch technology,” 2009 IEEE Topical Meeting on Silicon Monolithic Integrated Circuit Stack Height in RF System, pp. 1-4, 2009. Figure 5. Dependence of breakdown voltage on stack height. [3] H. Xu and K. Kenneth, “A 31.3-dBm bulk CMOS T/R switch using stacked transistors with sub-design-rule channel length in The uniformity of the voltage drop distribution can be floated p-wells,” IEEE Solid-State Circuits, Engineering , vol. further improved by iterating the procedure. Fig. 4 shows the 42, no. 11, pp. 2528-2534, Nov. 2007. distribution of voltage drop for the stacks with the same and [4] M. Shifrin, P. Katzin, Y. Ayasli, “Monolithic FET structures for high-power control component applications,” IEEE Trans. On the optimized peripheries, respectively. Significant Microwave Theory Techniques, vol. 37, no. 12, pp. 2134-2141, improvement in the voltage distribution can be observed. A Dec. 1989. SOI FET stacked with 35 FETs has been designed and [5] Y. Zhu, O. Klimashov, D. Bartle, "Analytical model of voltage fabricated. As shown in Fig. 5, the breakdown voltage above division inside stacked-FET switch," Microwave Conference 100V has been achieved with varying periphery FETs, and no (APMC), 2014 Asia-Pacific , vol., no., pp.750-752, 4-7 Nov. 2014. additional capacitances are needed. [6] X. Wang, C. Yue, "A Dual-Band SP6T T/R Switch in SOI IV. CONCLUSIONS CMOS With 37-dBm P_0.1dB for GSM/W-CDMA Handsets," Microwave Theory and Techniques, IEEE The voltage distribution inside FET stack has been Transactions on , vol.62, no.4, pp.861-870, April 2014. investigated with EM simulation. An equivalent circuit is then [7] Y. Zhu, C. Wei, G. Nohra, C. Zhang, O. Klimashov, Y. Hong, extracted from the simulated S parameter. It is shown that the D. Bartle, "Electromagnetic only HEMT model for switch design," APMC 2009 , pp.273-276, 7-10 Dec. 2009. stack breakdown voltage is limited by the unequally divided voltage drop among the FETs. A novel stack with varying periphery FETs is proposed to achieve a uniform distribution