The Space Simulator

Total Page:16

File Type:pdf, Size:1020Kb

The Space Simulator The Space Simulator Michael S. Warren Chris Fryer M. Patrick Goda [email protected] [email protected] [email protected] Abstract Buying a Supercomputer What would you do if you had $500,000 to buy a computer, and it The Space Simulator is a 294-processor Beowulf cluster with had to be delivered in 30 days? theoretical peak performance just below 1.5 Teraflop/s. It is based on the Shuttle XPC SS51G mini chassis. Each node consists of a budget space power cooling compiler system 2.53 GHz Pentium 4 processor, 1 Gb of 333 MHz DDR SDRAM, an 80 Gbyte Maxtor hard drive, and a 3Com 3C996B-T gigabit ethernet administration purchasing department card. The network is made up of a Foundry FastIron 1500 and 800 delivery deadline performance reliability Gigabit Ethernet switch. Each individual node cost less than $1000, and the entire system cost under $500,000. The cluster achieved code MPI latency tolerance SMP memory Linpack performance of 665.1 Gflop/s on 288 processors in October bandwidth bureaucracy shared memory 2002, making it the 85th fastest computer in the world according to the 20th TOP500 list. Performance has since improved to 757.1 Linpack operating system network bandwidth tools Gflop/s. Here we describe the design, implementation and performance of the cluster, as well as some scientific application results obtained with the machine. Instruction #1 — Assembly of Beowulf requires great peace of mind. Space Simulator Architecture Qty. Price Ext. Description 294 280 82,320 Shuttle SS51G mini system (bare) 294 254 74,676 Intel P4/2.53GHz, 533MHz FSB, 512k cache 588 118 69,384 512Mb DDR333 SDRAM (1024Mb per node) 294 95 27,930 3com 3c996B-T Gigabit Ethernet PCI card 294 83 24,402 Maxtor 4K080H4 80Gb 5400rpm Hard Disk 294 35 10,290 Assembly Labor/Extended Warranty 4,000 Cat6 Ethernet cables 3,300 Wire shelving/switch rack 1,378 Power strips 1 186,175 Foundry FastIron 1500+800, 304 Gbit ports Total $483,855 $1646 per node 5.06 Gflop/s peak/node Table 1: Space Simulator architecture and price (September, 2002). The total cost per node was $1646, with $728 (44%) of that figure representing the Network Interface Cards and Ethernet switches Space and Power Consumption Cluster Temperature Processor Athlon P4 P3 P4 TM5600 TM5800 Clock (MHz) 1800 2200 1133 2530 667 933 Performance (Mflop/s) 952 656 595 1357 298 373 Power (watts/proc) 160 130 70 125 22 24 Power eff. (Mflop/s/watt) 5.95 5.05 8.5 10.8 13.5 15.5 Table 2: Power consumption for various cluster configurations running the parallel N-body code. Note that power figures include power consumption of NIC and network switch. The P4 figures listed in column three represent the higher power consumed by the previous generation Figure 1: A smoothed representation of the temperature across the of processors. cluster obtained from the lm sensors package on each node. OS install Reliability We used PXE and RedHat kickstart. During the installation of the cluster and the initial large Linpack benchmark runs we identified the following defective hardware: • Make sure PXE is enabled on your NICs before you get them. 3 power supplies 6 disk drives 4 motherboards 6 sticks of DRAM 1 ethernet card • Turn off spanning tree protocol on your ethernet switches. During the six month period since the initial failures, the following hardware has failed: 2 power supplies 5 disk drives 1 motherboard 3 sticks of DRAM 1 fan connector loose It is possible that the faulty DRAM and motherboard/CPU discovered after the initial installation was defective to begin with, but took longer to identify since the errors were very infrequent. Software Environment and Tools Network Performance 800 700 Simpler is better. What do you really need? 600 "TCP" "LAM-O" "SWAMPI" "LAM" 500 "mpich2-0.92" "mpich-1.2.5" • A stock Linux distribution. Almost any one will work fine. 400 • A message passing library. LAM or MPICH are good. Bandwidth in Mbps 300 200 100 Everything else is an optimization. 0 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size in Bytes “Premature optimization is the root of all evil.” -Hoare Figure 2: We show bandwidth vs message size for a variety of message passing libraries as measured via NetPIPE. Memory Bandwidth Gravity Kernel Performance The node memory bandwidth is less than optimal for its 333 MHz Processor libm Karp frequency due to the fact that the on-board video system uses the 533-MHz Alpha EV56 76.2 242.2 system DRAM for it’s frame buffer. It is possible to disable the on-board 667-MHz Transmeta TM5600 128.7 297.5 VGA controller and increase memory copy bandwidth by 14%, but you 933-MHz Transmeta TM5800 189.5 373.2 must then insert an AGP video card into the system in order for it to 375-MHz IBM Power3 298.5 514.4 boot. 1133-MHz Intel P3 292.2 594.9 Stream results for the nodes in their normal configuration with a 4 1200-MHz AMD Athlon MP 350.7 614.0 MByte shared VGA frame buffer are: 2200-MHz Intel P4 668.0 655.5 2530-MHz Intel P4 779.3 792.6 Function Rate (MB/s) RMS time Min time Max time 1800-MHz AMD Athlon XP 609.9 951.9 Copy: 1144.5249 0.0700 0.0699 0.0702 1250-MHz Alpha 21264C 935.2 1141.0 Scale: 1145.2130 0.0699 0.0699 0.0700 2530-MHz Intel P4 (icc) 1170.0 1357.0 Add: 1262.9053 0.0951 0.0950 0.0951 Triad: 1265.4891 0.0949 0.0948 0.0949 Table 3: Mflop/s obtained on our gravitational micro-kernel benchmark. Linpack Benchmark Below are the results of running the HPL implementation of Linpack on the Space Simulator eight times in a row (which takes about 12 hours). Each run passed the residual check. Some commercial supercomputers have trouble running for 12 hours without an error. ========================================================================= T/V N NB P Q Time Gflops ------------------------------------------------------------------------- W25R2C4 180000 160 16 18 5153.50 7.544e+02 W25R2C4 180000 160 16 18 5150.74 7.549e+02 W25R2C4 180000 160 16 18 5146.35 7.555e+02 W25R2C4 180000 160 16 18 5135.46 7.571e+02 W25R2C4 180000 160 16 18 5160.75 7.534e+02 W25R2C4 180000 160 16 18 5191.60 7.489e+02 W25R2C4 180000 160 16 18 5177.24 7.510e+02 W25R2C4 180000 160 16 18 5159.14 7.536e+02 ========================================================================= NAS Parallel Benchmarks, Class D NAS Parallel Benchmarks, Class C Figure 3: Scaling of the NAS 2.4 Class D benchmarks on the Space Figure 4: Scaling of the NAS 2.4 Class C benchmarks on the Space Simulator. Perfect scaling would be a straight horizontal line for the plot Simulator. The computational problems are smaller than the Class D on the right. results shown in the previous plot, so the scaling is not as good for large numbers of processors. The Hashed Oct-tree Library Figure 5: On the left is the self-similar curve used for load-balancing, while the right figure represents a tree data structure in 2d for a group of centrally condensed particles. Core-Collapse Supernovae This image shows the radial velocities of material in a 0.5◦ slice across the core of a rotating supernova just before the the core bounces. 3-dimensional simulations are required to study the true effects of rotation. Moore’s Law Applied to Beowulf Clusters Moore’s Law Applied to Beowulf Clusters It is interesting to note there have been exactly six years between These factors of improvement over Moore’s Law are also realized in the completion of the Loki and Space Simulator clusters, which results the NPB performance results. For a given cost, the NPB performance in four “Moore’s Law” doublings. Comparing the Loki architecture and exceeds Moore’s Law scaling by 25% for BT, and close to a factor of two price to the Space Simulator, we can see that Moore’s Law scaling has for LU and MG. actually been greatly exceeded in some aspects of the architecture. For the N-body code, the overall price/performance improvement For instance, in 1996, Loki’s disks cost $111 per Gigabyte. For the that clusters have obtained over the past six years has not differed SS, they are close to $1 a Gigabyte, which is a factor of seven beyond much from Moore’s Law extrapolations. Loki obtained performance of the factor of 16 from Moore’s Law over six years. For memory, in the Loki 1.28 Gflop/s for for the N-body code, while the whole SS obtains 180 days it was $7.35 per Megabyte, and is now 23 cents per Megabyte, 2x Gflops, an improvement of a factor of 140. The price ratio between the lower than Moore’s Law would have predicted. machines is 9.4, which when multiplied by 16 for four 18-month Moore’s Law doublings, results in a ratio of 150. Historical Performance of the Treecode Conclusion Year Site Machine Procs Gflop/s Mflops/proc Overall, the Space Simulator provides a reliable computing resource with unbeatable price/performance for our applications. It is fortunate 2003 LANL ASCI QB 3600 2793 775.8 that the niche of small, quiet computers that Shuttle targeted with the 2003 LANL Space Simulator 288 179.7 623.9 Shuttle XPC series was quite well suited to the architecture of the latest 2002 NERSC IBM SP-3(375/W) 256 57.70 225.0 generation of Beowulf clusters.
Recommended publications
  • Green Destiny: a 240-Node Compute Cluster in One Cubic Meter
    Green Destiny: A 240-Node Compute Cluster in One Cubic Meter Wu-chun (Wu) Feng Research & Development in Advanced Network Technology (RADIANT) Computer & Computational Sciences Division Los Alamos National Laboratory LA-UR 02-6127 Outline Where is Supercomputing? Architectures from the Top 500. Evaluating Supercomputers Metrics: Performance & Price/Performance An Alternative Flavor of Supercomputing Supercomputing in Small Spaces Æ Bladed Beowulf Architecture of a Bladed Beowulf Performance Metrics Benchmark Results Discussion & Status Conclusion Acknowledgements & Media Coverage Wu-chun Feng http://www.lanl.gov/radiant [email protected] http://sss.lanl.gov Flavors of Supercomputing (Picture Source: Thomas Sterling, Caltech & NASA JPL) Wu-chun Feng http://www.lanl.gov/radiant [email protected] http://sss.lanl.gov 500 400 SIMD Architectures from the 300 Top 500 Supercomputer List 200 100 0 ProcessorSingle Wu-chun Feng [email protected] Jun-93 Nov-93 Jun-94 MPP Nov-94 Jun-95 Nov-95 Jun-96 Constellation SMP Nov-96 Cluster Jun-97 http://www.lanl.gov/radiant Nov-97 http://sss.lanl.gov Jun-98 Nov-98 Jun-99 Nov-99 Jun-00 Nov-00 Jun-01 Nov-01 Jun-02 Metrics for Evaluating Supercomputers Performance Metric: Floating-Operations Per Second (FLOPS) Example: Japanese Earth Simulator Price/Performance Æ Cost Efficiency Metric: Cost / FLOPS Examples: SuperMike, GRAPE-5, Avalon. Wu-chun Feng http://www.lanl.gov/radiant [email protected] http://sss.lanl.gov Performance (At Any Cost) Japanese Earth Simulator ($400M) Performance Price/Perf Peak 40.00 Tflop $10.00/Mflop Linpack 35.86 Tflop $11.15/Mflop n-Body 29.50 Tflop $13.56/Mflop Climate 26.58 Tflop $15.05/Mflop Turbulence 16.40 Tflop $24.39/Mflop Fusion 14.90 Tflop $26.85/Mflop Wu-chun Feng http://www.lanl.gov/radiant [email protected] http://sss.lanl.gov Price/Performance Cost Efficiency LSU’s SuperMike Performance Price/Perf (2002: $2.8M) Linpack 2210 Gflops $1.27/Mflop U.
    [Show full text]
  • Service Manual
    , , , , , www.sonyweb.co.uk , www.sonyweb.co.uk , , www.sonyweb.co.uk , www.sonyweb.co.uk , , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , SERVICE MANUAL www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk Ver 1-2002J www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk www.sonyweb.co.uk , , Revision History www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , PCG-GRV550 www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk www.sonyweb.co.uk , www.sonyweb.co.uk , , Lineup : PCG-GRV550 www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk For American Area www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk , www.sonyweb.co.uk www.sonyweb.co.uk , www.sonyweb.co.uk
    [Show full text]
  • Memorandum in Opposition to Hewlett-Packard Company's Motion to Quash Intel's Subpoena Duces Tecum
    ORIGINAL UNITED STATES OF AMERICA BEFORE THE FEDERAL TRADE COMMISSION ) In the Matter of ) ) DOCKET NO. 9341 INTEL. CORPORATION, ) a corporation ) PUBLIC ) .' ) MEMORANDUM IN OPPOSITION TO HEWLETT -PACKARD COMPANY'S MOTION TO QUASH INTEL'S SUBPOENA DUCES TECUM Intel Corporation ("Intel") submits this memorandum in opposition to Hewlett-Packard Company's ("HP") motion to quash Intel's subpoena duces tecum issued on March 11,2010 ("Subpoena"). HP's motion should be denied, and it should be ordered to comply with Intel's Subpoena, as narrowed by Intel's April 19,2010 letter. Intel's Subpoena seeks documents necessary to defend against Complaint Counsel's broad allegations and claimed relief. The Complaint alleges that Intel engaged in unfair business practices that maintained its monopoly over central processing units ("CPUs") and threatened to give it a monopoly over graphics processing units ("GPUs"). See CompI. iiii 2-28. Complaint Counsel's Interrogatory Answers state that it views HP, the world's largest manufacturer of personal computers, as a centerpiece of its case. See, e.g., Complaint Counsel's Resp. and Obj. to Respondent's First Set ofInterrogatories Nos. 7-8 (attached as Exhibit A). Complaint Counsel intends to call eight HP witnesses at trial on topics crossing virtually all of HP' s business lines, including its purchases ofCPUs for its commercial desktop, commercial notebook, and server businesses. See Complaint Counsel's May 5, 2010 Revised Preliminary Witness List (attached as Exhibit B). Complaint Counsel may also call HP witnesses on other topics, including its PUBLIC FTC Docket No. 9341 Memorandum in Opposition to Hewlett-Packard Company's Motion to Quash Intel's Subpoena Duces Tecum USIDOCS 7544743\'1 assessment and purchases of GPUs and chipsets and evaluation of compilers, benchmarks, interface standards, and standard-setting bodies.
    [Show full text]
  • The Technology Behind Crusoe™ Processors
    The Technology Behind Crusoe™ Processors Low-power x86-Compatible Processors Implemented with Code Morphing™ Software Alexander Klaiber Transmeta Corporation January 2000 The Technology Behind Crusoe™ Processors Property of: Transmeta Corporation 3940 Freedom Circle Santa Clara, CA 95054 USA (408) 919-3000 http://www.transmeta.com The information contained in this document is provided solely for use in connection with Transmeta products, and Transmeta reserves all rights in and to such information and the products discussed herein. This document should not be construed as transferring or granting a license to any intellectual property rights, whether express, implied, arising through estoppel or otherwise. Except as may be agreed in writing by Transmeta, all Transmeta products are provided “as is” and without a warranty of any kind, and Transmeta hereby disclaims all warranties, express or implied, relating to Transmeta’s products, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose and non-infringement of third party intellectual property. Transmeta products may contain design defects or errors which may cause the products to deviate from published specifications, and Transmeta documents may contain inaccurate information. Transmeta makes no representations or warranties with respect to the accuracy or completeness of the information contained in this document, and Transmeta reserves the right to change product descriptions and product specifications at any time, without notice. Transmeta products have not been designed, tested, or manufactured for use in any application where failure, malfunction, or inaccuracy carries a risk of death, bodily injury, or damage to tangible property, including, but not limited to, use in factory control systems, medical devices or facilities, nuclear facilities, aircraft, watercraft or automobile navigation or communication, emergency systems, or other applications with a similar degree of potential hazard.
    [Show full text]
  • USCOURTS-Ca9-09-35307-1.Pdf
    Case: 09-35307 01/18/2011 ID: 7614842 DktEntry: 67 Page: 1 of 67 FOR PUBLICATION UNITED STATES COURT OF APPEALS FOR THE NINTH CIRCUIT VANESSA SIMMONDS, Plaintiff-Appellant, v. CREDIT SUISSE SECURITIES (USA) LLC; JPMORGAN CHASE & CO., a Delaware corporation, successor in interest to Hambrecht & Quist and Chase Securities Inc.; BANK OF No. 09-35262 AMERICA CORPORATION, a Delaware D.C. No. 2:07-cv- corporation, successor in interest 01549-JLR to Fleetboston Robertson Stephens, Inc.; ONVIA INC., a Delaware corporation formerly known as Onvia.com Inc.; ROBERTSON STEPHENS, INC.; J.P. MORGAN SECURITIES INC., Defendants-Appellees. In Re: SECTION 16(b) LITIGATION 821 Case: 09-35307 01/18/2011 ID: 7614842 DktEntry: 67 Page: 2 of 67 822 SIMMONDS v. CREDIT SUISSE SECURITIES VANESSA SIMMONDS, Plaintiff-Appellant, v. DEUTSCHE BANK SECURITIES INC.; FOUNDRY NETWORKS INC., Nominal No. 09-35280 Defendant, a Delaware D.C. Nos. corporation; MERRILL LYNCH 2:07-cv-01566-JLR PIERCE FENNER & SMITH 2:07-cv-01549-JLR INCORPORATED; J.P. MORGAN SECURITIES INC., Defendants-Appellees. In Re: SECTION 16(b) LITIGATION VANESSA SIMMONDS, Plaintiff-Appellant, v. MERRILL LYNCH & CO. INC., Defendant, and No. 09-35282 D.C. Nos. FINISAR CORPORATION, Nominal Defendant, a Delaware 2:07-cv-01567-JLR 2:07-cv-01549-JLR corporation; MERRILL LYNCH PIERCE FENNER & SMITH INCORPORATED; J.P. MORGAN SECURITIES INC., Defendants-Appellees. In Re: SECTION 16(b) LITIGATION Case: 09-35307 01/18/2011 ID: 7614842 DktEntry: 67 Page: 3 of 67 SIMMONDS v. CREDIT SUISSE SECURITIES 823 VANESSA SIMMONDS, Plaintiff-Appellant, v. MORGAN STANLEY & CO., No. 09-35285 INCORPORATED; LEHMAN BROTHERS, D.C.
    [Show full text]
  • TRANSMETA BREAKS X86 LOW-POWER BARRIER VLIW Chips Use Hardware-Assisted X86 Emulation by Tom R
    MICROPROCESSOR www.MPRonline.com THE REPORTINSIDER’S GUIDE TO MICROPROCESSOR HARDWARE TRANSMETA BREAKS X86 LOW-POWER BARRIER VLIW Chips Use Hardware-Assisted x86 Emulation By Tom R. Halfhill {2/14/00-01} Like moths drawn to a flame, semiconductor startups seem to find the bright but dangerous glow of the x86 market irresistible. Never mind that companies as resourceful as AMD, Cen- taur, Cyrix, IBM, National Semiconductor, and Rise have all charred their wings in the fires of competition with Intel. More than 120 million x86 chips were with a software envelope that translates x86 binaries into sold in the profitable PC market last year, casting off a warmth native code at run time. that lures newly hatched companies from the darkness. While some companies have used the term “emula- The latest newcomer to emerge from its cocoon is tion” to describe the binary-translation process, Transmeta Transmeta. After nearly five years of unprecedented secrecy, founder Dave Ditzel shuns that term, preferring to describe the Santa Clara–based startup finally unveiled its pair of his company’s method of converting x86 instructions into x86-compatible Crusoe processors at a widely covered VLIW instructions as “code morphing” or simply “transla- media event near Silicon Valley last month. The event tion.” Sometimes this process is called dynamic binary received the same sort of overhyped coverage the U.S. Air recompilation. Transmeta’s code-morphing software cer- Force might attract by flinging open the gates to Area 51. A tainly is more advanced than old-fashioned emulators, large crowd of mainstream and business journalists were which slowly convert one type of binary executable into dazzled by marketing claims about “revolutionary” micro- another by translating one instruction at a time.
    [Show full text]
  • Vertigo: Automatic Performance-Setting for Linux
    USENIX Association Proceedings of the 5th Symposium on Operating Systems Design and Implementation Boston, Massachusetts, USA December 9–11, 2002 THE ADVANCED COMPUTING SYSTEMS ASSOCIATION © 2002 by The USENIX Association All Rights Reserved For more information about the USENIX Association: Phone: 1 510 528 8649 FAX: 1 510 548 5738 Email: [email protected] WWW: http://www.usenix.org Rights to individual papers remain with the author or the author's employer. Permission is granted for noncommercial reproduction of the work for educational or research purposes. This copyright notice must be included in the reproduced paper. USENIX acknowledges all trademarks herein. Vertigo: Automatic Performance-Setting for Linux Krisztián Flautner Trevor Mudge [email protected] [email protected] ARM Limited The University of Michigan 110 Fulbourn Road 1301 Beal Avenue Cambridge, UK CB1 9NJ Ann Arbor, MI 48109-2122 Abstract player, game machine, camera, GPS, even the wallet— into a single device. This requires processors that are Combining high performance with low power con- capable of high performance and modest power con- sumption is becoming one of the primary objectives of sumption. Moreover, to be power efficient, the proces- processor designs. Instead of relying just on sleep mode sors for the next generation communicator need to take for conserving power, an increasing number of proces- advantage of the highly variable performance require- sors take advantage of the fact that reducing the clock ments of the applications they are likely to run. For frequency and corresponding operating voltage of the example an MPEG video player requires about an order CPU can yield quadratic decrease in energy use.
    [Show full text]
  • The First International Conference on Mobile Systems, Applications, and Services
    USENIX Association Proceedings of MobiSys 2003: The First International Conference on Mobile Systems, Applications, and Services San Francisco, CA, USA May 5-8, 2003 © 2003 by The USENIX Association All Rights Reserved For more information about the USENIX Association: Phone: 1 510 528 8649 FAX: 1 510 548 5738 Email: [email protected] WWW: http://www.usenix.org Rights to individual papers remain with the author or the author's employer. Permission is granted for noncommercial reproduction of the work for educational or research purposes. This copyright notice must be included in the reproduced paper. USENIX acknowledges all trademarks herein. Operating System Modifications for Task-Based Speed and Voltage Scheduling Jacob R. Lorch Alan Jay Smith Microsoft Research University of California, Berkeley 1 Microsoft Way EECS Department, Computer Science Division Redmond, WA 98052 Berkeley, CA 94720-1776 [email protected] [email protected] Abstract lower voltages mean lower energy consumption. Lower voltages, however, necessitate lower CPU speeds, pre- This paper describes RightSpeed, a task-based speed senting an interesting operating system issue: how to en- and voltage scheduler for Windows 2000. It takes ad- sure that performance remains reasonable while some- vantage of the ability of certain processors, such as those times lowering speed to save energy. from Transmeta and AMD, to dynamically change speed Traditionally, systems use interval-based strategies. and voltage and thus to save energy while running more Such strategies divide time into intervals of fixed length slowly. RightSpeed uses PACE, an algorithm that com- and set the speed for each interval based on recent CPU putes the most energy efficient way to meet task dead- utilization.
    [Show full text]
  • Vol 1-No 2 0801.Qxd
    Antitrust Review Published by the Antitrust and Trade Regulation Practice Group Volume 2, No. 5 May 2004 We are proud to annouce that Robert W. Doyle, Jr. has been nominated to the DC Bar’s Antitrust and Consumer Law Steering Committee. Voting ends on June 4th. In This Issue OUT OF THE ROUGH: PGA “SCORES” ANTITRUST VICTORY An exhibitor of professional golf tournaments successfully defended • Out Of The Rough: PGA “Scores” Antitrust Victory its conduct in refusing to allow a media company to have access to real-time player scores from the PGA's tournaments unless the • Fashion Models Charge company agreed not to sell the information to Internet sites that Price-Fixing: “Ha! Ha! Ha!” compete with the PGA's Internet site. In a decision issued March 31, the 11th Circuit Court of Appeals held that even if the PGA has a • JFTC On Raid Patrol monopoly over the real-time reporting of golf tournament scores, the exhibitor's desire to discourage "free riders" from posting the scores • Gaming Corp. v. Black Hawk Casino Owners on their Internet sites without paying for such information constituted Association: All Roads a lawful "business justification" for PGA's refusal to deal with media Lead To Black Hawk that would not agree to restrict access to the information. Morris Communications Corp. v. PGA Tour, Inc., 2004 WL 627723 (March • District Court Rejects Per 31, 2004). The decision provides an example of where a presumed Se Price-Fixing Analysis monopolist is permitted to engage in a refusal to deal its monopoly For Borders/Amazon products or services in order to protect its economic investment in Websites creating the monopoly.
    [Show full text]
  • Linux Information Sheet Linux Information Sheet
    Linux Information Sheet Linux Information Sheet Table of Contents Linux Information Sheet....................................................................................................................................1 Michael K. Johnson <[email protected]>.......................................................................................1 1.Introduction to Linux............................................................................................................................1 2.Linux Features......................................................................................................................................1 3.Hardware Issues....................................................................................................................................1 4.An Incomplete List of Ported Programs and Other Software...............................................................1 5.Who uses Linux?...................................................................................................................................1 6.Getting Linux........................................................................................................................................1 7.Legal Status of Linux............................................................................................................................2 8.News About Linux................................................................................................................................2 9.The Future.............................................................................................................................................2
    [Show full text]
  • The Technology Behind Crusoe™ Processors: Low-Power X86-Compatible Processors Implemented with Code-Morphing™ Software”
    “The Technology Behind Crusoe™ Processors: Low-Power x86-Compatible Processors Implemented with Code-Morphing™ Software” Alexander Klaiber Transmeta Corporation January 2000 presented by nick black <[email protected]> for cs8803dc 2010-04-15 watch this space for valuable addenda -- BIG MONEY! BIG PRIZES! YOU LOVE IT!! Motivation ● Commercial processor built around binary translation. ● Anyone remember the M680x0 emulator for PowerPC Macs?(*) ● How about PRISM's Epicode + Mica? VEST/AEST on Alpha?(**) ● One of two major GP-VLIW implementations. ● Yes, I absolutely am discounting Multiflow Computer's 125 sales. ● Integrated design of architecture and translator. ● Interesting design space: ● An attempt to reduce power and size of PC2001/x86. ● Not targeted at embedded space, where cost is a main motivator! “A Microprogrammed Implementation of an Architecture Simulation Language” (1977) (*) Tom Hormby's IBM, Apple, RISC, and the Roots of the PowerPC and Steven Levy's Insanely Great. (**) Paul Bolotoff's Alpha: The History in Facts and Comments. Anti-Motivation (*) 1917-10-23, paraphrased from John Reed's Ten Days That Shook the World (1919) pull over; that table's too fat (woop woop) Sources: Transmeta product datasheets, UIUC CS433 “Processor Presentation Series” notes for Transmeta Crusoe, sandpile.org IA-32 Implementation Guides for Crusoe/Efficeon Initial reactions, pre-paper: ● Anyone can run an x86 translator/emulator ● Why wouldn't Intel just build this instead? ● P6 was doing hardware CISC-to-RISC (CRISC) in 1995 ...though dissipating
    [Show full text]
  • Credit Suisse Securities V. Simmonds (Brief in Opposition).Pdf
    NO. 10-1261 In the Supreme Court of the United States CREDIT SUISSE SECURITIES (USA) LLC, ET AL., Petitioners, v. VANESSA SIMMONDS, Respondent. IN RE SECTION 16(b) LITIGATION On Petition for a Writ of Certiorari to the United States Court of Appeals for the Ninth Circuit BRIEF IN OPPOSITION TO PETITION FOR WRIT OF CERTIORARI* Jeffrey I. Tilden William C. Smart Counsel of Record Ian S. Birk Jeffrey M. Thomas KELLER ROHRBACK L.L.P. Mark A. Wilner 1201 Third Avenue Jessica E. Levin Suite 3200 David M. Simmonds Seattle, WA 98101-3052 GORDON T ILDEN THOMAS (206) 623-1900 & CORDELL L.L.P. 1001 Fourth Avenue *This appeal relates Suite 4000 to the appeal Seattle, WA 98154-1007 previously docketed (206) 467-6477 as No. 10-1218 [email protected] Attorneys for Respondent May 12, 2011 Becker Gallagher · Cincinnati, OH · Washington, D.C. · 800.890.5001 i QUESTION PRESENTED Section 16(b) of the Securities Exchange Act of 1934, 15 U.S.C. § 78p(b) (“Section 16(b)”), is the only statute enacted by Congress that directly targets insider trading. Congress designed Section 16(b) to promote the public’s interest in preserving the integrity of United States financial markets. Section 16(b) is a strict liability scheme. It requires statutory insiders to disgorge profits from short-swing transactions in publicly-traded issuer securities. Congress gave exclusive enforcement authority of Section 16(b) to issuers and their shareholders. It also prescribed a two-year statute of limitations. Section 16(a) of the Securities Exchange Act of 1934, 15 U.S.C.
    [Show full text]