IBM XL Fortran Compilers Features
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From Blue Gene to Cell Power.Org Moscow, JSCC Technical Day November 30, 2005
IBM eServer pSeries™ From Blue Gene to Cell Power.org Moscow, JSCC Technical Day November 30, 2005 Dr. Luigi Brochard IBM Distinguished Engineer Deep Computing Architect [email protected] © 2004 IBM Corporation IBM eServer pSeries™ Technology Trends As frequency increase is limited due to power limitation Dual core is a way to : 2 x Peak Performance per chip (and per cycle) But at the expense of frequency (around 20% down) Another way is to increase Flop/cycle © 2004 IBM Corporation IBM eServer pSeries™ IBM innovations POWER : FMA in 1990 with POWER: 2 Flop/cycle/chip Double FMA in 1992 with POWER2 : 4 Flop/cycle/chip Dual core in 2001 with POWER4: 8 Flop/cycle/chip Quadruple core modules in Oct 2005 with POWER5: 16 Flop/cycle/module PowerPC: VMX in 2003 with ppc970FX : 8 Flops/cycle/core, 32bit only Dual VMX+ FMA with pp970MP in 1Q06 Blue Gene: Low frequency , system on a chip, tight integration of thousands of cpus Cell : 8 SIMD units and a ppc970 core on a chip : 64 Flop/cycle/chip © 2004 IBM Corporation IBM eServer pSeries™ Technology Trends As needs diversify, systems are heterogeneous and distributed GRID technologies are an essential part to create cooperative environments based on standards © 2004 IBM Corporation IBM eServer pSeries™ IBM innovations IBM is : a sponsor of Globus Alliances contributing to Globus Tool Kit open souce a founding member of Globus Consortium IBM is extending its products Global file systems : – Multi platform and multi cluster GPFS Meta schedulers : – Multi platform -
IBM Powerpc 970 (A.K.A. G5)
IBM PowerPC 970 (a.k.a. G5) Ref 1 David Benham and Yu-Chung Chen UIC – Department of Computer Science CS 466 PPC 970FX overview ● 64-bit RISC ● 58 million transistors ● 512 KB of L2 cache and 96KB of L1 cache ● 90um process with a die size of 65 sq. mm ● Native 32 bit compatibility ● Maximum clock speed of 2.7 Ghz ● SIMD instruction set (Altivec) ● 42 watts @ 1.8 Ghz (1.3 volts) ● Peak data bandwidth of 6.4 GB per second A picture is worth a 2^10 words (approx.) Ref 2 A little history ● PowerPC processor line is a product of the AIM alliance formed in 1991. (Apple, IBM, and Motorola) ● PPC 601 (G1) - 1993 ● PPC 603 (G2) - 1995 ● PPC 750 (G3) - 1997 ● PPC 7400 (G4) - 1999 ● PPC 970 (G5) - 2002 ● AIM alliance dissolved in 2005 Processor Ref 3 Ref 3 Core details ● 16(int)-25(vector) stage pipeline ● Large number of 'in flight' instructions (various stages of execution) - theoretical limit of 215 instructions ● 512 KB L2 cache ● 96 KB L1 cache – 64 KB I-Cache – 32 KB D-Cache Core details continued ● 10 execution units – 2 load/store operations – 2 fixed-point register-register operations – 2 floating-point operations – 1 branch operation – 1 condition register operation – 1 vector permute operation – 1 vector ALU operation ● 32 64 bit general purpose registers, 32 64 bit floating point registers, 32 128 vector registers Pipeline Ref 4 Benchmarks ● SPEC2000 ● BLAST – Bioinformatics ● Amber / jac - Structure biology ● CFD lab code SPEC CPU2000 ● IBM eServer BladeCenter JS20 ● PPC 970 2.2Ghz ● SPECint2000 ● Base: 986 Peak: 1040 ● SPECfp2000 ● Base: 1178 Peak: 1241 ● Dell PowerEdge 1750 Xeon 3.06Ghz ● SPECint2000 ● Base: 1031 Peak: 1067 Apple’s SPEC Results*2 ● SPECfp2000 ● Base: 1030 Peak: 1044 BLAST Ref. -
Chapter 1-Introduction to Microprocessors File
Chapter 1 Introduction to Microprocessors Expected Outcomes Explain the role of the CPU, memory and I/O device in a computer Distinguish between the microprocessor and microcontroller Differentiate various form of programming languages Compare between CISC vs RISC and Von Neumann vs Harvard architecture NMKNYFKEEUMP Introduction A microprocessor is an integrated circuit built on a tiny piece of silicon It contains thousands or even millions of transistors which are interconnected via superfine traces of aluminum The transistors work together to store and manipulate data so that the microprocessor can perform a wide variety of useful functions The particular functions a microprocessor perform are dictated by software The first microprocessor was the Intel 4004 (16-pin) introduced in 1971 containing 2300 transistors with 46 instruction sets Power8 processor, by contrast, contains 4.2 billion transistors NMKNYFKEEUMP Introduction Computer is an electronic machine that perform arithmetic operation and logic in response to instructions written Computer requires hardware and software to function Hardware is electronic circuit boards that provide functionality of the system such as power supply, cable, etc CPU – Central Processing Unit/Microprocessor Memory – store all programming and data Input/Output device – the flow of information Software is a programming that control the system operation and facilitate the computer usage Programming is a group of instructions that inform the computer to perform certain task NMKNYFKEEUMP Introduction Computer -
MTS on Wikipedia Snapshot Taken 9 January 2011
MTS on Wikipedia Snapshot taken 9 January 2011 PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sun, 09 Jan 2011 13:08:01 UTC Contents Articles Michigan Terminal System 1 MTS system architecture 17 IBM System/360 Model 67 40 MAD programming language 46 UBC PLUS 55 Micro DBMS 57 Bruce Arden 58 Bernard Galler 59 TSS/360 60 References Article Sources and Contributors 64 Image Sources, Licenses and Contributors 65 Article Licenses License 66 Michigan Terminal System 1 Michigan Terminal System The MTS welcome screen as seen through a 3270 terminal emulator. Company / developer University of Michigan and 7 other universities in the U.S., Canada, and the UK Programmed in various languages, mostly 360/370 Assembler Working state Historic Initial release 1967 Latest stable release 6.0 / 1988 (final) Available language(s) English Available programming Assembler, FORTRAN, PL/I, PLUS, ALGOL W, Pascal, C, LISP, SNOBOL4, COBOL, PL360, languages(s) MAD/I, GOM (Good Old Mad), APL, and many more Supported platforms IBM S/360-67, IBM S/370 and successors History of IBM mainframe operating systems On early mainframe computers: • GM OS & GM-NAA I/O 1955 • BESYS 1957 • UMES 1958 • SOS 1959 • IBSYS 1960 • CTSS 1961 On S/360 and successors: • BOS/360 1965 • TOS/360 1965 • TSS/360 1967 • MTS 1967 • ORVYL 1967 • MUSIC 1972 • MUSIC/SP 1985 • DOS/360 and successors 1966 • DOS/VS 1972 • DOS/VSE 1980s • VSE/SP late 1980s • VSE/ESA 1991 • z/VSE 2005 Michigan Terminal System 2 • OS/360 and successors -
SAS/ASSIST ® 9.1 the Correct Bibliographic Citation for This Manual Is As Follows: SAS Institute Inc
Getting Started with SAS/ASSIST ® 9.1 The correct bibliographic citation for this manual is as follows: SAS Institute Inc. 2004. Getting Started with SAS/ASSIST ® 9.1. Cary, NC: SAS Institute Inc. Getting Started with SAS/ASSIST® 9.1 Copyright © 2004, SAS Institute Inc., Cary, NC, USA ISBN 1–59047–205–5 All rights reserved. Produced in the United States of America. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise, without the prior written permission of the publisher, SAS Institute Inc. U.S. Government Restricted Rights Notice. Use, duplication, or disclosure of this software and related documentation by the U.S. government is subject to the Agreement with SAS Institute and the restrictions set forth in FAR 52.227–19, Commercial Computer Software-Restricted Rights (June 1987). SAS Institute Inc., SAS Campus Drive, Cary, North Carolina 27513. 1st printing, January 2004 SAS Publishing provides a complete selection of books and electronic products to help customers use SAS software to its fullest potential. For more information about our e-books, e-learning products, CDs, and hard-copy books, visit the SAS Publishing Web site at support.sas.com/pubs or call 1-800-727-3228. SAS® and all other SAS Institute Inc. product or service names are registered trademarks or trademarks of SAS Institute Inc. in the USA and other countries. ® indicates USA registration. IBM® and all other International Business Machines Corporation product or service names are registered trademarks or trademarks of International Business Machines Corporation in the USA and other countries. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
NBS FORTRAN Test Programs 3^1 No "I Volume 1- Documentation for Versions 1 and 3 V.I
j I i Vt NBS SPECIAL PUBLICATION 399 J Volume 1 U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards] National Bureau of Standards Library, £-01 Admin. BIdg. ncT 1 1981 13102^1 NBS FORTRAN Test Prog Volume 1-Documentation for Versions 1 and 3 NATIONAL BUREAU OF STANDARDS The National Bureau of Standards^ was established by an act of Congress March 3, 1901. The Bureau's overall goal is to strengthen and advance the Nation's science and technology and facilitate their effective application for public benefit. To this end, the Bureau conducts research and provides: (1) a basis for the Nation's physical measurement system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau consists of the Institute for Basic Standards, the Institute for Materials Research, the Institute for Applied Technology, the Institute for Computer Sciences and Technology, and the Office for Information Programs. THE INSTITUTE FOR BASIC STANDARI>S provides the central basis within the United States of a complete and consistent system of physical measurement; coordinates that system with measurement systems of other nations; and furnishes essential services leading to accurate and uniform physical measurements throughout the Nation's scientific community, industry, and commerce. The Institute consists of a Center for Radiation Research, an Office of Meas- urement Services and the following divisions: Applied Mathematics — Electricity — Mechanics -
On the Need of Compilepretation for Legacy Languages
On the Need of Compilepretation for Legacy Languages Vadim Zaytsev Raincode [email protected] Abstract handle it. The third family of reasons lies somewhere in be- The context of this work is the research and development tween: system elements could have been written in HLASM effort that went into creating a product called Raincode As- for optimisation purposes, to reduce program size, running sembler Compiler (Blagodarov et al. 2016), a reimplemen- time, memory footprint, implement very sophisticated er- tation of the IBM mainframe assembler language retargeted ror recovery strategies, fine-tune memory allocation. On the and replatformed for .NET Framework (ECMA-335 June grand scheme of things this may seem like a detail, but such 2012). The assembler language for IBM System/360 and details are what usually make grand schemes fall apart. In newer mainframes has existed and evolved since 1964 (Abel our case, such considerations demanded high efficiency and 1989; Carrano 1987; GC24-3414-7 1970; GC26-4943-06 productivity of our “compiler”. 2013; Kacmar 1988; McQuillen 1975; McQuillen and Prince Writing a language processor by the book seems to be 1987; O’Kane 2011; SA22-7832-09 2012; SC26-4940-06 straightforward (Grune et al. 2012): you parse the code, you 2013; SC26-4941-06 2013). The current version is called handle contexts and static semantics, you generate some in- High Level Assembler, or HLASM, and is widely accepted termediate representation, optimise it, generate code, opti- among mainframe developers and architects as a “second mise it and finally interpret it or let it be interpreted by the generation programming language”, thus positioning it be- target machine directly. -
YES/MVS: a Continuous Real Time Expert System
From: AAAI-84 Proceedings. Copyright ©1984, AAAI (www.aaai.org). All rights reserved. YEWMVS: A Continuous Real Time Expert System J.H. Griesmer, S.J. Hong, M. Karnaugh, J.K. Kastner, M.I. Schor Expert Systems Group, Mathematical Science Department R.L. Ennis, D.A. Klein, K.R. Milliken, H.M. VanWoerkom Installation Management Group, Computer Science Department IBM T. J. Watson Research Center Yorktown Heights, NY 10598 ABSTRACT: as they arise. A long training period is required to produce a skilled operator; trained operators, in turn, are often pro- YES/MVS (Yorktown Expert System for MVS opera- moted to systems programmers. The resulting shortage of tors) is a continuous, real time expert system that exerts skilled operators and the increasing complexity of the op- interactive control over an operating system as an aid to erator’s job calls for more powerful installation manage- computer operators. This paper discusses the YES/MVS ment tools. We have chosen the management of a Multiple system, its domain of application, and issues that arise in Virtual Storage (MVS) operating system, the most widely the design and development of an expert system that runs used operating system on large IBM mainframe computers, continuously in real time. as an example of the application of expert systems to problems in computer installation management. I INTRODUCTION B. Use of Expert System Techniques Each installation has a different configuration and dif- ferent local policies for computer operations, both of which Expert systems techniques are beginning to be success- change over time. The software running in a large com- fully applied to real problems in industry, although only a puter installation represents hundreds of man-years of de- handful are reportedly in use so far. -
Green500 List
Making a Case for a Green500 List S. Sharma†, C. Hsu†, and W. Feng‡ † Los Alamos National Laboratory ‡ Virginia Tech Outline z Introduction What Is Performance? Motivation: The Need for a Green500 List z Challenges What Metric To Choose? Comparison of Available Metrics z TOP500 as Green500 z Conclusion W. Feng, [email protected], (540) 231-1192 Where Is Performance? Performance = Speed, as measured in FLOPS W. Feng, [email protected], (540) 231-1192 What Is Performance? TOP500 Supercomputer List z Benchmark LINPACK: Solves a (random) dense system of linear equations in double-precision (64 bits) arithmetic. Introduced by Prof. Jack Dongarra, U. Tennessee z Evaluation Metric Performance, as defined by Performance (i.e., Speed) speed, is an important metric, Floating-Operations Per Second (FLOPS) but… z Web Site http://www.top500.org z Next-Generation Benchmark: HPC Challenge http://icl.cs.utk.edu/hpcc/ W. Feng, [email protected], (540) 231-1192 Reliability & Availability of HPC Systems CPUs Reliability & Availability ASCI Q 8,192 MTBI: 6.5 hrs. 114 unplanned outages/month. HW outage sources: storage, CPU, memory. ASCI 8,192 MTBF: 5 hrs. (2001) and 40 hrs. (2003). White HW outage sources: storage, CPU, 3rd-party HW. NERSC 6,656 MTBI: 14 days. MTTR: 3.3 hrs. Seaborg SW is the main outage source. Availability: 98.74%. PSC 3,016 MTBI: 9.7 hrs. Lemieux Availability: 98.33%. Google ~15,000 20 reboots/day; 2-3% machines replaced/year. (as of 2003) HW outage sources: storage, memory. Availability: ~100%. MTBI: mean time between interrupts; MTBF: mean time between failures; MTTR: mean time to restore Source: Daniel A. -
IBM Power Systems Compiler Strategy
Software Group Compilation Technology IBM Power Systems Compiler Strategy Roch Archambault IBM Toronto Laboratory [email protected] ASCAC meeting | August 11, 2009 @ 2009 IBM Corporation Software Group Compilation Technology IBM Rational Disclaimer © Copyright IBM Corporation 2008. All rights reserved. The information contained in these materials is provided for informational purposes only, and is provided AS IS without warranty of any kind, express or implied. IBM shall not be responsible for any damages arising out of the use of, or otherwise related to, these materials. Nothing contained in these materials is intended to, nor shall have the effect of, creating any warranties or representations from IBM or its suppliers or licensors, or altering the terms and conditions of the applicable license agreement governing the use of IBM software. References in these materials to IBM products, programs, or services do not imply that they will be available in all countries in which IBM operates. Product release dates and/or capabilities referenced in these materials may change at any time at IBM’s sole discretion based on market opportunities or other factors, and are not intended to be a commitment to future product or feature availability in any way. IBM, the IBM logo, Rational, the Rational logo, Telelogic, the Telelogic logo, and other IBM products and services are trademarks of the International Business Machines Corporation, in the United States, other countries or both. Other company, product, or service names may be trademarks or service -
Power Vector Intrinsic Programming Reference
REVIEW DRAFT www.openpowerfoundation.org Power Vector Intrinsic Program- February 11, 2020 Revision 1.0.0_prd2 ming Reference Power Vector Intrinsic Programming Reference System Software Work Group <[email protected]> OpenPower Foundation Revision 1.0.0_prd2 (February 11, 2020) Copyright © 2017-2020 OpenPOWER Foundation Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 REVIEW DRAFT - Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. The limited permissions granted above are perpetual and will not be revoked by OpenPOWER or its successors or assigns. This document and the information contained herein is provided on an "AS IS" basis AND TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, THE OpenPOWER Foundation AS WELL AS THE AUTHORS AND DEVELOPERS OF THIS STANDARDS FINAL DELIVERABLE OR OTHER DOCUMENT HEREBY DISCLAIM ALL OTHER WARRANTIES AND CONDITIONS, EITHER EXPRESS, REVIEW DRAFT - IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES, DUTIES OR CONDITIONS OF MERCHANTABILITY, OF FITNESS FOR A PARTICULAR PURPOSE, OF ACCURACY OR COMPLETENESS OF RESPONSES, OF RESULTS, OF WORKMANLIKE EFFORT, OF LACK OF VIRUSES, OF LACK OF NEGLIGENCE OR NON-INFRINGEMENT. OpenPOWER, the OpenPOWER logo, and openpowerfoundation.org are trademarks or registered trademarks of OpenPOWER Foundation, Inc., registered in many jurisdictions worldwide.