Architecture of 80286 Microprocessor

Introduction

The 80286 microprocessor was introduced by Intel in 1983. It operates at 8 or 10 MHz and can execute instructions up to 6 times as fast as the 8086. Like 8086, the 80286 is 16 bit microprocessor but it can address up to 16 mega bytes of real memory using its 24 address lines. The 80286 includes all of the instructions found on the 8086 and some added new features. Among these new features are:  Memory Management.  Task Management.  Protection Mechanism.  Support for Operating Systems. The 80286 microprocessor can operate in two modes:

 Real address mode.

 Protected virtual address mode (protected mode). Real mode operation allows the microprocessor to address only the 1st 1 Megabyte of memory space, all programs and operating systems written for the 8086 microprocessor will run without modifications. Protected mode memory addressing (80286 and above) allows access to data and programs above the 1st 1 M byte of memory as well as within the 1st 1 M byte of memory. Addressing this extended section of the memory system requires a change to the segment plus offset addressing scheme used with real mode. In protected mode, the offset is still used to access information located within the memory segment. The difference is that in place of the segment address, the segment register contains a selector that selects a descriptor describes the memory segment's Location, Length, and Access Rights.

The selector located in the segment register selects one of 8192 descriptors from one of two tables of descriptors. There are two descriptor tables used with the segment register: one contains global descriptors and the other contains local descriptors. The global descriptors contain segment definition that applies to all programs, while the local descriptors are usually unique to an application. Each descriptor table contains 8192 descriptors, so a total of 16384 descriptors are available to an application at any time. Because the descriptor describes a memory segment (of up to 64 KB) this allows up to 16384 memory segments to be described for each application.

15 0

Selector TI RPL

13-bits 1-bit 2-bits

Figure 3.1 Segment register functions in protected mode 80286 Internal Structures The principle built- in features in 80286 are: memory management, protection mechanism, task management and support for operating systems. Pipelining already a feature of the design of the 8086 is used extensively in the 80286. The hardware implementation of this functionality gives rise to very complex chip design which is divided into four relatively independent modules (units): 1. Bus Unit 2. Instruction Unit 3. Execution Unit 4. Address Unit 80286 Internal Structures

Address Bus Address Bus Unit Unit Data Bus

Execution Instruction Unit Unit

Figure 3.2 Functional Units of 80286 µp  Bus Unit: This unit implements input/output and memory operations, data transfer and control signal generation for the processor bus. The bus unit uses a pipelining technique, by reading instructions before they are needed. This unit can store up to 6 bytes of instructions.  Instruction Unit: Gets instructions from the queue of 6 bytes fetched by the bus unit, decodes these instructions and stores the decoded form in a queue containing up to 3 fully decoded instructions.  Execution Unit:

Fetches decoded instructions (from instruction unit) and execute them.

 Address Unit:

This unit implements all the operations necessary to generate real addresses to pass to the bus unit. The protection mechanism provided in protected mode is also implemented in the address unit.