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TPS59650EVM-753 Evaluation Module (EVM) Is a Complete Solution for Intel™ IMVP7 Serial VID(SVID) Power System from a 9V-20V Input Bus

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TPS59650EVM-753 Evaluation Module (EVM) Is a Complete Solution for Intel™ IMVP7 Serial VID(SVID) Power System from a 9V-20V Input Bus User's Guide SLUU896–March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System The TPS59650EVM-753 evaluation module (EVM) is a complete solution for Intel™ IMVP7 Serial VID(SVID) Power System from a 9V-20V input bus. This EVM uses the TPS59650 for IMVP7 - 3-Phase CPU and 2-Phase GPU Vcore controller, the TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4 Memory rail (1.2VDDQ, 0.6VTT and 0.6VTTREF) and also uses the (CSD87350Q5D) a 5mm x 6mm TI’s power block MOSFETs that uses Powerstack™ technology with high-side and low-side MOSFETs for high power density and superior thermal performance. Contents 1 Description ................................................................................................................... 5 1.1 Typical Applications ................................................................................................ 5 1.2 Features ............................................................................................................. 5 2 TPS59650EVM-753 Power System Block Diagram .................................................................... 6 3 Electrical Performance Specifications .................................................................................... 7 4 Test Setup ................................................................................................................... 8 4.1 Test Equipment ..................................................................................................... 8 4.2 Recommended Wire Gauge ...................................................................................... 9 4.3 Recommended Test Setup ....................................................................................... 9 4.4 USB Cable Connections ......................................................................................... 10 4.5 Input Connections ................................................................................................ 10 4.6 Output Connections .............................................................................................. 11 5 Configuration ............................................................................................................... 11 5.1 CPU and GPU Configuration ................................................................................... 11 5.2 1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration ...................................................... 13 5.3 1.05V VCCIO Configuration ..................................................................................... 13 6 Test Procedure ............................................................................................................ 14 6.1 Line/Load Regulation and Efficiency Measurement Procedure ............................................ 14 6.2 Equipment Shutdown ............................................................................................ 17 7 Performance Data and Typical Characteristic Curves ................................................................ 18 7.1 CPU 3-Phase Operation ......................................................................................... 18 7.2 CPU 2-Phase Operation ......................................................................................... 21 7.3 CPU1-Phase Operation .......................................................................................... 25 7.4 GPU 2 Phase Operation ......................................................................................... 29 7.5 GPU 1 Phase Operation ......................................................................................... 32 7.6 1.05V VCCIO ...................................................................................................... 36 7.7 1.2V VDDQ ........................................................................................................ 39 8 EVM Assembly Drawings and PCB Layout ............................................................................ 42 9 Bill of Materials ............................................................................................................. 47 10 Schematics ................................................................................................................. 50 List of Figures 1 TPS59650EVM-753 Power System Block Diagram.................................................................... 6 2 TPS59650EVM-753 EVM Illustration..................................................................................... 7 Powerstack is a trademark of Texas Instruments. Intel is a trademark of Intel. All other trademarks are the property of their respective owners. SLUU896–March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU 1 Submit Documentation Feedback SVID Power System Copyright © 2012, Texas Instruments Incorporated www.ti.com 3 USB Cable ................................................................................................................... 8 4 TPS59650EVM-753 Recommended Test Set Up..................................................................... 10 5 TPS59650EVM-753 CPU GUI set up Window ........................................................................ 15 6 TPS59650EVM-753 GPU GUI set up Window ........................................................................ 16 7 CPU3 Efficiency ........................................................................................................... 18 8 CPU3 Load regulation .................................................................................................... 18 9 CPU3 Enable Turn on .................................................................................................... 18 10 CPU3 Enable Turn off .................................................................................................... 18 11 CPU3 Switching Node(Ripple) .......................................................................................... 18 12 CPU3 Dynamic VID: SetVID-Slow/Slow................................................................................ 18 13 CPU3 Dynamic VID:SetVID-Fast/Fast ................................................................................. 19 14 CPU3 Dynamic VID:SetVID-Decay/Fast ............................................................................... 19 15 CPU3 Output Load Insertion with OSR/USR middle level .......................................................... 19 16 CPU3 Output Load Release with OSR/USR middle level............................................................ 19 17 CPU3 Bode Plot at 12Vin, 1.05V/60A .................................................................................. 20 18 CPU3 MOSFET ........................................................................................................... 20 19 CPU3 IC .................................................................................................................... 20 20 CPU2 Efficiency ........................................................................................................... 21 21 CPU2 Load regulation .................................................................................................... 21 22 CPU2 Enable Turn on .................................................................................................... 21 23 CPU2 Enable Turn off .................................................................................................... 21 24 CPU2 Switching Node(Ripple) .......................................................................................... 22 25 CPU2 Dynamic VID: SetVID-Slow/Slow................................................................................ 22 26 CPU2 Dynamic VID:SetVID-Fast/Fast ................................................................................. 22 27 CPU2 Dynamic VID:SetVID-Decay/Fast ............................................................................... 22 28 CPU2 Output Load Insertion with OSR/USR middle level .......................................................... 23 29 CPU2 Output Load Release with OSR/USR middle level............................................................ 23 30 CPU2 Bode Plot at 12Vin, 1.05V/55A .................................................................................. 24 31 CPU2 MOSFET ........................................................................................................... 24 32 CPU2 IC .................................................................................................................... 24 33 CPU1 Efficiency ........................................................................................................... 25 34 CPU1 Load regulation .................................................................................................... 25 35 CPU1 Enable Turn on .................................................................................................... 25 36 CPU1 Enable Turn off .................................................................................................... 25 37 CPU1 Switching Node ................................................................................................... 25 38 CPU1 Switching node and Ripple ...................................................................................... 25 39 CPU1 Dynamic VID:SetVID-Slow/Slow ................................................................................ 26 40 CPU1 Dynamic VID:SetVID-Fast/Fast ................................................................................. 26 41 CPU1
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