( 12 ) United States Patent ( 10) Patent No

US010388058B2 ( 12 ) United States Patent ( 10) Patent No. : US 10 , 388, 058 B2 Goossen et al. (45 ) Date of Patent: Aug. 20 , 2019 (54 ) TEXTURE RESIDENCY HARDWARE ( 56 ) References Cited ENHANCEMENTS FOR GRAPHICS PROCESSORS U . S . PATENT DOCUMENTS 6 ,707 ,458 B1 * 3 /2004 Leather ...... G06T 15 /04 (71 ) Applicant: Microsoft Technology Licensing , LLC , 345 / 582 Redmond , WA (US ) 7 , 193 ,627 B1 * 3/ 2007 Donovan ...... G06T 15 /04 345 / 428 (72 ) Inventors : James Andrew Goossen , Sammamish , 8 ,587 , 602 B2 11/ 2013 Grossman et al . WA (US ) ; Matthew William Lee , 2008 /0106552 AL 5 /2008 Everitt Sammamish , WA (US ); Mark S . 2011 /0157205 Al 6 / 2011 Tao et al . 2011/ 0157206 A1 * 6 / 2011 Duluk , Jr...... GO6T 15 /04 Grossman , Palo Alto , CA (US ) 345 / 582 2011/ 0157207 AL 6 / 2011 Hall et al. ( 73 ) Assignee: Microsoft Technology Licensing , LLC , 2015 /0089146 AL 3 /2015 Gotwalt et al . Redmond , WA (US ) 2015 /0379730 A1 12 / 2015 Tsakok et al. ( * ) Notice : Subject to any disclaimer , the term of this patent is extended or adjusted under 35 OTHER PUBLICATIONS U .S .C . 154 (b ) by 108 days . Harrison , et al. , “ AES Encryption Implementation and Analysis on Commodity Graphics Processing Units ” , In proceedings of the ( 21) Appl. No. : 15 /608 ,003 international Workshop on Cryptographic Hardware and Embedded ( 22 ) Filed : May 30 , 2017 Systems, Published on : Sep . 10 , 2007, 10 pages . (65 ) Prior Publication Data * cited by examiner US 2018 / 0232940 A1 Aug. 16 , 2018 Primary Examiner — Edward Martello Related U . S . Application Data (57 ) ABSTRACT (60 ) Provisional application No . 62 /459 ,726 , filed on Feb . Systems, methods, apparatuses , and software for graphics 16 , 2017 . processing systems in computing environments are provided herein . In one example , a method of handling tiled resources (51 ) Int. Ci. in graphics processing environments is presented . The G06T 15 /04 ( 2011 .01 ) method includes establishing , in a graphics processing unit , G06T 15 /00 ( 2011 .01 ) a residency map having values determined from memory G06T 15 /50 ( 2011 .01 ) residency properties of a texture resource, and sampling (52 ) U . S . Cl. from the residency map at a specified location to determine CPC ...... G06T 15 /04 (2013 . 01 ); G06T 15 / 005 a residency map sample for the texture resource at the ( 2013 .01 ) ; GO6T 15 /503 (2013 .01 ) ; G06T specified location , where the residency map sample indi 2200 /28 (2013 . 01 ) ; G06T 2210/ 36 ( 2013 .01 ) cates at least an initial level of detail presently resident and ( 58 ) Field of Classification Search a smoothing component to reach a next level of detail . None See application file for complete search history . 20 Claims, 9 Drawing Sheets

WIDTH = 2048 TEXELS RU 303 304 302 MIP LEVEL 4 MIP LEVEL 3 MP LEVEL 2

HEIGHT=2048TEXELS MIP LEVEL 1 305 RESIDENT MEMORY NON -RESIDENT MEMORY 10 : 30 20 8 .0 MIP LEVEL O 2010 2010 2048 x 2048 partially resident texture SA 4 .0 : 4 . 0 4 .0 4 . 0 with associated residency map 0 4 .0 4 .0 4 .0 4 .0 30 30 30 30 4 . 0 4 .0 4 . 0 4 .0 3. 0 3 .0 3. 0 3 .0 4 .0 4 .0 4 .0 4 .0 8x8 RESIDENCY MAP U . S . Patent Aug . 20, 2019 Sheet 1 of 9 US 10 , 388 ,058 B2

CACHEDTILES121 RESIDENCYMAP122 PROCESSOR130 PROCESSOR120 150 SYSTEM GRAPHICS SYSTEM MEMORY131 152

PROCESSOR130 GRAPHICS120 THERMALMGMTMEMORY 131 FIGURE1 ASSEMBLYELEMENTS ENCLOSURE :STORAGE COMMIF POWER USERSYSTEM 110 101

100 U . S . Patent Aug . 20, 2019 Sheet 2 of 9 US 10 , 388 ,058 B2

. .

. 266 . . MAP265 .

. .

. SAMPLER

. RESDENCY RESIDENCY . . .

. .

. 263 264 262 TILEMAP . . UNIT .

. TEXTURE TEXTURE . . MEMORY

. .

. . . 260 . . 261 .

. . SHADER

RESIDENCY LOG267 CACHEDTILES240 RESIDENCYMAP241 FIGURE2 CACHE221 GPU 220

200 250 U . S . Patent Aug. 20 , 2019 Sheet 3 of 9 US 10 , 388 ,058 B2

3,0 3,0 3,0 $3.00 304MPLEVEL AMIPLEVEL4 3,0 3,0 3.0 3,0 4.0 04.04 3.0 3,0 4.0 304.0 0

3.0 3,0 4.0 3,04. MIPLEVEL3 30 wwwwwwwwwwwww 8x8RESIDENCYMAP 0 ko200 100.01 3.0 10 10100 0 30303 3.0

min 3.0 o MIPLEVEL2 2 305 302

tuturo MIPLEVEL1 NON-RESIDENTMEMORY RESIDENTMEMORY 2048xpartiallyresidenttexture withassociatedresidencymap FIGURE3 301

tututututututet tttttttttttttt

DE.

WIDTH=2048TEXELS AAAAAAAAAAAA AAN TAMAAN

. MIPLEVELO

SWAX

TEXELS 2048 = HEIGHT atent Aug . 20 , 2019 Sheet 4 of 9 US 10 , 388 ,058 B2

WWW

RAWDATABILINEARLYSAMPLEDAS IFITWEREA2048xTEXTURE, WITHBILINEARWEIGHTSADJUSTED TOSHARPENFILTERING

403

Bilinearfilteringweightsadjustedtosharpenthe resultingfilteredimage SAMPLEDASIFITWEREA FIGURE4 RAWDATABILINEARLY 2048xTEXTURE

RAWDATA(4X4TEXELS)

0. 401 U . S . Patent Aug . 20, 2019 Sheet 5 of 9 US 10 , 388 ,058 B2

31-STANDARDBILINEARFILTERING -MODIFIEDBILINEARFILTERING .RAWSAMPLEVALUE 510 512 'Ucoordinate FIGURE5 51001 One-dimensionalviewofmodifiedbilinearfilteringforresidencymaps, comparedtostandardbilinearandrawtexeldata

512

level mip U . S . Patent Aug . 20, 2019 Sheet 6 of 9 US 10 , 388 ,058 B2

DRAM FIGURE6 610 612 611 -613 mm614 -615 w

COMPUTEMIPMAP(LOD) VALUE(S) FRACTIONALLODVALUE,AND INPUTSFROMSHADERPROGRAM FRACTIONALVALUEUSING GRADIENTS COMPUTETEXELSAMPLE ADDRESSESUSINGTEXTURE COORDINATESANDDISCRETELOD RETRIEVEDATACORRESPONDINGTO TEXELSAMPLEADDRESSES,OR SUBMITMEMORYREQUESTSTO MEMORYTOFETCHTHEDATA USINGTEXELSAMPLEDATA, TEXTURECOORDINATES, SAMPLERDESCRIPTION,COMPUTE THEFILTEREDRESULT RETURNRESULTTOSHADERPROGRAM

TEXTUREADDRESSING STEP1 TEXTURE ADDRESSINGSTEP2 TEXTURE CACHE TEXTURE FILTERING U . S . Patent Aug . 20, 2019 Sheet 7 of 9 US 10 , 388 ,058 B2

RESIDENCY MAP ADDRESSING RESIDENCY MAPCACHE RESIDENCY MAPFILTERING

717- 718 719

. . FIGURE7 .

CORRESPONDINGTO . COMPUTERESIDENCYMAP ADDRESSESUSINGTEXTURE RETRIEVEDATA . USINGTEXTURE COORDINATESAND RESIDENCYMAPSAMPLE DATA,COMPUTETHEFILTEREDRESULT DRAM RESIDENCYMAPADDRESSES .

COORDINATES .

212 713 -716 714 715 naman -

PROGRAM711 COMPUTEMIPMAP(LOD) DISCRETELODVALUE(S) TEXELSAMPLEADDRESSES,ORSUBMIT MEMORYREQUESTSTO COORDINATES,FRACTIONALLODVALUE RETURNRESULTTO INPUTSFROMSHADER "INTEGER.FRACTIONVALUEUSING GRADIENTS CLAMPLODVALUEWITHFILTERED RESIDENCYMAPVALUE COMPUTETEXELSAMPLEADDRESSES USINGTEXTURECOORDINATESAND RETRIEVEDATACORRESPONDINGTO FETCHTHEDATA USINGTEXELSAMPLEDATA,TEXTURE ANDSAMPLERDESCRIPTION,COMPUTE THEFILTEREDRESULT SHADERPROGRAM

TEXTURE ADDRESSING STEP1 "FRACTIONAL CLAMP TEXTURE ADDRESSING STEP2 TEXTURE CACHE TEXTURE FILTERING U . S . Patent Aug . 20, 2019 Sheet 8 of 9 US 10 , 388 ,058 B2

~811 812 813 814 ·815 -

SAMPLEFROMTHERESIDENCYMAPATASPECIFIEDLOCATIONTODETERMINE ESTABLISHCONCURRENTCACHERESIDENCYOFTEXTUREDATAINACCORDANCE PERFORMANINTERPOLATIONPROCESSBETWEENTHEINITIALLEVELOFDETAIL INTEGERPORTIONANDFRACTIONALTOBEEMPLOYEDINAFURTHER ESTABLISHARESIDENCYMAPHAVINGVALUESDETERMINEDFROMMEMORY RESIDENCYPROPERTIESOFATEXTURERESOURCE RESIDENCYMAPSAMPLEFORTHETEXTURERESOURCE WITHTHEINITIALLEVELOFDETAILCORRESPONDINGTOANINTEGERPORTION THERESIDENCYMAPSAMPLEANDANADDITIONALLEVELOFDETAILBEYOND INITIALLEVELOFDETAIL ANDTHENEXTLEVELOFDETAILTORENDERATLEASTONETEXTUREREGION BASEDATLEASTONABLENDFACTORDERIVEDFROMFRACTIONAL PORTIONOFTHERESIDENCYMAPSAMPLE UPDATETHERESIDENCYMAPATSPECIFIEDLOCATIONWITHANUPDATED BLENDINGPROCESS FIGURE8

810 U . S . Patent Aug . 20, 2019 Sheet 9 of 9 US 10 , 388 ,058 B2

TeTransVOforvresmapHalfV(inactive) Tf-TransU0forusresmapHalfu(inactive)

Ta=TransVO(active)Tb-TransUo(active) Tc=TransV1(active) Td=TransU1(active)

TC resmap(Uine+1,Vint)=2 11Vine1)=+Uing,Tresmap( +

---- u,v FIGURE9 Tf1 * TbTd RESIDENCYMAPFILTERING WY resmap(Uirt,Vint)=1i 31)=UintVin+,resmap( resmapHalfv] + resmapHalfU

900 US 10 , 388 , 058 B2 TEXTURE RESIDENCY HARDWARE implementations are described in connection with these ENHANCEMENTS FOR GRAPHICS drawings, the disclosure is not limited to the implementa PROCESSORS tions disclosed herein . On the contrary , the intent is to cover all alternatives, modifications , and equivalents . RELATED APPLICATIONS 5 FIG . 1 illustrates a graphics processing environment in an implementation . This application hereby claims the benefit of and priority to U . S . Provisional Patent Application 62 / 459 ,726 , titled FIG . 2 illustrates a graphics processor in an implementa " TEXTURE RESIDENCY HARDWARE ENHANCE tion . MENTS FOR GRAPHICS PROCESSORS, ” filed Feb . 16 , FIG . 3 illustrates an example texture information and 2017 , which is hereby incorporated by reference in its 10 residency map in an implementation . entirety . FIG . 4 illustrates an example filtering in an implementa tion . BACKGROUND FIG . 5 illustrates an example filtering in an implementa tion . Computing systems, such as personal computers , portable 15 FIG . 6 illustrates a method of operating a graphics pro computing platforms, gaming systems, and servers , can cessing environment in an implementation . include graphics processors along with main /central proces FIG . 7 illustrates a method of operating a graphics pro sors . These graphics processors , sometimes referred to as cessing environment in an implementation . graphics processing units (GPUs ) , can be integrated into the FIG . 8 illustrates a method of operating a graphics pro central processors or discretely provided on separate add -in 20 cessing environment in an implementation . cards, among other configurations . User applications, oper - FIG . 9 illustrates an example residency map filtering in an ating systems, video games , or other software elements can implementation . interface with GPUs using various application programming interfaces (APIs ) that allow for standardized software / logi DETAILED DESCRIPTION cal interfaces between the software elements and various 25 GPU hardware elements . Graphics processing units (GPUs ) include various inter Most GPUs can render both two - dimensional (2D ) and nal hardware components, such as processing stages , three -dimensional (3D ) graphics data for display, such as memory elements, and other pipelined processing elements . graphics data from operating systems, productivity applica - User content that is rendered by GPUs, such as video game tions , entertainment media , scientific analysis , gaming soft - 30 content, is expected to continue growing in complexity over ware , or other graphics data sources . Within the GPUs, time, but graphics hardware constraints such as bandwidth various internal stages can process graphics data into ren and memory capacity are not expected to grow at a similar dered images for display on a suitable display device . In rate . The techniques discussed herein provide improved many GPUs, these internal stages comprise a graphics efficiency in usage of residency maps for GPUs. The layout pipeline that can take representations of scenes or user 35 of the residency maps herein provides for viable hardware interfaces and render these into images for output to various implementations , leading to faster and more efficient ren display devices. Among these GPU stages are texture map dering of graphics for computing systems. ping stages that provide graphical details , surface textures, GPUs and associated support software can render 3D colors , or other elements for portions of rendered images . graphics , in some examples , by applying ' texture ' data to Texture maps are typically applied to surfaces of shapes 40 target objects within a 3D space rendered to a user. Texture within 3D data , and this combination is rendered as a 2D data provide surface details , surface graphics , texturing , or image for output to display devices . other surface features to represent objects with desired Overview surface details . Elements of software or the GPU can ‘map ' Systems, methods, apparatuses, and software for graphics the texture data onto the objects , such as by determining processing systems in computing environments are provided 45 relationships among geometric coordinates of the texture herein . In one example , a method of handling tiled resources data and the objects . In many examples, the texture data in graphics processing environments is presented . The comprises 2D image data that is mapped onto the surfaces of method includes establishing , in a graphics processing unit, a 3D object formed from discrete triangles /polygons . This a residency map having values determined from memory mapping process can be processor- intensive and require residency properties of a texture resource , and sampling 50 large amounts of memory to accomplish . Moreover, several from the residency map at a specified location to determine functions of the mapping process might be included soft a residency map sample for the texture resource at the ware that drives the GPU instead of hardware of the GPU specified location , where the residency map sample indi- itself , due in part to complexity and the amount of data that cates at least an initial level of detail presently resident and is usually manipulated . a smoothing component to reach a next level of detail . 55 To aid in the memory - intensive nature of the texture This Overview is provided to introduce a selection of mapping process , partially resident textures ( PRTs ) have concepts in a simplified form that are further described been developed . These PRTs partially map texture data only below in the Detailed Description . It may be understood that to portions of objects presently needed to be rendered , such this Overview is not intended to identify key features or as due to viewpoint characteristics of a user, obstruction by essential features of the claimed subject matter, nor is it 60 other objects , proximity to a viewer, or other factors . Mip intended to be used to limit the scope of the claimed subject mapping can also be included in this process to pre - compute matter. a series or set of smaller and smaller texture representations to suit different levels of detail for the textures . This mip BRIEF DESCRIPTION OF THE DRAWINGS mapping can aid in anti - aliasing as well as provide less 65 processor -intensive renderings . Many aspects of the disclosure can be better understood Migrating elements of texture streaming implementations with reference to the following drawings . While several from mip -based streaming (i . e. loading entire levels of US 10 ,388 ,058 B2 detail) to tile -based streaming and partial residency can be components detailed in FIG . 1 . These components include an effective mitigation to performance issues . Techniques graphics processor 120 and system processor 130 , as men using partial residency can allow content complexity to tioned above . Graphics processor 120 and system processor continue to grow without a corresponding increase in load 130 can each comprise one or more integrated elements , times or memory footprint. Tiled resources ( also known as 5 such as processor cores , cache memory , communication partially resident textures or PRTs ) can be improved so that interfaces, graphics cores, and north bridge elements, among these PRTs can be widely adopted while minimizing imple - other integrated elements not shown for clarity . Further mentation difficulty and performance overhead for GPUs. more , user system 110 can include various assembly ele These improvements include hardware residency map fea - ments , such as enclosure elements , thermal management tures and texture sample operations referred to herein as 10 elements , memory elements , storage elements , communica “ residency samples ,” among other improvements . tion interfaces, power system elements , among other ele A first enhancement includes a hardware residency map ments not shown for clarity . When graphics processor 120 feature comprising a low -resolution residency map that is and system processor 130 are installed in user system 110 , paired with a much larger PRT, and both are provided to these assembly elements provide system resources and con hardware at the same time. The residency map stores the 15 text for the operation of system processor 130 . Display 101 mipmap level of detail resident for each rectangular region can be included with user system 110 . of the texture . PRT textures are currently difficult to sample Enclosure elements can include structural support ele given sparse residency . Software - only residency map solu - ments , cases , chassis elements , or other elements that house tions typically perform two fetches of two different buffers and structurally support the further elements of user system in the shader , namely the residency map and the actual 20 110 . Thermal management elements can include heatsinks, texture map . The primary PRT texture sample is dependent fans, heat pipes , heat pumps , refrigeration elements, or other on the results of a residency map sample . These solutions are elements to manage and control temperature of user system effective , but require considerable implementation changes 110 . Memory elements can comprise random - access to shader and application code , especially to perform filter- memory (RAM ) , cache memory devices, or other volatile ing the residency map in order to mask unsightly transitions 25 memory elements employed by system processor 130 or between levels of detail, and may have undesirable perfor - graphics processor 120 . Storage elements comprise non mance characteristics. The improvements herein can stream - volatile memory elements , such as hard disk drives (HDDs ) , line the concept of a residency map and move the residency flash memory devices, solid state drives (SSDs ) , or other map into a hardware implementation . memory devices which store operating systems, applica A second enhancement includes an enhanced type of 30 tions , or other software or firmware for user system 110 . texture sample operation called a " residency sample . ” The Communication interfaces can include network interfaces , residency sample operates similarly to a traditional texture peripheral interfaces, storage interfaces, audio / video inter sampling , except the part of the texture sample that requests faces , or others which communicatively couple user system texture data from cache /memory and filters the texture data to external systems and devices. Graphics elements can to provide an output value is removed from the residency 35 include display interfaces , displays , touchscreens , touch sample operation . The purpose of the residency sample is to interfaces , user interfaces , among others. Power system generate memory addresses that reach the page table hard - elements typically include voltage regulator circuitry , con ware in the graphics processor but do not continue on to troller circuitry , power filtering elements , power condition become full memory requests . Instead , the residency of the ing elements , power conversion elements , power electronics PRT at those addresses is checked and missing pages are 40 elements , or other power handling and regulation elements . non - redundantly logged and requested to be filled by the OS Power system elements receive power from an external or a delegate. source , such as from batteries or an external power source , Turning now to an example systems and platforms that and converts /regulates the power to produce voltages and can provide at least the above enhancements , FIG . 1 is currents to operate the elements of user system 110 . provided . FIG . 1 illustrates graphics processing environment 45 User system 110 can communicate over one or more 100 in an implementation . Environment 100 includes user communication links comprising one or more network links . system 110 , graphics processor 120 , and system processor Example communication links can use metal, glass , optical, 130 . In operation , system processor 130 can boot into an air, space , or some other material as the transport media . operating system (OS ) to provide various operations of user Example communication links can use various communica system 110 including user applications , communication ser - 50 tion interfaces and protocols, such as Internet Protocol (IP ) , vices , storage services , gaming services , or other features of Ethernet , USB , Thunderbolt , Bluetooth , IEEE 802 . 11 WiFi, a computing system . Graphics processor 120 can provide or other communication signaling or communication for graphics processing and rendering services for system pro - mats , including combinations, improvements , or variations cessor 130 . Graphics processor 120 also provides enhanced thereof. Communication links can be direct links or may operations including operations involving cached tiles 121 55 include intermediate networks , systems, or devices, and can and residency map 122 , as will be discussed below . include a logical network link transported over multiple Although graphics processor 120 is shown as a separate physical links . element that communicates over at least link 150 with User system 110 can include software such as an operat processor 120 in FIG . 1 , it should be understood that other ing system , logs , databases, utilities, drivers, networking examples can provide graphics processor 120 within system 60 software , user applications , gaming applications , and other processor 130 , such as when system processor 130 inte software stored on a computer- readable medium . Software grates elements of graphics processor 120 . of user system 110 can comprise one or more platforms User system 110 comprises a computing system or com - which are hosted by a distributed computing system or puting assembly , such as a computer , server , tablet device , cloud -computing service . Software of user system 110 can laptop computer , smartphone , gaming system , entertainment 65 comprise logical interface elements , such as software system , storage system , or other computing system , includ - defined interfaces and Application Programming Interfaces ing combinations thereof. User system 110 includes several (APIs ) . Software of user system 110 can be used to generate US 10 , 388 , 058 B2 data to be rendered by graphics processor 120 and control memory 262 . Tile map 264 may optionally be implemented the operation of graphics processor 120 to render the graph - as a cache that is filled with contents from an area of texture ics for output to one or more display devices . memory 262 . Graphics processor 120 , system processor 130 , and sys - Residency map 241 comprises a buffer in memory that tem memory 131 can communicate over associated links 5 exists alongside tiled resources referred to as PRT ( partially 150 - 152 . Example links can use metal, glass , optical, air , resident textures ) . Residency map 241 indicates a combined space, or some other material as the transport media . The " A . B ” representation of a mipmap level of detail resident in links can use various communication protocols and com texture memory 262 (“ A ” ) along with a fractional value munication signaling , such as computer busses , including employed in a filtering clamp (“ B ” ) . The residency map is combinations or variations thereof. The links can be direct 10 links or may include intermediate networks , systems, or provided to graphics processor 220 along with the PRT in devices , and can include a logical network link transported the same " descriptor, " with the PRT being the primary data over multiple physical links. source and the residency map being the secondary “meta System memory 131 typically comprises any physical or data ” data source . The residency map is a relatively compact virtual allotment of random access memory (RAM ) or 15 data structure that represents one data sample per ( u , v ) dynamic RAM , among other components , including inter rectangular region of the PRT , and can be held in entirely facing elements . System memory 131 can be shared among hardware _ such as cache 221 . Each data sample in the system processor 130 and graphics processor 120 , or parti 1 regiresidency map can represent predetermined region of the tioned to be exclusive to either system processor 130 and PRT, such as a rectangular region of the PRT. graphics processor 120 . 20 Residency sampler 266 comprises logic that performs a FIG . 2 illustrates graphics processing system 200 in an sample from residency map 241 . Residency sampler 266 implementation . System 200 includes graphics processor generates memory addresses that reach the page table hard 220 which further includes hardware cache 221. Graphics ware in graphics processor 220 , but do not continue on to processor 220 can be an example of graphics processor 120 , become full memory requests . Instead , the residency of the although variations are possible . Graphics processor 220 can 25 PRT at those addresses is checked and recorded in residency provide graphics processing and rendering services for a log 267. Residency log 267 can be read by a designated system processor that indicates data and instructions over entity so that unused pages in texture memory 262 can be link 250 , such as system processor 130 in FIG . 1 . Cache 221 discarded and missing pages in texture memory 262 are comprises a memory or storage area incorporated into filled . graphics processor 220 for storing usage -based data and 30 FIG . 3 is provided to highlight example operations of components for graphics processor 220 . Cache 221 can store elements of FIGS . 1 - 2 . In FIG . 3 , shows several precom cached tiles 240 and residency map 241, among other items. puted texture renderings at different detail levels , namely In some examples , cache 221 comprises a hardware - based renderings 300 - 304 . Each rendering corresponds to texture cache memory in the hardware components that from graph data that covers the same quantity of texels ( i . e . 2048x2048 ics processor 220 , such as on -die cache memory . 35 texels ) , and each square corresponds to the same or similar As mentioned above , graphics processor 220 can include quantity of memory for texture data . Thus , each successive one or more stages or internal components that can process rendering covers the same number of texels , but in a content/ data into rendered images for display. These ele - successively lower level of detail . Further texture mapping ments can include those shown in FIG . 1 for graphics processes can use a selected level of detail to map to an processing unit (GPU ) elements 260 , although it should be 40 object depending on visibility , distance , or other scene understood that other configurations are possible . Elements driven factors . Each black square in renderings 300 - 304 260 include shader 261, texture memory 262 , texture unit indicates a portion that is currently ‘ resident' or available for 263, tile map 264 , residency map 241 , and residency sam - texture mapping . pler 266 . The detail levels of renderings 300 - 304 corresponds to a Texture memory 262 can include texture data that is 45 different 'mip ' level ( derived from the Latin phase multum provided by a content source for use by graphics processor in parvo ) . Renderings 300 - 304 comprise a set , with each 220 . Texture memory 262 can serve as a tile cache that stores member mapping to coordinates of a target object for which tiles for associated partially resident textures that are an associated texture is applied . Thus , renderings 300 - 304 employed in rendering . Tiles can be any discrete unit/ region can comprise a 'mipmap ' or ' pyramid ' that is pre - calculated of a texture map . Cached tiles 240 are included in FIG . 2 50 with progressively lower resolution representations of the representative of one or more resident portions of texture same texture . data within a cache portion of graphics processor 220 . Residency map 305 is also shown in FIG . 3 , and samples Shader 261 determines color information during the render - are made from residency map 305 to determine which mip ing process, and in some examples comprises pixel shading level is currently available . When the graphics processor features. Shader 261 can communicate with texture unit 263 55 samples from the PRT, it would first sample from the to determine colors /shading for regions of textures , which residency map . For example , for a given region of residency can be referred to as texels . Shader 261 can indicate level of map 305 , a sample indicates the lowest mip level resident in detail ( LOD ) thresholds to texture unit 263 , which is used the pre - computed renderings 300 - 305 . Further texture map for associated tile handling processes . The LOD thresholds ping processes can then use this minimum available mip can include a detail level needed for a particular tile , which 60 level in level- of -detail ( “ LOD ” ) considerations . The result can be based on various factors , including 3D - viewability of the residency map sample is a LOD value that is used to factors . LOD will be discussed in more detail below . clamp LOD calculations used for the subsequent sample of Tile map 264 specifies what tiles and detail levels are the PRT. This new LOD clamp would be applied in con stored in texture memory 262 , and can comprise one or more junction with existing LOD clamps specified by the resource tables or other data structures to track the information in 65 descriptor, sampler descriptor, and optional per -pixel input texture memory 262 . Values in tile map 264 indicate integers value from the shader. LOD bias calculations should be corresponding to levels of detail that are resident in texture applied before clamping . US 10 , 388 , 058 B2 Residency map 305 is a relatively small data structure that example 403 illustrates raw data bilinearly sampled as if it represents one data sample per ( u , v ) rectangular region of were a 2048x2048 texture with bilinear weights adjusted to the PRT . Only one two -dimensional plane of residency map sharpen filtering . is required for each two- dimensional array slice of a PRT, When filtering the residency map , a modified bilinear regardless of the mip dimensions of the PRT. The memory 5 filter can be used to sample LOD clamp values. The bilinear footprint of residency map 305 is kept small so that the weights for filtering adjacent residency map samples are adjustable to simulate the residency map being closer or residency map remains within cache memory and can be equivalent to the dimensions of the PRT. Specifically , the quickly prefetched into cache if necessary . Each residency filter weights can blend between adjacent residency map map data sample is one byte , encoded with a fixed - point 10 samples much closer to the (u , v ) space boundaries of the representation such as ( 4 -bits ). ( 4 - bits ) that accommodates rectangular regions in the PRT. Parameters could be pro encoding of a 0 - 15 fractional LOD value for LOD clamping . vided in the sampler or descriptor to bias the bilinear lerp A one byte fixed -point representation ( e .g . 4 . 4 above, among threshold by independent powers of 2 in each of U and V other representations ) can be stored in the residency map , directions. with a 4 -bit integer portion and a 4 -bit fractional portion 15 FIG . 5 illustrates a one - dimensional view of modified delimited by a binary radix point . bilinear filtering for residency maps, compared to standard A typical residency map is sized along the lines of 64 - 256 bilinear and raw texel value / data . Graph 500 illustrates three bytes per array slice of the PRT, which would be 8x8 or curves, namely raw sample value 510 , standard bilinear 16x16 entries, respectively . The size of the residency map filtering 511 , and modified bilinear filtering 512 . Element can also be made configurable, as a variable power -of - 2 20 510 can correspond to example 401 in FIG . 4 , element 511 division of the X - Y dimensions of the PRT. If configurable , can correspond to example 402 in Figure , and element 512 a developer would be responsible for ensuring the residency can correspond to example 403 in FIG . 4 , although varia map size remains suitable to reside in a hardware cache . tions are possible . Other encodings could be used for the residency map values, The filtering linear interpolation (e . g . lerp ) value can be such as a higher precision delta value encoded in the 25 modified so that the entire range of the blend between residency map which is added to a PRT- global base value . adjacent samples of differing value occurs within the sample The residency map can be sized proportional to a texture of lowest value . For example, if two adjacent residency map resource size using a scaling factor, such as having 2 " values samples contained values 0 and 3 , the blend from 0 to 1 to in a residency map for a particular texture resource size , 2 to 3 would occur entirely within the region represented by where “ n ” corresponds to a predetermined number. For 30 the sample . Once the sampling location crosses the bound example, a UxV sized texture resource ( e . g . 2048x2048 ) ary from 0 to 3 , the resulting value should be 3 . could produce n = U / 128 or n = U /256 ( or n = 2048 / 128 in the FIG . 6 and FIG . 7 illustrate example operations of texture 2048x2048 example ). mapping processes performed by graphics processing envi The layout of residency map samples can be linear ( such ronment 100 . FIG . 6 illustrates example process 610 that as an array of strided rows ) corresponding with geographic 35 includes a first example texture sampling pipeline not layout in ( u , v ) space . Linear layout is efficient for applica - involving a residency map . FIG . 7 illustrates example pro tion code to manipulate , and when the residency map is cess 710 that includes a second example texture sampling small enough , then linear layout has less impact on cache pipeline with residency map filtering . The operations of FIG . coherency . 6 and FIG . 7 can be performed by portions of a graphics Each data sample in the residency map represents a 40 processor or graphics processing unit (GPU ) , such as graph rectangular region of the PRT, as mentioned above. The ics processing elements , texture processing elements , tex value of that data sample represents the lowestmip level that ture units , or other elements . In some examples , operations is fully resident within that region , where 0 is the base of FIG . 6 and FIG . 7 are performed by portions of graphics ( largest ) mip level, and larger numbers represent succes processor 220 , such as texture unit 263, cache 221, and sively smaller mip levels . The fractional component is 45 residency sampler 266 , among other elements , including present in order to smoothly transition the value from one combinations thereof. whole number to the next. For example , if a fractional value In FIG . 6 , a typical texture sampling operation consists of is employed , then mip levels corresponding to the integer the following high -level steps , arranged as a sequential value and the next higher mip level, such that an A . B pipeline . In operation 611 , texture sampling inputs are fractional value would indicate that mip levels A and A + 1 50 received from a shader program , such as ( u , v ) texture are resident. A filtering process can be employed to deter - coordinates , texture coordinate gradients , texture descrip mine information between adjacent samples of residency tions ( format/ dimensions ), and sampler descriptions ( texture map 305 . filtering details ). In operation 612 , a texture addressing ( step Advantageously , due in part to residency map 305 being 1 ) is provided . Mip map (LOD ) fractional values are com small and granular, residency map 305 can be fully imple - 55 puted using gradients . In operation 613 , a further texture mented into hardware components of graphics processor addressing ( step 2 ) is provided . Texel sample addresses are 120 . This has the technical effects of faster , more efficient computed using texture coordinates and discrete LOD operation of graphics processors , the ability to hold value ( s ) . In operation 614 , a texture cache operation is enhanced residency maps in hardware , and reduced com provided . Data is retrieved that corresponds to texel sample puting resource required to properly render texture data for 60 addresses . In some examples, this data might be retrieved objects in rendered scenes . from memory (DRAM ) via one or more memory requests . FIGS. 4 and 5 are provided to illustrate some examples of In operation 615 , a texture filtering process is provided . the filtering processes with regards to residency map 305 . Using texel sample data , texture coordinates, fractional LOD FIG . 4 illustrates bilinear filtering weights adjusted to values , and sampler descriptions, a filtered result is com sharpen the resulting filtered image . Example 401 illustrates 65 puting and returned to the shader program . raw data for 4x4 texels , example 402 illustrates raw data In FIG . 7 , an example process 710 includes further bilinearly sampled as if it were a 2048x2048 texture , and enhanced residency maps and residency sampling opera US 10 , 388 , 058 B2 10 tions in a texture sampling pipeline. In FIG . 7 , a residency performed for the residency map . The LOD result from the sample operation has a different mode of operation for the residency map is used to complete operation 613 for sam texture sampling pipeline than in FIG . 6 . In FIG . 7 , the pling the PRT. If the LOD clamp value obtained from the residency sample operation is not configured to retrieve residency map was insufficient to avoid sampling from texture data . Texture data is not brought into or retrieved 5 nonresident regions of the PRT - i . e . if the residency map from the texture cache, and since no texture data is retrieved , values were incorrectly constructed then existing function no filtering is performed either. This can ensure that the ality to handle non - residency in texture filtering would be memory addresses reach the translation lookaside buffer used . A known value ( typically 0 ) would be used for ( TLB ) , which may have a reporting feature that registers all nonresident samples, and a non - residency failure code could requested memory addresses over a period of time. Resi - 10 be returned to the shader program if requested . dency sampling does not access or use the residency map Turning now to the operations of FIG . 8 , another example metadata feature described earlier . LOD clamping applied to process 810 includes further enhanced residency maps and the residency map is the traditional clamping specified by residency sampling operations in a texture sampling pipe the resource descriptor and /or sampler descriptor. line . Operations of FIG . 8 are related to elements of FIG . 2 , Turning now to the operations of FIG . 7 , operation 711 , 15 although it should be understood that other components and texture sampling inputs are received from a shader program , elements can be applied . such as ( u , v ) texture coordinates, texture coordinate gradi- A cache portion , such as cache 221 , establishes ( 811 ) , in ents , texture descriptions ( format /dimensions ) , and sampler a graphics processing unit , a residency map 265 having descriptions ( texture filtering details ) . These texture sam - values determined from memory residency properties of a pling inputs are then converted into a series of texture 20 texture resource . A residency sampler, such as residency sample locations . In operation 712 , a texture addressing sampler 266 , samples ( 812 ) from the residency map at a ( step 1 ) is provided . Mip map ( LOD ) fractional values ( e . g . specified location to determine a residency map sample for integer. fraction ) are computed using gradients . The texture the texture resource at the specified location , where the sample locations are converted to coarse residency map residency map sample indicates at least an initial level of addresses and the LOD for each is looked up and the results 25 detail ( N ) presently resident and a smoothing component or filtered . blending factor used in a blending process with a next level However , additional operations are provided in FIG . 7 as (N + 1 ) of detail. In this example , the residency map sample compared to FIG . 6 . First , operation 717 includes a resi comprises an integer portion and fractional portion . The dency map addressing operation that computes residency integer portion represents a lowest level of detail presently map addresses using texture coordinates . Operation 718 30 resident for the texture resource at the specified location . includes a residency map cache operation that retrieves data The fractional portion represents the smoothing component corresponding to residency map addresses . This data might or blending factor used in a blending process between the be retrieved from memory , such as from dynamic random initial level of detail and the next level of detail . The access memory (DRAM ) . Operation 719 includes a resi- blending process might be a transition over time between the dency map filtering operation that uses texture coordinates 35 initial level of detail and the next level of detail, or instead and residency map sample data to compute the filtered can be a detail blending between the between the initial level result . This filtered result is provided to operation 716 which of detail and the next level of detail for a single instance of clamps a LOD fractional value from operation 712 with a rendering. filtered residency map value received from operation 719 . A texture unit, such as texture unit 263 , establishes ( 813 ) Then , in operation 713 , a further texture addressing ( step 2 ) 40 cache residency of texture data in accordance with at least is provided . Texel sample addresses are computing using the initial level of detail corresponding to the integer portion texture coordinates and discrete LOD value ( s ) . Texture of the residency map sample and the next level of detail sampling inputs along with the filtered LOD are converted corresponding to the integer portion " plus one ” ( i . e . N + 1 ) . to linear texture data virtual memory addresses by the Both the N level and N + 1 level have concurrent cache " texture addressing ” hardware . 45 residency in this example . Based at least on the smoothing In operation 714 , a texture cache operation is provided . component of the residency map sample indicated by the Data is retrieved that corresponds to texel sample addresses . fractional portion , the texture unit performs (814 ) an inter In some examples , this data might be retrieved from memory polation process or other blending process between the (DRAM ) via one or more memory requests . Texture initial level of detail and the next level of detail to render at addresses are sent out to the texture cache , which consists of 50 least one texture region . In some examples this interpolation the following sub steps ( 1 ) virtual to physical address comprises a trilinear interpolation between level of detail N translation via the translation lookaside buffer ( TLB ) and the and N + 1 using the smoothing component or blending factor . GPU page table walker , ( 2 ) cache inspection to see if the The texture unit updates (815 ) the residency map at the data at the given address is already in the cache, and ( 3 ) specified location with an updated smoothing component memory requests to fetch data into the cache if it is not 55 indicated by a fractional value employed in a further inter present. polation process between further levels ofdetail . The integer In operation 715 , a texture filtering process is provided . portion can also be updated to transition to a further coarse Using texel sample data , texture coordinates , fractionalLOD level of detail . values , and sampler descriptions, a filtered result is com - A further description of a residency feedback loop is now puting and returned to the shader program . Texture data 60 discussed . This residency feedback loop can be imple retrieved from the cache can be filtered into a resulting mented by using both residency maps and residency sam output value by the “ texture data ” hardware . pling , such as described in FIGS . 7 and 8 , the following The residency map sampling includes portions of opera process can be implemented . First , an application creates a tion 712 above , namely the texture sample locations are PRT in memory , along with its residency map . At this time, converted to coarse residency map addresses and the LOD 65 all areas of the PRT are nonresident, and all residency map for each is looked up and the results filtered . Before texture values are set to the highest possible value (such as samples can be generated for the PRT, operation 712 is 15 . 9375 ) . The smallest mip level( s ) of the PRT are loaded US 10 , 388 , 058 B2 12 ( i. e . mip levels 8 and higher ) and made resident in memory , Now the process can apply a modified bilinear filter. Sepa and the residency map is updated to reflect the loaded mip rable filtering can be used , and the results of the u -axis and level( s ) . Now all of the residency map values are set to 8 . 0 . V - axis filters are combined . The process provides a tslope An object in the scene using the PRT is rendered . The PRT value which is 1 /transition distance per LOD difference , e .g . is first sampled using the residency map . The values of 8 . 0 5 8 to 64 subdivisions of a map region , which for hardware from the residency map are used to clamp the LOD , and the ease, can be made into a power of two . The tslope value can scene renders with mip level 8 . 0 . The PRT is sampled again be provided in a programmable register that controls the using the residency sampling feature. The “ ideal” LOD is resmap filtering function . Which two local resmap texel computed as 3 . 5 , and texture addresses are generated formip . boundaries are of interest (i . e . that border the transition levels 3 and 4 . The memory requests go only to the TLB / " zones ) depends in part on which resmap texel is currently page walker, and are logged by the graphics processor. After being sampled in , using Ufrac , Vfrac . There are 8 transition the frame completes , the application inspects the log gen - zones possible but only two are interesting in this example . erated by the TLB , and finds that mip levels 3 and 4 were In example hardware implementations, boundaries are deter requested for part of the PRT, while only mip level 8 is 16 mined unconditionally . The u - axis transition zone is defined currently resident for those regions . Texture streaming code as the range [ trans _ u0 , trans _ u1 ] . The v -axis transition zone in the application begins loading all mip levels for that is defined as the range [ trans _ v0 , trans_ v1 ]. region up to mip level 3 , starting with the smallest ( largest The process determines final tslopeU and tslope V for the index ) mip levels first. A portion of mip level 7 is loaded current resmap as : first , and the residency map is updated to contain values of 20 tslopeU = tslope > > logRegions 7 .0 in some areas. The application may choose to smoothly tslopeV = tslope > > logRegions V fade in mip level 7 over a few frames, writing successive The process sets a transition zone minimum and maximum fractional values into the residency map , such as 7. 75 , 7 .5 , per -boundary value with the following routine: 7 . 25 , and finally 7 . 0 . Execution repeats at step 3 . Over time, If (resLOD _ ul> resLOD _ ur) more portions of mip levels are loaded in and the loaded 25 Trans_ u0 = resMapHalfU ; Trans _ ul = resMap HalfU + state of the PRT gradually approaches the “ ideal” LOD ( resLOD _ ul - resLOD _ ur )/ tslopeU calculated by the residency sample . Then , a residency Else if (resLOD _ ul< resLOD _ ur ) sample operation is performed to record the tiles that would Trans_ u0 = resMapHalfU + (resLOD _ ul- resLOD _ ur ) have been required based on the original gradient based tslopeU ; Trans_ ul= resMapHalfU LOD . 30 To further describe an example residency map ( “ resmap ” ) 30 Else Trans u0 = Trans _ ul = resMapHalfU filtering process /algorithm , FIG . 9 is provided . The example Repeat similarly for resLOD _ ul vs. resLOD _ 11 to produce graph 900 in FIG . 9 corresponds to the following process , trans _ v0 and trans_ v1 relevant when sampling the residency with some values listed in key 901. In FIG . 9 , a system map within the left two samples . Repeat similarly for constant can be established as uvTotalBits which can be set 35 teresLOD _ 11 vs. resLOD _ Ir to produce trans_ u0 and trans_ ul to an example value of 19 to be sufficient for 8K max texture relevant when sampling the residency map within the bot dimension and 1 /256 texel precision . Another constant can be tom two samples. Repeat similarly for resLOD _ ur vs. established as logRegions which is set to a power of 2 of resLOD _ Ir to produce trans _ vo and trans _ v1 relevant when dimension of the current residency map . Thus, the size of the sampling the residency map within the right two samples . residency map corresponds to resmap [ 2logRegionsU1 40 Now the process determines a per -axis filtered and clamped [ 2logRegions ' ], and can be rectangular. Each pixel shader LOD (LUDu and LUDV ) which accounts for whether the thread is supplied u , v, and gradientLOD . A half - texel offset resmap (u ,v ) is inside or outside the transition zone : is applied because the corner is 0 , 0 and resmap u , v origin is If (Ufrac < Trans _ u0 ) at (0 . 5 , 0 . 5 ) in the upper left corner texel. After the offset is LODu = (Vfrac < 0 . 5 ) ? resLOD _ ul: resLOD _ 11 applied , the “ 0 . 5 " value is on the boundary between resmap 45 Else if (Ufrac < Trans _ ul) texels and is dependent on the map resolution . Thus, the LODu = tslope( u - TransOu ) + (Vfrac < 0 . 5 ) ? resLOD _ ul : following values can be established : resLOD _ 11 resMap HalfU = 0 . 5 > > logRegionsU Else LODu = ( Vfrac < 0 . 5 ) ? resLOD _ ur : resLOD _ lr resMap HalfV = 0 . 5 > > logRegions V Repeat for LUDV, then combine to produce the final LOD : (umap ,vmap )= (u , v ) - (resMap HalfU , resMap HalfV ) 50 fracbitsU = uvTotalBits - logRegions resLOD = max ( LODu , LODV ) fracbits V = uvTotalBits - logRegions V Final LOD = max ( gradientLOD , resLOD ) Uint= umap > > ( fracbitsU ) Sample( u , v , LOD ) Vint = vmap > > ( fracbits V ) Now the process can perform a residency sample operation . Ufrac = umap & ( 2 fracbitsU - 1 ) 55 Certain inventive aspects may be appreciated from the now equal to the distance from left resmap pixel center foregoing disclosure , of which the following are various to right resmap pixel examples . Vfrac = vmap & ( 2 ^ fracbits V - 1 ) now equal to the distance from top resmap pixel to Example 1 bottom resmap pixel 60 Now the process can look up in the residency map , and the A method of handling tiled resources in graphics process options of clamp and wrap can be applied to all (u ,v ) below ing environments , the method comprising establishing , in a to match actual texture sampler settings . graphics processing unit, a residency map having values resLOD _ ul= resmap [uint ][ vint] determined from memory residency properties of a texture resLOD _ ur = resmap [ uint + 1 ] [vint ] 65 resource , and sampling from the residency map at a specified resLOD _ 11 = resmap [uint ] [ vint + 1 ] location to determine a residency map sample for the texture resLOD _ lr = resmap [uint + 1 ][ vint+ 1 ] resource at the specified location , where the residency map US 10 , 388 , 058 B2 13 14 sample indicates at least an initial level of detail presently texture resource , and where each location in the residency resident and a fractional portion used in a blending process map corresponds to a 1 - byte fixed point value encoding an integer portion indicating the initial level of detail and the with a next level of detail. fractional portion . Example 2 Example 10 The method of Example 1, where the residency map A graphics processing unit, comprising a cache portion sample comprises an integer portion and fractional portion , configured to hold a residency map with values determined where the integer portion represents a lowest level of detail from memory residency properties of a texture resource , and presently resident for the texture resource at the specified 10 a residency sampler configured to sample from a specified location , and where the fractional portion represents a blend location in the residency map to determine a residency map ing factor for transitioning with the blending process to the sample for the texture resource at the specified location , next level of detail from the initial level of detail . where the residency map sample indicates at least an initial level of detail presently resident and a fractional portion Example 3 used in a blending process with a next level of detail. The method of Examples 1 - 2 , further comprising estab Example 11 lishing concurrent cache residency of texture data in accor dance with at least the initial level of detail corresponding to 20 The graphics processing unit of Example 10, where the the integer portion of the residency map sample and the next residency map sample comprises an integer portion and level of detail corresponding to an additional level of detail fractional portion , where the integer portion represents a beyond the initial level of detail . lowest level of detail presently resident for the texture resource at the specified location , and where the fractional Example 4 portion represents a blending factor for transitioning with the blending process to the next level of detail from the The method of Examples 1 - 3 , further comprising based at initial level of detail. least on the blending factor indicated by the residency map sample , performing an interpolation process between the Example 12 initial level of detail and the next level of detail to render at least one texture region . 30 The graphics processing unit of Examples 10 - 11, further comprising a texture unit configured to establish concurrent Example 5 cache residency of texture data in accordance with at least the initial level of detail corresponding to the integer portion The method of Examples 1 - 4 , further comprising updat of the residency map sample and the next level of detail ing the residency map at the specified location with an 3 corresponding to an additional level of detail beyond the updated fractional portion indicating a new blending factor initial level of detail. employed in a further interpolation process between the initial level of detail and the next level of detail . Example 13 Example 6 40 The graphics processing unit of Examples 10 - 12 , com prising based at least on the blending factor indicated by the The method of Examples 1- 5 , further comprising sam - residency map sample , the texture unit further configured to pling and filtering at least four nearest samples to the perform an interpolation process between the initial level of residency map sample to produce a current level of detail in detail and the next level of detail to render at least one an associated texture resource . 45 texture region . Example 7 Example 14 The method of Examples 1- 6 , where the filtering com The graphics processing unit of Examples 10 - 13 , com prises filtering among the four nearest samples according to 50 prising the texture unit further configured to update the a dimensional characteristic of the texture resource to pro - residency map at the specified location with an updated duce the current level of detail , the filtering including the fractional portion indicating a new blending factor employed initial level of detail clamped based at least upon the in a further interpolation process between the initial level of fractional portion indicated in the residency map sample . detail and the next level of detail . 55 Example 8 Example 15 The method of Examples 1 - 7 , further comprising receiv The graphics processing unit of Examples 10 - 14 , com ing , into a hardware cache of the graphics processing unit , prising the texture unit further configured to sample and a descriptor comprising a data portion defining the texture 60 filter at least four nearest samples to the residency map resource and a metadata portion defining the residency map sample to produce a current level of detail in an associated with values corresponding to the texture resource . texture resource . Example 9 Example 16 65 The method of Examples 1 - 8 , where the residency map The graphics processing unit of Examples 10 - 15 , where comprises an array sized proportional to a dimension of the the filtering comprises filtering among the four nearest US 10 , 388 , 058 B2 15 16 samples according to a dimensional characteristic of the ciate that a method could alternatively be represented as a texture resource to produce the current level of detail , the series of interrelated states or events , such as in a state filtering including the initial level of detail clamped based at diagram . Moreover , not all acts illustrated in a methodology least upon the fractional portion indicated in the residency may be required for a novel implementation . map sample . The descriptions and figures included herein depict spe cific implementations to teach those skilled in the art how to Example 17 make and use the best option . For the purpose of teaching inventive principles, some conventional aspects have been The graphics processing unit of Examples 10 , comprising simplified or omitted . Those skilled in the art will appreciate the cache portion further configured to receive a descriptor 10 variations from these implementations that fall within the comprising a data portion defining the texture resource and scope of the disclosure. Those skilled in the art will also a metadata portion defining the residency map with values appreciate that the features described above can be com corresponding to the texture resource . bined in various ways to form multiple implementations . As a result, the invention is not limited to the specific imple Example 18 15 mentations described above, but only by the claims and their equivalents . The graphics processing unit of Examples 10 , where the What is claimed is : residency map comprises an array sized proportional to a 1 . A method of handling tiled resources in graphics dimension of the texture resource , and where each location processing environments, the method comprising : in the residency map corresponds to a 1 -byte fixed point 20 establishing , in a graphics processing unit , a residency value encoding an integer portion indicating the initial level map having values determined from memory residency of detail and the fractional portion . properties of a texture resource ; sampling from the residency map at a specified location to Example 19 determine a residency map sample for the texture 25 resource at the specified location , wherein the resi A method of handling partially resident textures in a dency map sample indicates at least an initial level of graphics processing unit (GPU ) , the method comprising detail presently resident and a fractional portion used in establishing, in a GPU , a hardware residency map with a blending process with a next level of detail ; and values indicating residency properties of a texture resource , updating the residency map at the specified location with and sampling from the hardware residency map at specified 30 updated fractional portions indicating subsequent locations to determine corresponding residency map blending factors used to achieve one or more transition samples each comprising an integer portion and fractional levels between the initial level of detail and the next portion , where the integer portion indicates an associated level of detail . lowest level of detail presently resident for the texture 2 . The method of claim 1 , wherein the residency map resource , and where the fractional portion represents an 35 sample comprises an integer portion and fractional portion , associated smoothing component for transitioning in a wherein the integer portion represents a lowest level of blending process with a next level of detail concurrently detail presently resident for the texture resource at the resident for the texture resource . specified location , and wherein the fractional portion repre sents a blending factor for transitioning with the blending Example 20 40 process to the next level of detail from the initial level of detail . The method of Example 19 , further comprising for at least 3 . The method of claim 2 , further comprising : the specified locations of the hardware residency map , establishing concurrent cache residency of texture data in establishing residency of texture data in accordance with accordance with at least the initial level of detail lowest levels of detail corresponding to the integer portions 45 corresponding to the integer portion of the residency of the residency map samples and next levels of details map sample and the next level of detail corresponding beyond the integer portions . Based at least on the smoothing to an additional level of detail beyond the initial level component of the residency map samples , the method of detail. includes performing interpolation processes between the 4 . The method of claim 3 , further comprising : lowest levels of detail and the next levels of detail to render 50 based at least on the blending factor indicated by the at least one texture region . The method also includes updat residency map sample , performing an interpolation ing the residency map at the specified locations with at least process to achieve at least one among the one or more updated smoothing components indicated by the fractional transition levels between the initial level of detail and portions to be employed in further interpolation processes. the next level of detail to render at least one texture The functional block diagrams, operational scenarios and 55 region . sequences , and flow diagrams provided in the Figures are 5 . The method of claim 4 , further comprising : representative of exemplary systems, environments , and updating the residency map at the specified location with methodologies for performing novel aspects of the disclo the updated fractional portions to transition to the next sure . While , for purposes of simplicity of explanation , level of detail over time by employing repeated methods included herein may be in the form of a functional 60 smoothing processes indicated by the fractional por diagram , operational scenario or sequence , or flow diagram , tions . and may be described as a series of acts , it is to be 6 . The method of claim 1 , further comprising : understood and appreciated that the methods are not limited sampling and filtering at least four nearest samples to the by the order of acts , as some acts may, in accordance residency map sample to produce a current level of therewith , occur in a different order and / or concurrently with 65 detail in an associated texture resource . other acts from that shown and described herein . For 7 . The method of claim 6 , wherein the filtering comprises example , those skilled in the art will understand and appre - filtering among the four nearest samples according to a US 10 , 388 , 058 B2 17 18 dimensional characteristic of the texture resource to produce 15 . The graphics processing unit of claim 10 , comprising: the current level of detail , the filtering including the initial the texture unit further configured to sample and filter at level of detail clamped based at least upon the fractional least four nearest samples to the residency map sample portion indicated in the residency map sample . to produce a current level of detail in an associated 8 . The method of claim 1 , further comprising : texture resource . receiving , into a hardware cache of the graphics process 16 . The graphics processing unit of claim 15 , wherein the ing unit , a descriptor comprising a data portion defining filtering comprises filtering among the four nearest samples the texture resource and a metadata portion defining the according to a dimensional characteristic of the texture residency map with values corresponding to the texture resource to produce the current level of detail, the filtering resource . 9 . The method of claim 1 , wherein the residency map including the initial level of detail clamped based at least comprises an array sized proportional to a dimension of the upon the fractional portion indicated in the residency map texture resource, and wherein each location in the residency sample . map corresponds to a 1 - byte fixed point value encoding an 17 . The graphics processing unit of claim 10 , comprising : integer portion indicating the initial level of detail and the 15 the cache portion further configured to receive a descrip fractional portion . tor comprising a data portion defining the texture 10 . A graphics processing unit , comprising : resource and a metadata portion defining the residency a cache portion configured to hold a residency map with map with values corresponding to the texture resource . values determined from memory residency properties 18 . The graphics processing unit of claim 10 , wherein the 2020 residency map comprises an array sized proportional to a of a texture resource ; dimension of the texture resource , and wherein each location a residency sampler configured to sample from a specified in the residency map corresponds to a 1 - byte fixed point location in the residency map to determine a residency value encoding an integer portion indicating the initial level map sample for the texture resource at the specified of detail and the fractional portion . location , wherein the residency map sample indicates at 19 . A method of handling partially resident textures in a leastfractional an initial portion level used of detailin a blendingpresently processresident with and a 25 graphics processing unit (GPU ) , the method comprising : next level of detail ; and establishing , in a GPU , a hardware residency map with the residency sampler configured to update the residency values indicating residency properties of a texture map at the specified location with updated fractional resource ; portions indicating subsequent blending factors used to 30 sampling from the hardware residency map at specified achieve one or more transition levels between the initial locations to determine corresponding residency map level of detail and the next level of detail . samples each comprising an integer portion and frac 11 . The graphics processing unit of claim 10 , wherein the tional portion , wherein the integer portion indicates an residency map sample comprises an integer portion and associated lowest level of detail presently resident for fractional portion , wherein the integer portion represents a 35 the texture resource , and wherein the fractional portion lowest level of detail presently resident for the texture represents an associated smoothing component for resource at the specified location , and wherein the fractional transitioning in a blending process with a next level of portion represents a blending factor for transitioning with detail concurrently resident for the texture resource ; the blending process to the next level of detail from the and initial level of detail . - 40 updating the residency map at the specified locations with 12 . The graphics processing unit of claim 11 , further updated fractional portions indicating subsequent comprising : blending factors used to achieve one or more transition a texture unit configured to establish concurrent cache levels between the initial level of detail and the next residency of texture data in accordance with at least the level of detail . initial level of detail corresponding to the integer 45 20 . The method of claim 19 , further comprising: portion of the residency map sample and the next level for at least the specified locations of the hardware resi of detail corresponding to an additional level of detail dency map , establishing residency of texture data in beyond the initial level of detail. accordance with lowest levels of detail corresponding 13 . The graphics processing unit of claim 12 , comprising : to the integer portions of the residency map samples based at least on the blending factor indicated by the 50 and next levels of details beyond the integer portions ; residency map sample , the texture unit further config based at least on the smoothing component of the resi ured to perform an interpolation process to achieve at dency map samples, performing interpolation pro least one among the one or more transition levels cesses to achieve at least one among the one or more between the initial level of detail and the next level of transition levels between the lowest levels of detail and detail to render at least one texture region . 55 the next levels of detail to render at least one texture 14 . The graphics processing unit of claim 13, comprising : region ; and the texture unit further configured to update the residency updating the residency map at the specified locations with map at the specified location with the updated frac at least updated smoothing components indicated by tional portions to transition to the next level of detail the fractional portions to be employed in further inter over time by employing repeated smoothing processes 60 polation processes . indicated by the fractional portions. * * * *