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( 12 ) United States Patent ( 10) Patent No US010388058B2 ( 12 ) United States Patent ( 10 ) Patent No. : US 10 , 388, 058 B2 Goossen et al. (45 ) Date of Patent: Aug. 20 , 2019 ( 54 ) TEXTURE RESIDENCY HARDWARE ( 56 ) References Cited ENHANCEMENTS FOR GRAPHICS PROCESSORS U . S . PATENT DOCUMENTS 6 ,707 ,458 B1 * 3 /2004 Leather .. .. .. G06T 15 /04 (71 ) Applicant: Microsoft Technology Licensing , LLC , 345 / 582 Redmond , WA (US ) 7 , 193 ,627 B1 * 3 / 2007 Donovan . .. .. G06T 15 /04 345 / 428 (72 ) Inventors : James Andrew Goossen , Sammamish , 8 ,587 , 602 B2 11/ 2013 Grossman et al . WA (US ) ; Matthew William Lee , 2008 /0106552 AL 5 /2008 Everitt Sammamish , WA (US ) ; Mark S . 2011 /0157205 Al 6 / 2011 Tao et al . 2011/ 0157206 A1 * 6 / 2011 Duluk , Jr. .. GO6T 15 /04 Grossman , Palo Alto , CA (US ) 345 / 582 2011/ 0157207 AL 6 / 2011 Hall et al. ( 73 ) Assignee : Microsoft Technology Licensing , LLC , 2015 /0089146 AL 3 /2015 Gotwalt et al . Redmond , WA (US ) 2015 /0379730 A1 12 / 2015 Tsakok et al. ( * ) Notice : Subject to any disclaimer , the term of this patent is extended or adjusted under 35 OTHER PUBLICATIONS U . S . C . 154 ( b ) by 108 days . Harrison , et al. , “ AES Encryption Implementation and Analysis on Commodity Graphics Processing Units ” , In proceedings of the ( 21) Appl . No. : 15 /608 ,003 international Workshop on Cryptographic Hardware and Embedded ( 22 ) Filed : May 30 , 2017 Systems, Published on : Sep . 10 , 2007, 10 pages . (65 ) Prior Publication Data * cited by examiner US 2018 / 0232940 A1 Aug. 16 , 2018 Primary Examiner — Edward Martello Related U . S . Application Data (57 ) ABSTRACT (60 ) Provisional application No . 62 /459 ,726 , filed on Feb . Systems, methods, apparatuses , and software for graphics 16 , 2017 . processing systems in computing environments are provided herein . In one example , a method of handling tiled resources (51 ) Int. Ci. in graphics processing environments is presented . The G06T 15 /04 ( 2011 .01 ) method includes establishing , in a graphics processing unit , G06T 15 /00 ( 2011 .01 ) a residency map having values determined from memory G06T 15 /50 ( 2011 .01 ) residency properties of a texture resource, and sampling (52 ) U . S . Cl. from the residency map at a specified location to determine CPC . .. .. G06T 15 /04 (2013 . 01 ) ; G06T 15 / 005 a residency map sample for the texture resource at the ( 2013 .01 ) ; GO6T 15 /503 (2013 .01 ) ; G06T specified location , where the residency map sample indi 2200 /28 ( 2013. 01 ) ; G06T 2210 / 36 ( 2013 .01 ) cates at least an initial level of detail presently resident and ( 58 ) Field of Classification Search a smoothing component to reach a next level of detail . None See application file for complete search history . 20 Claims, 9 Drawing Sheets WIDTH = 2048 TEXELS RU 303 304 302 MIP LEVEL 4 MIP LEVEL 3 MP LEVEL 2 HEIGHT=2048TEXELS MIP LEVEL 1 305 RESIDENT MEMORY NON -RESIDENT MEMORY 10 : 30 20 8 .0 MIP LEVEL O 2010 2010 2048 x 2048 partially resident texture SA 4 .0 : 4 . 0 4 .0 4 . 0 with associated residency map 0 4 .0 4 .0 4 .0 4 .0 30 30 30 30 4 . 0 4 .0 4 . 0 4 .0 3. 0 3 .0 3. 0 3 .0 4 .0 4 .0 4 .0 4 .0 8x8 RESIDENCY MAP U . S . Patent Aug . 20, 2019 Sheet 1 of 9 US 10 , 388 ,058 B2 CACHEDTILES121 RESIDENCYMAP122 PROCESSOR130 PROCESSOR120 150 SYSTEM GRAPHICS SYSTEM MEMORY131 152 PROCESSOR130 GRAPHICS120 THERMALMGMTMEMORY 131 FIGURE1 ASSEMBLYELEMENTS ENCLOSURE :STORAGE COMMIF POWER USERSYSTEM 110 101 100 U . S . Patent Aug . 20, 2019 Sheet 2 of 9 US 10 , 388 ,058 B2 . 266 . MAP265 . SAMPLER . RESDENCY RESIDENCY . 263 264 262 TILEMAP . UNIT . TEXTURE TEXTURE . MEMORY . 260 . 261 . SHADER RESIDENCY LOG267 CACHEDTILES240 RESIDENCYMAP241 FIGURE2 CACHE221 GPU 220 200 250 U . S . Patent Aug. 20 , 2019 Sheet 3 of 9 US 10 , 388 ,058 B2 3,0 3,0 3,0 $3.00 304MPLEVELA MIPLEVEL4 3,0 3,0 3.0 3,0 4.0 04.04 3.0 3,0 4.0 304.0 0 3.0 3,0 4.0 3,04. MIPLEVEL3 30 wwwwwwwwwwwww 8x8RESIDENCYMAP 0 ko200 100.01 3.0 10 10100 0 30303 3.0 min 3.0 o MIPLEVEL2 2 305 302 tuturo MIPLEVEL1 NON-RESIDENTMEMORY RESIDENTMEMORY 2048xpartiallyresidenttexture withassociatedresidencymap FIGURE3 301 tututututututet tttttttttttttt DE. WIDTH=2048TEXELS AAAAAAAAAAAA AAN TAMAAN . MIPLEVELO SWAX TEXELS 2048 = HEIGHT atent Aug . 20 , 2019 Sheet 4 of 9 US 10 , 388 ,058 B2 WWW RAWDATABILINEARLYSAMPLEDAS IFITWEREA2048xTEXTURE, WITHBILINEARWEIGHTSADJUSTED TOSHARPENFILTERING 403 Bilinearfilteringweightsadjustedtosharpenthe resultingfilteredimage SAMPLEDASIFITWEREA FIGURE4 RAWDATABILINEARLY 2048xTEXTURE . RAWDATA(4X4TEXELS) . 0. 401 U . S . Patent Aug . 20, 2019 Sheet 5 of 9 US 10 , 388 ,058 B2 31-STANDARDBILINEARFILTERING -MODIFIEDBILINEARFILTERING .RAWSAMPLEVALUE 510 512 'Ucoordinate FIGURE5 51001 One-dimensionalviewofmodifiedbilinearfilteringforresidencymaps, comparedtostandardbilinearandrawtexeldata 512 level mip U . S . Patent Aug . 20, 2019 Sheet 6 of 9 US 10 , 388 ,058 B2 DRAM FIGURE6 610 612 611 -613 mm614 -615 w COMPUTEMIPMAP(LOD) VALUE(S) FRACTIONALLODVALUE,AND INPUTSFROMSHADERPROGRAM FRACTIONALVALUEUSING GRADIENTS COMPUTETEXELSAMPLE ADDRESSESUSINGTEXTURE COORDINATESANDDISCRETELOD RETRIEVEDATACORRESPONDINGTO TEXELSAMPLEADDRESSES,OR SUBMITMEMORYREQUESTSTO MEMORYTOFETCHTHEDATA USINGTEXELSAMPLEDATA, TEXTURECOORDINATES, SAMPLERDESCRIPTION,COMPUTE THEFILTEREDRESULT RETURNRESULTTOSHADERPROGRAM TEXTUREADDRESSING STEP1 TEXTURE ADDRESSING STEP2 TEXTURE CACHE TEXTURE FILTERING U . S . Patent Aug . 20, 2019 Sheet 7 of 9 US 10 , 388 ,058 B2 RESIDENCY MAP ADDRESSING RESIDENCY MAPCACHE RESIDENCY MAPFILTERING 717- 718 719 . FIGURE7 . CORRESPONDINGTO . COMPUTERESIDENCYMAP ADDRESSESUSINGTEXTURE RETRIEVEDATA . USINGTEXTURE COORDINATESAND RESIDENCYMAPSAMPLE DATA,COMPUTETHEFILTEREDRESULT DRAM RESIDENCYMAPADDRESSES . COORDINATES . 212 713 -716 714 715 naman - PROGRAM711 COMPUTEMIPMAP(LOD) DISCRETELODVALUE(S) TEXELSAMPLEADDRESSES,ORSUBMIT MEMORYREQUESTSTO COORDINATES,FRACTIONALLODVALUE RETURNRESULTTO INPUTSFROMSHADER "INTEGER.FRACTIONVALUEUSING GRADIENTS CLAMPLODVALUEWITHFILTERED RESIDENCYMAPVALUE COMPUTETEXELSAMPLEADDRESSES USINGTEXTURECOORDINATESAND RETRIEVEDATACORRESPONDINGTO FETCHTHEDATA USINGTEXELSAMPLEDATA,TEXTURE ANDSAMPLERDESCRIPTION,COMPUTETHEFILTEREDRESULT SHADERPROGRAM TEXTURE ADDRESSING STEP1 "FRACTIONAL CLAMP TEXTURE ADDRESSING STEP2 TEXTURE CACHE TEXTURE FILTERING U . S . Patent Aug . 20, 2019 Sheet 8 of 9 US 10 , 388 ,058 B2 ~811 812 813 814 ·815 - SAMPLEFROMTHERESIDENCYMAPATASPECIFIEDLOCATIONTODETERMINE ESTABLISHCONCURRENTCACHERESIDENCYOFTEXTUREDATAINACCORDANCE PERFORMANINTERPOLATIONPROCESSBETWEENTHEINITIALLEVELOFDETAIL INTEGERPORTIONANDFRACTIONALTOBEEMPLOYEDINAFURTHER ESTABLISHARESIDENCYMAPHAVINGVALUESDETERMINEDFROMMEMORY RESIDENCYPROPERTIESOFATEXTURERESOURCE RESIDENCYMAPSAMPLEFORTHETEXTURERESOURCE WITHTHEINITIALLEVELOFDETAILCORRESPONDINGTOANINTEGERPORTION THERESIDENCYMAPSAMPLEANDANADDITIONALLEVELOFDETAILBEYOND INITIALLEVELOFDETAIL ANDTHENEXTLEVELOFDETAILTORENDERATLEASTONETEXTUREREGION BASEDATLEASTONABLENDFACTORDERIVEDFROMFRACTIONAL PORTIONOFTHERESIDENCYMAPSAMPLE UPDATETHERESIDENCYMAPATSPECIFIEDLOCATIONWITHANUPDATED BLENDINGPROCESS FIGURE8 810 U . S . Patent Aug . 20, 2019 Sheet 9 of 9 US 10 , 388 ,058 B2 TeTransVOforvresmapHalfV(inactive) Tf-TransU0forusresmapHalfu(inactive) Ta=TransVO(active)Tb-TransUo(active) Tc=TransV1(active) Td=TransU1(active) TC resmap(Uine+1,Vint)=2 11Vine1)=+Uing,Tresmap( + ---- u,v FIGURE9 Tf1 * TbTd RESIDENCYMAPFILTERING WY resmap(Uirt,Vint)=1i 31)=UintVin+resmap,( resmapHalfv] + resmapHalfU 900 US 10 , 388 , 058 B2 TEXTURE RESIDENCY HARDWARE implementations are described in connection with these ENHANCEMENTS FOR GRAPHICS drawings, the disclosure is not limited to the implementa PROCESSORS tions disclosed herein . On the contrary , the intent is to cover all alternatives, modifications , and equivalents . RELATED APPLICATIONS 5 FIG . 1 illustrates a graphics processing environment in an implementation . This application hereby claims the benefit of and priority to U . S . Provisional Patent Application 62 / 459 ,726 , titled FIG . 2 illustrates a graphics processor in an implementa " TEXTURE RESIDENCY HARDWARE ENHANCE tion . MENTS FOR GRAPHICS PROCESSORS, ” filed Feb . 16 , FIG . 3 illustrates an example texture information and 2017 , which is hereby incorporated by reference in its 10 residency map in an implementation . entirety . FIG . 4 illustrates an example filtering in an implementa tion . BACKGROUND FIG . 5 illustrates an example filtering in an implementa tion . Computing systems, such as personal computers , portable 15 FIG . 6 illustrates a method of operating a graphics pro computing platforms, gaming systems, and servers , can cessing environment in an implementation . include graphics processors along with main /central proces FIG . 7 illustrates a method of operating a graphics pro sors . These graphics processors , sometimes referred to as cessing environment in an implementation . graphics processing units (GPUs ) , can be integrated into the FIG . 8 illustrates a method of operating a graphics pro central processors or discretely provided on separate add -in 20 cessing environment in an implementation . cards, among other configurations . User applications, oper - FIG . 9 illustrates an example residency map filtering in an ating systems, video games , or other software elements can implementation . interface with GPUs using various application programming interfaces (APIs ) that allow for standardized software / logi DETAILED DESCRIPTION cal interfaces between the software elements and various 25 GPU hardware elements . Graphics processing
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