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The Requirements of I/O OS Basics: I/O in a Picture

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The Requirements of I/O OS Basics: I/O in a Picture The Requirements of I/O CS162 • So far in this course: Operating Systems and – We have learned how to manage CPU and memory Systems Programming Lecture 16 • What about I/O? – Without I/O, computers are useless (disembodied brains?) General I/O – But… thousands of devices, each slightly different » How can we standardize the interfaces to these devices? October 18th, 2017 – Devices unreliable: media failures and transmission errors Neeraja J. Yadwadkar » How can we make them reliable??? http://cs162.eecs.Berkeley.edu – Devices unpredictable and/or slow » How can we manage them if we don’t know what they will do or how they will perform? 10/18/17 CS162 © UCB Spring 2017 Lec 16.2 OS Basics: I/O In a Picture Threads Read / Address Spaces Windows Write wires Processes Files Sockets Processor OS Hardware Virtualization Core I/O Software Controllers Hardware ISA Memory interrupts Secondary Read / DMA transfer Write Main Secondary Storage Processor Protection Core Memory Storage (Disk) Boundary (DRAM) (SSD) OS Ctrlr Networks storage • I/O devices you recognize are supported by I/O Controllers • Processors accesses them by reading and writing IO registers as if they were memory Displays – Write commands and arguments, read status and results Inputs 10/18/17 CS162 © UCB Spring 2017 Lec 16.3 10/18/17 CS162 © UCB Spring 2017 Lec 16.4 Operational Parameters for I/O Kernel Device Structure • Data granularity: Byte vs. Block The System Call Interface – Some devices provide single byte at a time (e.g., keyboard) – Others provide whole blocks (e.g., disks, networks, etc.) Process Memory Device Filesystems Networking Management Management Control • Access pattern: Sequential vs. Random Concurrency, Files and dirs: Virtual TTYs and Connectivity – Some devices must be accessed sequentially (e.g., tape) multitasking memory the VFS device access File System – Others can be accessed “randomly” (e.g., disk, cd, etc.) Types Network » Fixed overhead to start transfers Architecture Subsystem Memory Device Dependent – Some devices require continual monitoring Manager Control Code Block IF drivers – Others generate interrupts when they need service Devices • Transfer Mechanism: Programmed IO and DMA 10/18/17 CS162 © UCB Spring 2017 Lec 16.5 10/18/17 CS162 © UCB Spring 2017 Lec 16.6 The Goal of the I/O Subsystem Want Standard Interfaces to Devices • Block Devices: e.g. disk drives, tape drives, DVD-ROM • Provide Uniform Interfaces, Despite Wide Range of Different – Access blocks of data Devices – Commands include open(), read(), write(), seek() – This code works on many different devices: – Raw I/O or file-system access FILE fd = fopen("/dev/something", "rw"); – Memory-mapped file access possible for (int i = 0; i < 10; i++) { • Character Devices: e.g. keyboards, mice, serial ports, some USB fprintf(fd, "Count %d\n", i); devices } – Single characters at a time close(fd); – Commands include get(), put() – Why? Because code that controls devices (“device driver”) – Libraries layered on top allow line editing implements standard interface • Network Devices: e.g. Ethernet, Wireless, Bluetooth • We will try to get a flavor for what is involved in actually – Different enough from block/character to have own interface controlling devices in rest of lecture – Unix and Windows include socket interface – Can only scratch surface! » Separates network protocol from network operation » Includes select() functionality – Usage: pipes, FIFOs, streams, queues, mailboxes 10/18/17 CS162 © UCB Spring 2017 Lec 16.7 10/18/17 CS162 © UCB Spring 2017 Lec 16.8 How Does User Deal with Timing? Chip-scale Features of 2015 x86 (Sky Lake) • Blocking Interface: “Wait” • Significant pieces: – When request data (e.g. read() system call), put process to sleep until – Four OOO cores with deeper buffers data is ready » New Intel MPX (Memory Protection Extensions) – When write data (e.g. write() system call), put process to sleep until » New Intel SGX (Software Guard Extensions) device is ready for data » Issue up to 6 µ-ops/cycle • Non-blocking Interface: “Don’t Wait” – Integrated GPU, System Agent (Mem, Fast I/O) – Large shared L3 cache with on-chip ring bus – Returns quickly from read or write request with count of bytes successfully transferred » 2 MB/core instead of 1.5 MB/core » High-BW access to L3 Cache – Read may return nothing, write may write nothing • Integrated I/O • Asynchronous Interface: “Tell Me Later” – Integrated memory controller (IMC) – When request data, take pointer to user’s buffer, return immediately; » Two independent channels of DDR3L/DDR4 DRAM later kernel fills buffer and notifies user – High-speed PCI-Express (for Graphics cards) – When send data, take pointer to user’s buffer, return immediately; later kernel takes data and notifies user – Direct Media Interface (DMI) Connection to PCH (Platform Control Hub) 10/18/17 CS162 © UCB Spring 2017 Lec 16.9 10/18/17 CS162 © UCB Spring 2017 Lec 16.10 Sky Lake I/O: PCH Modern I/O Systems • Platform Controller Hub – Connected to processor with proprietary bus » Direct Media Interface • Types of I/O on PCH: – USB, Ethernet – Thunderbolt 3 network – Audio, BIOS support – More PCI Express (lower speed than on Processor) – SATA (for Disks) Sky Lake System Configuration 10/18/17 CS162 © UCB Spring 2017 Lec 16.11 10/18/17 CS162 © UCB Spring 2017 Lec 16.12 Example Device-Transfer Rates in Mb/s Example: PCI Architecture (Sun Enterprise 6000) Memory RAM CPU Bus Host Bridge PCI #0 ISA Bridge PCI Bridge PCI #1 ISA PCI Slots USB SATA Controller Scanner Controller Controller Legacy Root Devices Hub Hard DVD Disk 10m ROM Hub Webcam • Device Rates vary over 12 orders of magnitude !!! – System better be able to handle this wide range Mouse Keyboard – Better not have high overhead/byte for fast devices! – Better not waste time waiting for slow devices 10/18/17 CS162 © UCB Spring 2017 Lec 16.13 10/18/17 CS162 © UCB Spring 2017 Lec 16.14 How does the processor actually talk to the device? Example: Memory-Mapped Display Controller Processor Memory Bus Regular Memory • Memory-Mapped: Bus Bus CPU 0x80020000 Graphics Adaptor Adaptor Device – Hardware maps control registers and display Address + Controller memory into physical address space Command Other Devices Data Bus Hardware Queue or Buses » Addresses set by HW jumpers or at boot time 0x80010000 Interrupt Interface Controller Display Controller Interrupt Request read – Simply writing to display memory (also called Memory write Addressable the “frame buffer”) changes image on screen • CPU interacts with a Controller control Memory 0x8000F000 – Contains a set of registers that status and/or » Addr: 0x8000F000 — 0x8000FFFF can be read and written Registers Queues – Writing graphics description to cmd queue (port 0x20) Memory Mapped 0x0007F004 Command – May contain memory for request » Say enter a set of triangles describing some scene queues or bit-mapped images Region: 0x8f008020 0x0007F000 Status • Regardless of the complexity of the connections and buses, processor » Addr: 0x80010000 — 0x8001FFFF accesses registers in two ways: – Writing to the command register may cause – I/O instructions: in/out instructions on-board graphics hardware to do something » Example from the Intel architecture: out 0x21,AL » Say render the above scene Physical – Memory mapped I/O: load/store instructions » Registers/memory appear in physical address space » Addr: 0x0007F004 Address » I/O accomplished with load and store instructions • Can protect with address translation Space 10/18/17 CS162 © UCB Spring 2017 Lec 16.15 10/18/17 CS162 © UCB Spring 2017 Lec 16.16 Administrivia • Midterm 2 coming up on Mon 10/23 6:30-8:00PM – All topics up to and including Lecture 16 » Focus will be on Lectures 10 – 16 and associated readings » Projects 1 and 2 » Homework 0 – 2 – Closed book – 2 pages hand-written notes both sides – Room assignment » Li Ka Shing, GPB 100, Kreober 160 BREAK • Project 2 Design Documents due today! • Sign up: Project 2 Design Reviews! 10/18/17 CS162 © UCB Spring 2017 Lec 16.17 10/18/17 CS162 © UCB Spring 2017 Lec 16.18 Transferring Data To/From Controller Transferring Data To/From Controller • Programmed I/O: • Programmed I/O: – Each byte transferred via processor in/out or load/store – Each byte transferred via processor in/out or load/store – Pro: Simple hardware, easy to program – Pro: Simple hardware, easy to program – Con: Consumes processor cycles proportional to data size – Con: Consumes processor cycles proportional to data size • Direct Memory Access: • Direct Memory Access: – Give controller access to memory bus – Give controller access to memory bus – Ask it to transfer 1 – Ask it to transfer data blocks to/from data blocks to/from memory directly memory directly 6 • Sample interaction • Sample interaction 2 with DMA controller with DMA controller 5 (from OSC book): 3 (from OSC book): 4 10/18/17 CS162 © UCB Spring 2017 Lec 16.19 10/18/17 CS162 © UCB Spring 2017 Lec 16.20 I/O Device Notifying the OS Device Drivers • Device Driver: Device-specific code in the kernel that interacts • The OS needs to know when: directly with the device hardware – The I/O device has completed an operation – Supports a standard, internal interface – The I/O operation has encountered an error – Same kernel I/O system can interact easily with different device drivers • I/O Interrupt: – Special device-specific configuration supported with the ioctl() – Device generates an interrupt whenever it needs service system call – Pro: handles unpredictable events well – Con: interrupts relatively high overhead • Polling:
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