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Linear Address Physical Address CCChahahaptptpteeerrr 222 MMMeeemmmooorrryyy AAAddddddrrreeessssssiiingngng Hsung-Pin Chang Department of Computer Science National Chung Hsing University Outline • Memory address • Segmentation – Segmentation in Hardware – Segmentation in Linux • Paging – Paging in Hardware – Paging in Linux Memory Address • Previously, a memory address is the way to access the memory cell – However, with 80x86, we have to specify the “address” precisely • Memory address – Logical address – Linear address ( or virtual address ) – Physical address Memory Address (Cont.) • Logical address – Used to specify the address of an operand or of an instruction – Consist of a segment and an offset values • Linear address – A single 32-bit unsigned integer that can be used to address up to 4GB Memory Address (Cont.) • Physical address – Used to address memory cells in memory chips – Represented as 32-bit unsigned integers logical address SEGMENTATION Linear address PAGING Physical address UNIT (HW) UNIT (HW) Segmentation in Hardware • Segmentation Registers • Segment Descriptors • Fast Access to Segment Descriptors • Segmentation Unit Segmentation Registers • A logical address consists of two parts – A segment identifier • A 16-bit field called Segment Selector – An offset that specifies the relative address within the segment • A 32-bit field Segmentation Registers (Cont.) • To quickly retrieve Segment Selectors, Intel provides segmentation registers – cs: code segment register – ss: stack segment register – ds: data segment register – es, fsand gs: general purpose Segmentation Registers (Cont.) • csregister has a 2-bit field that specified the Current Privilege Level (CPL) of the CPU – 0: highest privilege level – 3: the lowest one • Linux use only level 0 and 3 as Kernel Mode and User Mode Segment Descriptors • Each segment is represented by an 8- byte Segment Descriptor • Segment Descriptors are stored either in Global Descriptor Table (GDT) or in Local Descriptor Table (LDT) – gdtrregister points to the address of GDT in memory – ldtrregister points to the address of LDT in memory Segment Descriptors (Cont.) • Each Segment Descriptor consists of the following fields – 32-bit Base field: contain the linear address of the segment – A G granularity flag • 0: the segment size is expressed in byte • 1: it is expressed in multiple of 4096 bytes – 20-bit Limit field: denote the segment length Segment Descriptors (Cont.) – S (system) flag • 0: a system segment that stores kernel data structure • 1: a normal code or data segment – 4-bit Type field: characterizes the segment type and its access right – DPL (Descriptor Privilege Level): 2-bit field represent the minimal CPU privilege level requested for accessing the segment Segment Descriptors (Cont.) – Segment-Present flag • 0: not stored in memory • 1: in memory • Linux always set to 1 since it never swap out whole segment to disk Segment Descriptors (Cont.) • Code Segment Descriptor • Data Segment Descriptor • Task State Segment Descriptor (TSSD) – Refer to a Task State Segment (TSS), that is, a segment used to save the contents of the processor registers – Appear only in the GDT • Local Descriptor Table Descriptor (LDTD) – Refer to a segment containing an LDT – Appear only in the GDT Translating a Logical Address • As stated before – A logical address consist of a 16-bit Segment Selector and a 32-bit Offset – Segmentation registers store the Segment Selector Translating a Logical Address (Cont.) • Each Segment Selector – A 13-bit index identifies the Segment Descriptor entry contained in the GDT or LDT – A TI (Table Indicator): • 0: the Segment Descriptor is in GDT • 1: the Segment Descriptor is in GDT – A 2-bit RPL (Requestor Privilege Level) field • Equal to the Current Privilege Level in the cs register when loaded Translating a Logical Address (Cont.) 15 Selector 0 31 0 logical address Index TI Offset gdtor ldt gdtror ldtr Segment + Descriptor linear address Segment Descriptor Table Fast Access to Segment Descriptors • Intel also provides an additional nonprogrammable register for each segmentation register – Contains the 8-byte Segment Descriptor specified by the corresponding segmentation register – Once a Segment Selector is loaded in a segmentation register • The corresponding Segment Descriptor is also loaded into the matching nonprogrammable register – Thus, translations of logical address can be performed without accessing the GDT or LDT in main memory Segment Selector and Segment Descriptor Segment Selector Nonprogrammable Register 15 0 Segment Selector Segment Descriptor Segment Descriptor Segment Descriptor Table Segment Segmentation in Linux • Segmentation and Paging are similar since they both separate the physical address space of process • Linux prefers paging to segmentation since – Memory management is simpler when they share the same set of linear address – To portable since RISC architecture have limited support for segmentation Segmentation in Linux (Cont.) • Linux uses segmentation in a very limited way – Only when required by the 80x86 CPU – All processes use the same logical addressed – Try to store all Segment Descriptor in the GDT Segmentation in Linux (Cont.) • Linux uses the following segments – Kernel code segment • Base = 0x00000000 • Limit = 0xfffff • G = 1, that is, expressed in pages • S = 1, for normal code or data segment • Type = 0xa, can be read and executed • DLP = 0, for Kernel Mode – kernel 4GB code at 0x00000000 Segmentation in Linux (Cont.) – Kernel data segment • Base = 0x00000000 • Limit = 0xfffff • G = 1, that is, expressed in pages • S = 1, for normal code or data segment • Type = 2, can be read and written • DLP = 0, for Kernel Mode – kernel 4GB code at 0x00000000 Segmentation in Linux (Cont.) – User code segment shared by all processes in User Mode • Base = 0x00000000 • Limit = 0xfffff • G = 1, that is, expressed in pages • S = 1, for normal code or data segment • Type = 0xa, can be read and executed • DLP = 3, for Kernel Mode – User 4GB code at 0x00000000 Segmentation in Linux (Cont.) – User data segment shared by all processes in User Mode • Base = 0x00000000 • Limit = 0xfffff • G = 1, that is, expressed in pages • S = 1, for normal code or data segment • Type =2, can be read and written • DLP = 3, for Kernel Mode – User 4GB data at 0x00000000 Segmentation in Linux (Cont.) • A Task State Segment (TSS) for each processor – Stored in init_tss array and each segment is 236 bytes • A default Local Descriptor Table (LDT) that is shared by all processes – Include only a single entry consists of a null Segment Descriptor Segmentation in Linux (Cont.) – Four segments related to the Advanced Power Management (APM) support • APM consists of a set of BIOS routines devoted to the management of the power states of the system • Two data segments and two code segments for APM related kernel functions • Figure 2.5 Segmentation in Linux (Cont.) • Thus, when switch from Kernel Mode to User Mode – The dsregister original contains the Segment Selector of the kernel data segment – Change to the Segment Selector of the user data segment – The ssregister also have to be changed accordingly Paging in Hardware • Paging unit translates linear addresses into physical one • Linear addresses are grouped in fixed- length intervals called pages – The corresponding unit in RAM is called page frames • In 80x86, paging is enabled by setting the PG flag in cr0 control register. Otherwise, paging is disable. Paging by 80x86 • Each page is 4KB • The 32 bits of a liner address are divided into three fields – Directory: the most significant 10 bits – Table: the intermediate 10 bits – Offset: the least significant 12 bits Paging by 80x86 Linear address 31 22 21 12 11 0 Directory Table Offset 12 10 Page directory 10 Physical Address Page-Table Entry Directory Entry Page table 32 Page frame CR3 Entries of Page Directories and Page Tables • Present flag – 1: in memory – 0: not in memory and the remaining entry bits may be used by O.S. • Paging unit stores the linear address in a control register named cr2 and generate the page fault exception Entries of Page Directories and Page Tables (Cont.) • Field containing the 20 most significant bits of a page frame physical address – Since a page frame is 4KB, thus, to access a page, the 12 least significant bits of the physical address are always set to zero – If the field refers to a Page Directory, the page frame contains a Page Table – If it refers to a Page Table, the page frame contains a page of data Entries of Page Directories and Page Tables (Cont.) • Access flag – Set when paging unit addresses the corresponding page frame – Used by O.S. to select page to be swapped out – Never reset by paging unit, but only by O.S. Entries of Page Directories and Page Tables (Cont.) • Dirty page – Applied only to Page Table entries – Set each time a write operation is performed – Used by O.S. to select page to be swapped out – Never reset by paging unit, but only by O.S. Entries of Page Directories and Page Tables (Cont.) • Read/Write flag – Contain the access right of the page or of the Page Table • User/Supervisor flag – The privilege level required to access the page or Page Table • PCD (Page Cache Disable) and PWT (Page Write-Through) – Intel allow a different cache management policy with each page frame Entries of Page Directories and Page Tables (Cont.) • Page Size flag – Applies only to Page Directory entries – If set, refer to 2 MB or 4MB page frame • Global flag – Prevent frequently used page from being flushed from the TLB cache Extended Paging
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