Optimizing Oracle VM Server for X86 Performance
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Consolidation Using Oracle's SPARC Virtualization Technologies
&RQVROLGDWLRQ8VLQJ2UDFOH¶V63$5& Virtualization Technologies ORACLE TECHNICAL WHITE PAPER | OCTOBER 2015 Table of Contents Introduction 3 Designing a Consolidated Infrastructure 6 Seven Areas of Consideration for Consolidation 6 Security Isolation 6 Resource Isolation 6 Workload Efficiency 7 Availability 7 Serviceability 7 Flexibility 8 Agility 8 Requirements-Based Consolidation 9 Oracle Virtualization Technologies 9 Physical Domains (PDoms) 9 Oracle VM Server for SPARC 10 Control, I/O, Service, Guest, and Guest Root Domain Roles 11 Guest Domains Model 11 Redundant Guest Domains Model 12 SR-IOV or Direct I/O Domains Model 13 Redundant SR-IOV Domains Model 14 Guest Root Domains Model 15 Oracle Solaris Zones 16 Native Branded Zones 17 1 | ENTER TITLE OF DOCUMENT HERE Kernel Zones 18 Non-Native Branded Zones 19 Combining Virtualization Technologies 20 Redundant Guest Domains and Oracle Solaris Zones 22 Guest Root Domains and Oracle Solaris Zones 23 Root Domains and SR-IOV Domains 24 Hybrid Combination of All Oracle Virtualization Technologies 26 Summary of Characteristics for Combined Virtualization Technologies 27 Conclusion 28 About Oracle Elite Engineering Exchange 28 2 | CONSOLIDATION USING ORACLE¶¶663$5&9,578$/,=$7ION TECHNOLOGIES Introduction This paper provides a high-level overYLHZRI2UDFOH¶VYLUWXDOL]DWLRQWHFKQRORJLHVDQGit introduces a methodology for evaluating their features so that they can be matched against workload requirements by observing the following seven characteristics: » Security isolation » Resource isolation » Efficiency » Availability » Serviceability » Flexibility » Agility This methodology could also be used to evaluate other Oracle virtualization technologies, as well as other combinations of Oracle virtualization technologies not covered in this paper, such as pluggable databases in Oracle Database 12c or application consolidation within Oracle WebLogic Server. -
The Von Neumann Computer Model 5/30/17, 10:03 PM
The von Neumann Computer Model 5/30/17, 10:03 PM CIS-77 Home http://www.c-jump.com/CIS77/CIS77syllabus.htm The von Neumann Computer Model 1. The von Neumann Computer Model 2. Components of the Von Neumann Model 3. Communication Between Memory and Processing Unit 4. CPU data-path 5. Memory Operations 6. Understanding the MAR and the MDR 7. Understanding the MAR and the MDR, Cont. 8. ALU, the Processing Unit 9. ALU and the Word Length 10. Control Unit 11. Control Unit, Cont. 12. Input/Output 13. Input/Output Ports 14. Input/Output Address Space 15. Console Input/Output in Protected Memory Mode 16. Instruction Processing 17. Instruction Components 18. Why Learn Intel x86 ISA ? 19. Design of the x86 CPU Instruction Set 20. CPU Instruction Set 21. History of IBM PC 22. Early x86 Processor Family 23. 8086 and 8088 CPU 24. 80186 CPU 25. 80286 CPU 26. 80386 CPU 27. 80386 CPU, Cont. 28. 80486 CPU 29. Pentium (Intel 80586) 30. Pentium Pro 31. Pentium II 32. Itanium processor 1. The von Neumann Computer Model Von Neumann computer systems contain three main building blocks: The following block diagram shows major relationship between CPU components: the central processing unit (CPU), memory, and input/output devices (I/O). These three components are connected together using the system bus. The most prominent items within the CPU are the registers: they can be manipulated directly by a computer program. http://www.c-jump.com/CIS77/CPU/VonNeumann/lecture.html Page 1 of 15 IPR2017-01532 FanDuel, et al. -
Virtualization Strategy with Oracle VM and Oracle Linux
Virtualization Strategy with Oracle VM and Oracle Linux Bjorn Naessens Join the buzz: • Wifi pass: BANQ • Twitter – #oracleopenxperience – @oopenxperience 2 About me • Certifications – OVM 2.x/3.x Implementation Specialist – Oracle Linux 5.x Certified Administrator • Twitter – @BjornNaessens • Blog – http://bjornnaessens.wordpress.com 3 Agenda • Oracle’s Virtualization Strategy • Oracle VM 3.x • Oracle Linux • Oracle Enterprise Manager 12c • Xsigo Data Center Fabric • Q&A 4 Virtualization Strategy Oracle VM 3.x Oracle Linux Oracle’s Virtualization Strategy OEM12c Xsigo Q&A 5 Virtualization Strategy Oracle VM 3.x Oracle Linux OEM12c Xsigo Q&A Oracle’s Server to Desktop Portfolio 6 Benefits of Virtualization • Virtualization offers cost savings benefits – Server consolidation Virtualization Strategy – Lower energy, facility and labor costs Oracle VM 3.x – Lower Licensing Cost Oracle Linux OEM12c Xsigo Q&A • Virtualization offers additional benefits – Standardization – Isolate Applications – Optimize Resources 7 Oracle’s Virtualization Strategy “Virtualization that makes software easier to deploy, easier to manage, and easier to support. Not Virtualization for Virtualization’s sake.” Virtualization Strategy Oracle VM 3.x Oracle Linux OEM12c Xsigo Q&A 8 Virtualization Strategy Oracle VM 3.x Oracle Linux Oracle VM 3.x for x86 OEM12c Xsigo Q&A 9 Positioning • for both Oracle and non-Oracle applications • The only x86 server virtualization software supported Virtualization Strategy and certified for all Oracle software Oracle VM 3.x Oracle Linux • Almost no hypervisor overhead OEM12c Xsigo • Used in Oracle’s Engineered Systems Q&A (ODA, exadata, exalogic and exalytics) • Can be used to limit your license cost of Oracle Products 10 Positioning Continued • Oracle is in the “Challengers” quadrant. -
Lecture Notes
Lecture #4-5: Computer Hardware (Overview and CPUs) CS106E Spring 2018, Young In these lectures, we begin our three-lecture exploration of Computer Hardware. We start by looking at the different types of computer components and how they interact during basic computer operations. Next, we focus specifically on the CPU (Central Processing Unit). We take a look at the Machine Language of the CPU and discover it’s really quite primitive. We explore how Compilers and Interpreters allow us to go from the High-Level Languages we are used to programming to the Low-Level machine language actually used by the CPU. Most modern CPUs are multicore. We take a look at when multicore provides big advantages and when it doesn’t. We also take a short look at Graphics Processing Units (GPUs) and what they might be used for. We end by taking a look at Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC). Stanford President John Hennessy won the Turing Award (Computer Science’s equivalent of the Nobel Prize) for his work on RISC computing. Hardware and Software: Hardware refers to the physical components of a computer. Software refers to the programs or instructions that run on the physical computer. - We can entirely change the software on a computer, without changing the hardware and it will transform how the computer works. I can take an Apple MacBook for example, remove the Apple Software and install Microsoft Windows, and I now have a Window’s computer. - In the next two lectures we will focus entirely on Hardware. -
Optimizing Oracle Database on Oracle Linux with Flash
An Oracle White Paper September 2014 Optimizing Oracle Database Performance on Oracle Linux with Flash Optimizing Oracle Database Performance on Oracle Linux with Flash Introduction ....................................................................................... 1 Advantages of Using Flash-based Caching / Storage with an Oracle Database and Oracle Linux .................................................... 2 Overview of Oracle’s Sun Flash Accelerator PCIe Card .................... 2 Configuring Oracle Linux and the Oracle Database for Optimum I/O Performance ................................................................................ 3 Configure Oracle’s Sun Flash Accelerator PCIe Card as a File System ................................................................................. 3 Configure Oracle ASM Using Multiple Oracle’s Sun Flash Accelerator PCIe Cards for Mirroring or for Increased Smart Flash Cache Capacity ............................................................. 5 Configuring the Oracle Database to Use Database Smart Flash Cache .................................................................................. 5 Oracle 11g Release 2 Database Smart Flash Cache ..................... 6 Database Settings ......................................................................... 9 Benchmark Results ........................................................................... 9 Baseline Results .......................................................................... 10 Results with Database Smart Flash Cache Enabled -
Theoretical Peak FLOPS Per Instruction Set on Modern Intel Cpus
Theoretical Peak FLOPS per instruction set on modern Intel CPUs Romain Dolbeau Bull – Center for Excellence in Parallel Programming Email: [email protected] Abstract—It used to be that evaluating the theoretical and potentially multiple threads per core. Vector of peak performance of a CPU in FLOPS (floating point varying sizes. And more sophisticated instructions. operations per seconds) was merely a matter of multiplying Equation2 describes a more realistic view, that we the frequency by the number of floating-point instructions will explain in details in the rest of the paper, first per cycles. Today however, CPUs have features such as vectorization, fused multiply-add, hyper-threading or in general in sectionII and then for the specific “turbo” mode. In this paper, we look into this theoretical cases of Intel CPUs: first a simple one from the peak for recent full-featured Intel CPUs., taking into Nehalem/Westmere era in section III and then the account not only the simple absolute peak, but also the full complexity of the Haswell family in sectionIV. relevant instruction sets and encoding and the frequency A complement to this paper titled “Theoretical Peak scaling behavior of current Intel CPUs. FLOPS per instruction set on less conventional Revision 1.41, 2016/10/04 08:49:16 Index Terms—FLOPS hardware” [1] covers other computing devices. flop 9 I. INTRODUCTION > operation> High performance computing thrives on fast com- > > putations and high memory bandwidth. But before > operations => any code or even benchmark is run, the very first × micro − architecture instruction number to evaluate a system is the theoretical peak > > - how many floating-point operations the system > can theoretically execute in a given time. -
COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous Multi-Threading and Multi-Core Processors Edgar Gabriel Spring 2011
COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous multi-threading and multi-core processors Edgar Gabriel Spring 2011 Edgar Gabriel Moore’s Law • Long-term trend on the number of transistor per integrated circuit • Number of transistors double every ~18 month Source: http://en.wikipedia.org/wki/Images:Moores_law.svg COSC 6385 – Computer Architecture Edgar Gabriel 1 What do we do with that many transistors? • Optimizing the execution of a single instruction stream through – Pipelining • Overlap the execution of multiple instructions • Example: all RISC architectures; Intel x86 underneath the hood – Out-of-order execution: • Allow instructions to overtake each other in accordance with code dependencies (RAW, WAW, WAR) • Example: all commercial processors (Intel, AMD, IBM, SUN) – Branch prediction and speculative execution: • Reduce the number of stall cycles due to unresolved branches • Example: (nearly) all commercial processors COSC 6385 – Computer Architecture Edgar Gabriel What do we do with that many transistors? (II) – Multi-issue processors: • Allow multiple instructions to start execution per clock cycle • Superscalar (Intel x86, AMD, …) vs. VLIW architectures – VLIW/EPIC architectures: • Allow compilers to indicate independent instructions per issue packet • Example: Intel Itanium series – Vector units: • Allow for the efficient expression and execution of vector operations • Example: SSE, SSE2, SSE3, SSE4 instructions COSC 6385 – Computer Architecture Edgar Gabriel 2 Limitations of optimizing a single instruction -
Reverse Engineering X86 Processor Microcode
Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz, Ruhr-University Bochum https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/koppe This paper is included in the Proceedings of the 26th USENIX Security Symposium August 16–18, 2017 • Vancouver, BC, Canada ISBN 978-1-931971-40-9 Open access to the Proceedings of the 26th USENIX Security Symposium is sponsored by USENIX Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz Ruhr-Universitat¨ Bochum Abstract hardware modifications [48]. Dedicated hardware units to counter bugs are imperfect [36, 49] and involve non- Microcode is an abstraction layer on top of the phys- negligible hardware costs [8]. The infamous Pentium fdiv ical components of a CPU and present in most general- bug [62] illustrated a clear economic need for field up- purpose CPUs today. In addition to facilitate complex and dates after deployment in order to turn off defective parts vast instruction sets, it also provides an update mechanism and patch erroneous behavior. Note that the implementa- that allows CPUs to be patched in-place without requiring tion of a modern processor involves millions of lines of any special hardware. While it is well-known that CPUs HDL code [55] and verification of functional correctness are regularly updated with this mechanism, very little is for such processors is still an unsolved problem [4, 29]. known about its inner workings given that microcode and the update mechanism are proprietary and have not been Since the 1970s, x86 processor manufacturers have throughly analyzed yet. -
Assembly Language: IA-X86
Assembly Language for x86 Processors X86 Processor Architecture CS 271 Computer Architecture Purdue University Fort Wayne 1 Outline Basic IA Computer Organization IA-32 Registers Instruction Execution Cycle Basic IA Computer Organization Since the 1940's, the Von Neumann computers contains three key components: Processor, called also the CPU (Central Processing Unit) Memory and Storage Devices I/O Devices Interconnected with one or more buses Data Bus Address Bus data bus Control Bus registers Processor I/O I/O IA: Intel Architecture Memory Device Device (CPU) #1 #2 32-bit (or i386) ALU CU clock control bus address bus Processor The processor consists of Datapath ALU Registers Control unit ALU (Arithmetic logic unit) Performs arithmetic and logic operations Control unit (CU) Generates the control signals required to execute instructions Memory Address Space Address Space is the set of memory locations (bytes) that are addressable Next ... Basic Computer Organization IA-32 Registers Instruction Execution Cycle Registers Registers are high speed memory inside the CPU Eight 32-bit general-purpose registers Six 16-bit segment registers Processor Status Flags (EFLAGS) and Instruction Pointer (EIP) 32-bit General-Purpose Registers EAX EBP EBX ESP ECX ESI EDX EDI 16-bit Segment Registers EFLAGS CS ES SS FS EIP DS GS General-Purpose Registers Used primarily for arithmetic and data movement mov eax 10 ;move constant integer 10 into register eax Specialized uses of Registers eax – Accumulator register Automatically -
Oracle VM Server Virtualization
1 Copyright © 2012, Oracle and/or its affiliates. All rights reserved. The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle’s products remains at the sole discretion of Oracle. 2 Copyright © 2012,2011, Oracle and/or its affiliates. All rights Insert Information Protection Policy Classification from Slide 8 Allreserved. rights reserved. ORACLE PRODUCT LOGO Übersicht und Aktuelles zu Virtualisierungstechnologien im Oracle-Portfolio Franz Haberhauer LOGO 3 CopyrightChief © 2012, Oracle Technologist and/or its affiliates. Hardware Presales Northern Europe All rights reserved. Virtualisierung • Abstraktionsschicht zwischen Ressource und Nutzer – zwischen OS und HW: Hypervisor-basierte virtuelle Maschinen – zwischen Anwendung und OS: Ausführungsumgebungen – Effizienz • Ressourcen transparent aufteilen oder zusammenfassen – Isolation der Nutzer gemeinsamer Ressourcen – Ressourcemanagement • Provisionierung und Management – Flexibilität durch Entkopplung von Abhängigkeiten 4 Copyright © 2012, Oracle and/or its affiliates. All rights reserved. Wozu virtualisieren? Konsolidierung Flexibilität Effizienz - primär CPU -Provisionierung - Scaleout im Management - RAM? Netzwerk? - Golden Images - OS-Instanzen - Image Archiv -
Oracle VM Server for X86 Virtualization and Management
ORACLE DATA SHEET Oracle VM Server for x86 Virtualization and Management Oracle VM Server for x86 is a zero license cost server virtualization and management solution that makes enterprise applications easier to deploy, manage, and support. Backed worldwide by affordable enterprise-quality support for both Oracle and non-Oracle environments, Oracle VM reduces operations and support costs while increasing IT efficiency and agility. Engineered for Open Cloud Infrastructure ORACLE’S SERVER VIRTUALIZATION AND MANAGEMENT SOLUTION You are facing increased operating costs and inefficient resource utilization, and have an eye toward cloud computing. Your virtualization solution has to increase datacenter flexibility, meet KEY FEATURES AND BENEFITS your price/performance needs, and make applications easier to deploy, manage, and support. • Complete server virtualization and management solution with zero license Oracle VM delivers: cost • High performance and scalability: Low-overhead architecture with the Xen® hypervisor • Modern, low overhead architecture provides scalable performance under increasing workloads. Supports up to 384 physical based on the Xen hypervisor for leading price/performance CPUs and 6TB memory with each guest VM supporting up to 256 virtual CPUs and 2,000,000MB memory to accommodate the most demanding enterprise and cloud • Speeds application deployment with applications. Oracle VM Templates and virtual appliances • Broad guest operating system support: Oracle Linux, Oracle Solaris, Red Hat Enterprise Linux, SUSE Linux Enterprise Server, CentOS, Microsoft Windows. • Full Oracle VM Manager command-line interface (CLI) and Web Services API • Modern Dom0 kernel: Oracle Unbreakable Enterprise Kernel (UEK) Release 4 offers high (WS-API) allow greater automation and performance and streamlined partner certifications. interoperability • Dom0 UEK update on live systems: Oracle Ksplice updates the Dom0 UEK with all of the • Advanced virtualization features important security patches with no server reboot required. -
Oracle® VM Manager User's Guide for Release 3.3
Oracle® VM Manager User's Guide for Release 3.3 E50250-09 July 2017 Oracle Legal Notices Copyright © 2011, 2017 Oracle and/or its affiliates. All rights reserved. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish, or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, then the following notice is applicable: U.S. GOVERNMENT END USERS: Oracle programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, delivered to U.S. Government end users are "commercial computer software" pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations. As such, use, duplication, disclosure, modification, and adaptation of the programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, shall be subject to license terms and license restrictions applicable to the programs. No other rights are granted to the U.S.