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Our Tas Top 11 Technologies of the Decade Tinyos and Nesc Hardware Evolu On Our TAs Top 11 Technologies of the Decade Mo Sha Yong Fu 1.! Smartphones 7.! Drone Aircra • [email protected]" •! [email protected]" •! TinyOS tutorial." •! Grade critiques." 2.! Social Networking 8.! Planetary Rovers •! Help students with projects." •! Office Hour: by appointment." 3.! Voice over IP 9.! Flexible AC •! Manage motes." •! Bryan 502D Transmission •! Grade projects." 4.! LED Lighng •! Office Hour: Tue/Thu 5:30-6." 5.! Mul@core CPUs 10.!Digital Photography •! Bryan 502A 6.! Cloud Compung 11.!Class-D Audio Chenyang Lu 1 Chenyang Lu 2 TinyOS and nesC Hardware Evoluon ! TinyOS: OS for wireless sensor networks. ! Miniature devices manufactured economically ! nesC: programming language for TinyOS. ! Microprocessors ! Sensors/actuators ! Wireless chips 4.5’’X2.4’’ 1’’X1’’ 1 mm2 1 nm2 Chenyang Lu 4 Chenyang Lu 3 Mica2 Mote Hardware Constraints ! Processor ! Microcontroller: 7.4 MHz, 8 bit Severe constraints on power, size, and cost ! Memory: 4KB data, 128 KB program ! slow microprocessor ! Radio ! low-bandwidth radio ! Max 38.4 Kbps ! limited memory ! Sensors ! limited hardware parallelism CPU hit by many interrupts! ! Light, temperature, acceleraon, acous@c, magne@c… ! manage sleep modes in hardware components ! Power ! <1 week on two AA baeries in ac@ve mode ! >1 year baery life on sleep modes! Chenyang Lu 5 Chenyang Lu 6 Soware Challenges Tradional OS ! Small memory footprint ! Mul@-threaded ! Efficiency - power and processing ! Preemp@ve scheduling ! Concurrency-intensive operaons ! Threads: ! Diversity in applicaons & plaorm efficient modularity ! ready to run; ! Support reconfigurable hardware and soJware executing ! execu@ng on the CPU; ! wai@ng for data. gets CPU preempted needs data gets data ready waiting needs data Chenyang Lu 7 Chenyang Lu 8 Pros and Cons of Tradional OS Example: Preempve Priority Scheduling ! Each process has a fixed priority (1 highest); ! Mul@-threaded + preemp@ve scheduling ! P1: priority 1; P2: priority 2; P3: priority 3. ! Preempted threads waste memory P released ! Context switch overhead 3 P released ! I/O P2 released 1 ! Blocking I/O: waste memory on blocked threads ! Polling (busy-wait): waste CPU cycles and power P2 P1 P2 P3 0 10 20 30 40 50 60 time 10 Chenyang Lu 9 Chenyang Lu CSE 467S Context Switch Exisng Embedded OS Name Code Size Target CPU pOSEK 2K Microcontrollers pSOSystem PII->ARM Thumb process 1 VxWorks 286K Pentium -> Strong ARM PC QNX Nutrino >100K Pentium II -> NEC registers QNX RealTime 100K Pentium II -> SH4 process 2 OS-9 Pentium -> SH4 Chorus OS 10K Pentium -> Strong ARM ... CPU ARIEL 19K SH2, ARM Thumb Creem 560 bytes ATMEL 8051 ! QNX context switch = 2400 cycles on x86 memory ! pOSEK context switch > 40 µs ! Creem -> no preemp@on System architecture directions for network sensors, J. Hill, R. Szewczyk, A. Woo, S. Hollar, D. Culler, K. Pister. ASPLOS 2000. 11 Chenyang Lu CSE 467S Chenyang Lu 12 TinyOS Soluons Example: Surge ! Efficient modularity ! Applicaon = scheduler + graph of components Sur geC ! Compiled into one executable StdControl ! Only needed components are complied/loaded BootC Sur geP StdControl ADC Timer SendMsg Leds ! Concurrency: event-driven architecture Main (includes Scheduler) Application (User Components) StdControl ADC StdControl Timer StdControl SendMsg Leds PhotoC TimerC MultihopC LedsC Actuating Sensing Communication Communication Hardware Abstractions Modified from D. Culler et. Al., TinyOS boot camp presentation, Feb 2001 Chenyang Lu 13 Chenyang Lu 14 Typical Applica=on Two-level Scheduling D. Culler et. Al., TinyOS boot camp presentation, Feb 2001 application sensing application ! Events handle interrupts ! Interrupts trigger lowest level events routing Routing Layer ! Events can signal events, call commands, or post tasks ! Tasks perform deferred computaons ! Interrupts preempt tasks and interrupts messaging Messaging Layer Preempt Tasks POST FIFO packet Radio Packet commands events events byte Radio Byte (MAC) Temp commands photo SW Interrupts RFM HW Time bit clocks ADC i2c Hardware Chenyang Lu 15 Chenyang Lu 16 Mul=ple Data Flows Sending a Message ! Respond quickly: sequence of event/command through the component graph. ! Immediate execu@on of func@on calls ! e.g., get bit out of radio hw before it gets lost. ! Post tasks for deferred computaons. ! e.g., encoding. ! Events preempt tasks to handle new interrupts. Timing diagram of event propagation (step 0-6 takes about 95 microseconds total) Chenyang Lu 17 Chenyang Lu 18 Scheduling Space Breakdown… ! Interrupts preempt tasks Code size for ad hoc networking application ! Respond quickly ! Event/command implemented as func@on calls ! Task cannot preempt tasks 3500 Interrupts ! Reduce context switch efficiency 3000 Message Dispatch Initilization ! Single stack low memory footprint C-Runtime 2500 Scheduler: 144 Bytes code ! TinyOS 2 supports pluggable task scheduler (default: FIFO). Light Sensor Totals: 3430 Bytes code 2000 Clock ! Scheduler puts processor to sleep when Scheduler 226 Bytes data Led Control ! Bytes 1500 no event/command is running Messaging Layer ! task queue is empty 1000 Packet Layer Radio Interface 500 Routing Application Radio Byte Encoder 0 D. Culler et. Al., TinyOS boot camp presentation, Feb 2001 Chenyang Lu 19 Chenyang Lu 20 Power Breakdown… Time Breakdown… Active Idle Sleep Packet reception Components work breakdown CPU Utilization Energy (nj/Bit) CPU 5 mA 2 mA 5 μA AM 0.05% 0.20% 0.33 Radio 7 mA (TX) 4.5 mA (RX) 5 μA Packet 1.12% 0.51% 7.58 EE-Prom 3 mA 0 0 Ratio handler 26.87% 12.16% 182.38 Panasonic LED’s 4 mA 0 0 CR2354 Radio decode thread 5.48% 2.48% 37.2 Photo Diode 200 μA 0 0 560 mAh RFM 66.48% 30.08% 451.17 Temperature 200 μA 0 0 Radio Reception - - 1350 Idle - 54.75% - ! Lithium Baery runs for 35 hours at peak load and years at Total 100.00% 100.00% 2028.66 minimum load! •! That’s three orders of magnitude difference! ! 50 cycle task overhead (6 byte copies) ! A one byte transmission uses the same energy as approx 11000 ! 10 cycle event overhead (1.25 byte copies) cycles of computaon. Chenyang Lu 21 Chenyang Lu 22 Advantages Disadvantages ! Small memory footprint ! Lack preemp@ve real-@me scheduling ! Only needed components are complied/loaded ! Urgent task may wait for non-urgent ones ! Single stack for tasks ! Lack flexibility ! Power efficiency ! Stac linking only ! Put CPU to sleep whenever the task queue is empty ! Cannot change parts of the code dynamically ! TinyOS 2 provides efficient power management for peripherals and ! Lack virtual memory microprocessors. ! Efficient modularity ! Event/command interfaces between components ! Event/command implemented as func@on calls ! Concurrency-intensive operaons ! Event/command + tasks Chenyang Lu 23 Chenyang Lu 24 More nesC Mul@-threaded vs. event-driven architectures Programming language for TinyOS and applicaons Lack empirical comparison against exis@ng OSes Support TinyOS components A “standard” OS is more likely to be adopted by industry Whole-program analysis at compile @me Jury is s@ll out… Improve robustness: detect race condi@ons Alternave: Nave Java Virtual Machine Op@mizaon: func@on inlining Java programming Stac language Virtual machine provides protec@on No func@on pointer Example: Sun SPOT No malloc Call graph and variable access are known at compile @me Chenyang Lu 25 Chenyang Lu 26 Applica=on Interface interface Clock { command error_t setRate(char interval, char scale); Implementaon Interfaces event error_t fire(); } module: C behavior provides interface configuraon: select & wire uses interface interface Send { command error_t send(message_t *msg, uint16_t length); event error_t sendDone(message_t *msg, error_t success); module TimerP { } StdControl Timer provides { interface StdControl; interface ADC { TimerP interface Timer; command error_t getData(); } event error_t dataReady(uint16_t data); Clock uses interface Clock; } ... } Bidirec=onal interface supports split-phase operaon Chenyang Lu 27 Chenyang Lu 28 module SurgeP { provides interface StdControl; uses interface ADC; Module Configuraon uses interface Timer; uses interface Send; } StdControl Timer implementation { configuration TimerC { bool busy; provides { norace uint16_t sensorReading; interface StdControl; async event result_t Timer.fired() { StdControl Timer bool localBusy; interface Timer; atomic { TimerP } } localBusy = busy; Clock busy = TRUE; implementation { } components TimerP, HWClock; if (!localBusy) call ADC.getData(); StdControl = TimerP.StdControl; return SUCCESS; Clock Timer = TimerP.Timer; } async event result_t ADC.dataReady(uint16_t data) { HWClock sensorReading = data; TimerP.Clock -> HWClock.Clock; post sendData(); TimerC } return SUCCESS; } ... } Chenyang Lu 29 Chenyang Lu 30 Example: Surge Concurrency Race condi@on: concurrent interrupts/tasks update shared variables. Sur geC StdControl Asynchronous code (AC): reachable from at least one interrupt Sur geP BootC handler. StdControl ADC Timer SendMsg Leds Synchronous code (SC): reachable from tasks only. Any update of a shared variable from AC is a poten@al race condi@on. StdControl ADC StdControl Timer StdControl SendMsg Leds PhotoC TimerC MultihopC LedsC Chenyang Lu 31 Chenyang Lu 32 A Race Condi=on Atomic Sec=ons module SurgeP { ... } implementation { atomic { bool busy; <Statement list> norace uint16_t sensorReading; async event result_t Timer.fired() { } if (!busy) { busy = TRUE; call ADC.getData(); Disable interrupt when atomic code is being executed } return SUCCESS; But cannot disable interrupt for long! } No loop task void sendData()
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