Posits: an Alternative to Floating Point Calculations
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Rochester Institute of Technology RIT Scholar Works Theses 5-2020 Posits: An Alternative to Floating Point Calculations Matt Wagner [email protected] Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Wagner, Matt, "Posits: An Alternative to Floating Point Calculations" (2020). Thesis. Rochester Institute of Technology. Accessed from This Master's Project is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. POSITS:AN ALTERNATIVE TO FLOATING POINT CALCULATIONS by MATT WAGNER GRADUATE PAPER Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in Electrical Engineering Approved by: Mr. Mark A. Indovina, Senior Lecturer Graduate Research Advisor, Department of Electrical and Microelectronic Engineering Dr. Sohail A. Dianat, Professor Department Head, Department of Electrical and Microelectronic Engineering DEPARTMENT OF ELECTRICAL AND MICROELECTRONIC ENGINEERING KATE GLEASON COLLEGE OF ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY ROCHESTER,NEW YORK MAY, 2020 I dedicate this paper to everyone along the way. Declaration Declaration I hereby declare that except where specific reference is made to the work of others, that all content of this Graduate Paper are original and have not been submitted in whole or in part for consideration for any other degree or qualification in this, or any other University. This Graduate Project is the result of my own work and includes nothing which is the outcome of work done in collaboration, except where specifically indicated in the text. Matt Wagner May, 2020 Acknowledgements I would like to thank everyone that has helped me get to where I am. I would like to specifically thank my advisor, Mark Indovina, for helping me put in the hours and always offering help. Abstract Floating point arithmetic is one of several methods of performing computations in digital de- signs; others include integer and fixed point computations. Fixed point utilizes a method com- parable to scientific notation in the binary domain. In terms of computations, floating pointis by far the most prevalent in today’s digital designs. Between the support offered by compilers, as well as for ready-to-use IP blocks, floating point units (FPU’s) are a de-facto standard for most processors. Despite its prevalence in modern designs, floating point has many flaws. One of the most common is the use of not-a-numbers (NaN’s). These are meant to provide a way of signaling invalid operation, however the excessive amount of them wastes usable bit patterns. As an alternative to floating point, a system named "Universal Numbers" or UNUMs wasde- veloped. This system consists of three different types, however for hardware compatibility, the Type III provides the best stand in for floating point. This system eliminates the NaN problem by only using one bit pattern, and also provides many other inherent benefits. Contents Contents v List of Figures ix List of Tablesx 1 Introduction1 1.1 Research Goals . .2 1.2 Organization . .2 2 Floating Point Representation4 2.1 Development . .4 2.2 Format . .5 2.3 Conversion . .6 2.3.1 Determine Sign . .6 2.3.2 Determine Exponent . .6 2.3.3 Determine Fractional Component . .7 2.4 Floating Point Exceptions . .8 2.4.1 Zero and Infinity . .8 2.4.2 Not a Number (NaN) . .9 2.4.3 Subnormal Numbers . .9 2.5 Floating Point Problems . .9 2.5.1 Meaningless Exceptions . 10 2.5.2 Unnecessary Hardware . 10 2.5.3 Overflow . 10 2.5.4 Round-off . 11 3 Unum Representation 12 3.1 Type I Unums . 12 3.1.1 Format . 12 3.1.1.1 U-Bit . 13 3.1.1.2 Exponent & Fraction Size Bits . 13 Contents vi 3.1.2 Type I Unum Characteristics . 14 3.2 Type II Unums . 15 3.2.1 Design . 15 3.2.2 Operations . 17 3.2.3 Accuracy . 17 3.2.4 Hardware Cost . 18 3.3 Interval Arithmetic . 18 4 Posit Representation 20 4.1 Background . 20 4.2 Format . 21 4.3 Regime . 21 4.4 Scaling Factor . 22 4.5 Exponent . 23 4.6 Fraction . 23 4.7 Exceptions . 24 4.8 Benefits . 24 5 Floating Point Core Design 26 5.1 Hierarchical Design . 26 5.2 Data Path . 27 5.2.1 Unpack Module . 28 5.2.2 Exception Handler . 28 5.2.3 Adder/Subtractor . 28 5.2.4 Multiplication . 29 5.2.4.1 Hardware Multiplier . 31 5.2.5 Divider . 31 5.2.5.1 Hardware Divider . 32 5.3 Post-Processor . 32 5.3.1 Rounding Block . 33 5.3.2 Packing Block . 34 5.4 Timing . 34 6 Posit Core Design 36 6.1 Hierarchical Design . 36 6.1.1 Control Logic . 37 6.1.2 Extraction Block . 37 6.1.3 Scaling Block . 37 6.1.3.1 Addition/Subtraction Scaling . 38 6.1.3.2 Multiplication/Division Scaling . 39 6.2 Operation Block . 39 Contents vii 6.3 Decoding Block . 40 6.4 Timing . 41 7 Testbench Design 42 7.1 Testbench . 42 7.1.1 UVM Testbench . 43 7.1.1.1 Top Level . 43 7.1.1.2 Test Case . 44 7.1.1.3 UVM Sequence . 44 7.1.1.4 UVM Environment . 45 7.1.1.5 UVM Scoreboard . 45 7.1.1.6 UVM Agent . 46 7.1.1.7 UVM Sequencer . 46 7.1.1.8 UVM Driver . 47 7.1.1.9 UVM Monitor . 47 7.2 Analysis . 47 8 Hardware Results 50 8.1 Hardware Synthesis . 50 8.2 DFT Insertion . 51 8.3 Analysis Results . 52 9 Conclusions and Further Research 54 9.1 Conclusions . 54 9.2 Future Research . 55 References 57 I FPU Source Code I-1 I.1 FPU Top Level . I-1 I.2 FPU Data Path . I-6 I.3 FPU Unpack . I-15 I.4 FPU Exception Handler . I-17 I.5 FPU Adder/Subtractor . I-22 I.6 FPU Multiplier . I-30 I.7 FPU Divider . I-38 I.8 FPU Post Processor . I-46 I.9 FPU Rounding . I-49 I.10 FPU Packing . I-51 I.11 FPU Test Frame . I-53 Contents viii II PAU Source Code II-1 II.1 PAU Top Level . II-1 II.2 PAU Extraction . II-9 II.3 PAU Scaler . II-12 II.4 PAU Operator . II-17 II.5 PAU Decoder . ..