Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

Improved Reconfigurable based Lightweight Crypto Algorithms for IoT based Applications Dr.G. Mohammed Gouse, Assistant Professor, Department of Computer Networking, College of Engineering and Computer Science, Lebanese French University, Erbil, Iraq. E-mail: [email protected] Chiai Mohammed Haji, Lecturer, Department of Information Technology, College of Engineering and Computer Science, Lebanese French University, Erbil, Iraq. E-mail: [email protected] Dr. Saravanan, Assistant Professor, Debre Berhan University, Debre Berhan, Ethiopia. E-mail: [email protected] Abstract--- Internet of Things (IoT) based devices were integrated with most of the -day activities and applications. IoT combines various heterogeneous devices along with security, privacy, communication and computing. Different malicious attacks, Denial of Service (DoS) and hacking the information are possible to collapse the IoT network. Traditional security and authentication algorithm for secure communication will not properly fit with present IoT situation. To address this issue, this paper focuses on lightweight crypto algorithms with improved configurations. This proposed algorithm concentrates on Generalized along with pipeline mechanism. Experiments are targeted to reconfigurable device such as Field Programmable Gate Array (FPGA) and compared with various existing methods in terms of hardware resource utilization, maximum frequency and power. Experimental results show that proposed method will be well fit with IoT based applications in terms of high throughput, low power activity and more efficient. Keywords--- Lightweight Crypto Algorithms, Information Security, Feistel Cipher, FPGA, Internet of Things (IoT).

I. Introduction Internet of Things (IoT) based applications and innovations are growing rapidly without any boundaries. It helps in creating communication between dissimilar of various devices in heterogeneous environment. IoT also provides more comfort to the user by maintaining various secure services like confidentiality, authentication, integrity and authorization. These services give trust on transit information, verified received data, prevent intruder in modifying original data and better authentication to access the resources. Internet based communication connects low power resources with different nature of devices and computes process to achieve the task in the network. Due to the huge number of communications, it is necessary to trust the security of information. Possible of threat may result in this heterogenous device based secure communication. IoT is influenced by number of attacks like man in middle attack, saturation attack, related attack, differential attack and Denial of Service (DoS) attack. These attacks will collapse the devices physically and damage the network communication and leads to unauthorized access. So, providing better authentication, confidentiality, low power devices and integrity of information are the main challenging task of future IoT. Security Architecture of IoT reference model is shown in table 1. It contains 7 basic layer and have an inside view of security protocols, various attacks, basic security, target and activities. In the physical layer, IEEE 802.15.4 and MAC of IoT are considered as security protocol. It gets the real time signals from sensors and devices like GPRS and RFID. Basic IoT security provided by random number generator. Jamming and battery exhausted attacks are considered in this layer. In the data link layer, ATM and FDDI kind of protocols are used. Collision and spoofing attacks are possible in this IoT layer. In the network layer, Internet protocol like IPv6 and IP routing are functioning. Basic IoT security can be provided in key management to prevent replay attack. In the transport layer, UDP and DTLS security protocols are considered. It provides basic IoT security in and also prevent data flooding attack. In the session layer, NFS and SCP related authentication protocols are used. Efficient authentication provides for IoT security. Data aggregation is possible attack IoT. In the presentation layer, DNS and HTTP based protocols are considered for various applications. For secure IoT, this layer provides anti-virus compatible to avoid data diverse attack. In the application layer, various security protocols like COAP, XMPP and AMQP are used. For better IoT security, network firewall is provided to prevent application data process attack. Thus, the above observation gives overall view of various attacks in all the layers of secure IoT reference model.

ISSN 1943-023X 186 Received: 23 October 2018/Accepted: 21 November 2018 Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

Table 1: Security Architecture of IoT Reference Model

Layer Security Protocol Attacks Basic Security Target Activities Application COAP, MQTT, Depend on protocol Network Firewall People and Transformational decision based Layer XMPP, AMQP Process on thing apps and data Presentation DNS, Date Diverse Anti-virus Applications Custom Apps built using thing Layer HTTP data Session Layer NFS, Data Aggregation Authentication Data Analysis Reporting, Mining, Aggregation SCP Distortion Transport UDP, DTLS Flooding attack Encryption Data Ingestion Big Data, Storage of Thing Data Layer Network Layer IPv6, Replay attack Key management Global Cloud infrastructure – public, IP routing Infrastructure private Data Link ATM, Collision attack, Trust Zone Connectivity Communication protocols, Layer FDDI Spoofing attack Computing M2M, Wi-fi Physical Layer IEEE 802.15.4 Jamming, Battery Random number Things Devices, MAC exhaustion generator Sensors, controllers To address the need of secure communication, various cryptographic algorithms are considered. Basic structure of cryptographic algorithms is classified into symmetric and asymmetric algorithms. In symmetric cryptographic algorithm, single private key is used for security purpose. Sender and receiver uses the same private key for secure communication. It gives better confidentiality and integrity on transit data with less number of keys but fails to provide better authentication. AES, DES, IDEA, are considered as traditional symmetric cryptographic algorithms. In asymmetric cryptographic algorithm, public and private key is used for secure communication. It provides better confidentiality, integrity and authentication but increases the complexity of the algorithm by large . RSA, Diffie Helmen, Hash functions, Elliptic curve are famous asymmetric algorithms. General procedure of symmetric and asymmetric cryptographic algorithms not able to integrate with IoT based environment due to consumption of more power, more memory and more computational resources. So, it is necessary to incorporate smart cryptographic algorithms with low power activity, low memory and better computational resources. To address this issue, lightweight based security algorithms are considered. Lightweight solution is known as in terms of less key size, less memory usage and speed in process. Various like Feistel, Substitution and Permutation Network (SPN), EDFN are considered depends upon their internal arrangements of plain text and key combinations. Feistel structure [28] divides the plain text into two equal-half of data and proceed each round. For decryption process, it uses the same program code of encryption functionality with help of reverse key logic. Thus, it reduces the additional hardware and resource implementation. Feistel cipher is basically classified as Generalized Feistel structure and Classical Feistel structure. For better security, more number of rounds is considered in Generalized Feistel structure. [17], HISEC [43], GIFT [10], GRANULE [9], DLBCA [11], LiCi [12] are some popular Feistel networks. Substitution and Permutation Networks (SNP) based operations are achieved by series of mathematical link process. In substitution function, non-linear look-up table-based S-Box operation is performed. In permutation function, invertible linear transformation operation is considered. LED [19], PRINCE [40], RECTANGLE [16], MANTIS [33], GIFT [10] are some of widely used SPN based block ciphers. Table 2 shows various popular lightweight cryptographic algorithms. It projects the structure of lightweight, number of rounds which is used in permutation, key size, block size and possible attacks. Table 2: Popular LIGHTWEIGHT Cryptographic Algorithms Lightweight Algorithm Structure Number of rounds Key size Block size Possible Attacks LED [19] SPN 32 64 64 Dedicated attack PRINCE [40] SPN 12 128 64 Saturation attack SIMON [17] Feistel 32 64 32 Differential attack HISEC [43] Feistel 15 80 64 Collision attack RECTANGLE [16] SPN 25 80 / 128 64 MANTIS [33] SPN 10 / 12 128 64 Meet-in-the-attack Lilliput [8] EGFN 30 80 64 Differential attack GIFT [10] SPN 28 / 40 128 64 / 128 Less robust SIT [42] Feistel + SPN 5 64 64 Schedule attack Granule [9] Feistel 32 128 64 Slide attack DLBCA [11] Feistel 15 80 32 Key attack LiCi [12] Feistel 31 128 64 Collision attack

ISSN 1943-023X 187 Received: 23 October 2018/Accepted: 21 November 2018 Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

II. Related Works Lightweight cryptographic algorithms attract more attention due to the demand of Internet of Things (IoT). In this present decade, many researchers address the various solutions to this particular emerging technology. Improved security and trustable communication has led many research publications in the field of lightweight cryptographic for IoT based applications. IoT device survey, security challenges and its emerging need were discussed in paper [3,5, 6, 15,22,24,27]. In paper [18], embedded security was achieved by lightweight encryption concept. IoT security was analyzed with various paraments in paper [23]. In paper [1,14], the author gave a detailed review of lightweight block ciphers by providing various comparison between block structure, key size and block size. It also shows comparative study and open issues related to low resources devices. In paper [21], analysis of various architecture parameters like power, energy and area for lightweight was discussed. In paper [4], hardware based lightweight block cipher was proposed. It also shows how to model block cipher for secure communication. Symmetric algorithm and lightweight symmetric survey [7,26] was conducted with various comparative analysis. Various implementation in AES S-Box with high throughput and low power [29], lightweight S-Box [30], low power S-Box [31], lightweight block cipher [32] were also elaborated. Optimal lightweight AES encryption on FPGA was explained in paper [2]. In paper [13], lightweight algorithms like HIGHT block cipher was designed and targeted to FPGA device. Pipeline base technique on FPGA was proposed in paper [20]. Unroll architecture for 64-bit secure algorithm [25] was observed in FPGA. AES algorithm [34], Gigabit DES [35], Two methods of RSA [36] and extended recipes for AES on FPGA [41] were also targeted to FPGA platform. In paper [16], the author claimed RECTANGLE lightweight block cipher suitable for multiple platforms like hardware and software. Various lightweight based block cipher named Lilliput [8], GRANULE [9], GIFT [ 10], DLBCA [11], LiCi [12], SIMON [17], [17], LEA [19], MANTIS [33], PRESENT [37], LED [38], Hybrid lightweight [39], PRINCE [40], SIT [42] and HISEC [43] were developed. Even after observing various lightweight algorithms, still there is demand for better lightweight algorithms. Low power, high performance, low resource utilization and secure communication are still the urge need for future IoT based application

III. Proposed Design This paper focuses on Generalized Feistel cipher [28] based lightweight algorithm. It is a symmetric structure with less key size. It has the advantages of no extra design need for decryption process because, it is similar to encryption operations flow in most of the cases. It is possible to achieve by reversal of the key scheduling used in encryption and decryption process. Thus, it is also helps to achieve compatible code size, less memory and less hardware resources. A Feistel cipher network [28] is described by a general function (F) in terms of {0,1}2n →{0,1}2n. It is n n parameterized by the number of rounds d N and the round functions f1,f2,f3...,fd: {0,1} →{0,1} . The general function F, operates in ‘d’ number of rounds (typically between 12 and 16). In the ith round, plain text is divided into two halves like Li−1|| Ri−1, and the round function∈ fi is applied to the right half results fi(Ri−1). Next step is to include the Exclusive-OR (EX-OR) logic operation value and the left half yield Li−1 fi(Ri−1). In the last step, the left and right side are swapped, thus yielding the round output Li||Ri = Ri−1 || Li−1 fi (Ri−1). The main objective of the function F defined by a Feistel cipher network is a permutation for arbitrary⊕ functions fi. particularly these do not even need to be invertible. ⊕ Thus, due to simple and less utilization of resources Feistel cipher networks are very popular in lightweight cryptographic algorithms. In Generalized Feistel cipher network, Plain text (P) and Cipher text (C) have the length of N bit along with Secrete Key are considers as follows. 0 0 0 0 The input plain text P = X = (X 1, X 2,…….. X n ) i i-1 i i-1 i-1 For i = 1,2,3,…r X n = X n XOR F (X 1, X 2,…….. X n) r r r r The output cipher text C = X = (X 1, X 2,…….. X n ).

ISSN 1943-023X 188 Received: 23 October 2018/Accepted: 21 November 2018 Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

Proposed Pseudo Code for Pipeline Concept Encryption Process

Input: 128 Key (Ki) and Plain text (Xi) Output: Cipher text (Ci) Split (Xi) block into two equal pieces as (Left0, Right0) Consider Ki for odd and even pipeline concept For each round i=0,1,2,..n for pipeline Li+1 = Ri Ri+1=Li XOR F(Ri, Ki). Merge pipeline output Output cipher text is (Rn+1, Ln+1) Decryption Process

Cipher text (Rn+1, Ln+1) Split pipeline output For each round i=n,n-1,…0 Ri = Li+1 Li = Ri+1 XOR F(Li+1, Ki). Merge pipeline output Output plain text is (L0, R0 ) Proposed Block Diagram for Pipeline Concept Lightweight Feistel cipher block along with pipeline (Figure 1) concept is proposed in this paper. As per the pseudo code steps, input plain text (64 bit) were divided into two equal portions as Left (L0) and Right (R0). Thus, each split portion will get 32-bit of plain text. Then Key (Ki) is consider for odd and even based groups to achieve pipe functionality. This groups will work independently to achieve the process faster in computation. In earlier methods key were arranged in sequential order like one by one in the memory. It will take more time in fetching the key and processing with current round function. This proposed method provides various registers to the design at the input (R0, R1, R2.. Rn) between (Ki) and also for direct functional path. In hardware-based pipeline, when first clock is activated Even key will performed. So, keys K0, K2… Kn stored in registers R0, R2…Rn will get the latest key values and process. After the round function the updated values will be stored in the corresponding register. In the second clock, odd key K1, K3… Kn-1 will be activated with R1, R3…Rn-1. In this stage there is a possibility of getting new results. This means different set of data like previous and present results can be operate at the same time with help of pipeline concept. Thus, reconfigurable FPGA based design will help for holding earlier and current results. In non- pipeline design, only single output function is possible. So, the process will take more time. But in pipeline-based design the registers are used to store the functional results of the individual stages of lightweight Feistel cipher block design. These components add to the logic resources used by the design and increase the hardware.

Even L0 R0 Odd Keys Keys

K0 F

F K1

K 2 F

Kn-1 For n round

Figure 1: Proposed Feistel Cipher with Pipeline

ISSN 1943-023X 189 Received: 23 October 2018/Accepted: 21 November 2018 Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

IV. Experimental Results Lightweight Feistel cipher along with pipeline concept promises for improved security of IoT based applications. This proposed method is target to reconfigurable Field Programmable Gate Array (FPGA) based device known as Cyclone IV EP4CE15F23C6 using Quartus Prime 17.1. Proposed algorithm is compared with other existing algorithms in terms of hardware resource utilization, maximum frequency and power consumption. In table 3, hardware resource utilization is compared with other algorithms. AES32 [41], AES128 [41] and AES128U [41] consumed more hardware in terms of Block RAM (BRAM) and DSP in Virtex-5 FPGA. But Logic Element (LE), Combinational Functions and Register (Flipflop) consumption are very less when compared with other algorithms. In AES-pipeline usage of register resource are in more than proposed method. In paper [34 – 36], usage of combinational functions is very huge in numbers when compared with our method. Proposed method has reasonable amount of increase in resource utilization due to pipe line mechanism. Table 3: Comparison of Hardware Resource Utilization Design Target LE/ Com. function Reg (FF) Others Slices Component AES-Pipeline [2] Cyclone IV EP4CE30F29C 2059 2509 1678 AES S-Box [29] Cyclone III EP3C5F256C6 95 75 90 AES S-box [30] Cyclone III EP3C5F256C6 66 66 36 AES S-Box [31] Cyclone III EP3C5F256C6 71 68 32 A – Design [32] Cyclone II EP2C20F484C7 1818 -- -- B – Design [32] Cyclone II EP2C20F484C7 2234 -- -- AES32 [41] Virtex-5 107 320 257 BRAM -2 DSP - 4 AES128 [41] Virtex-5 259 338 624 BRAM - 8 DSP – 16 AES128U [41] Virtex-5 321 738 1031 BRAM - 80 DSP - 160 [34] Spartan II-6 -- 12,288 -- [35] Virtex-6 -- 73,728 -- [36] APEX 20KE-1 -- 102,400 -- Proposed Method Cyclone IV EP4CE15F23C6 9974 9883 199 Maximum frequency of various methods compared with proposed method and tabulated in table 4. Having the FPGA architecture at 100 MhZ, the timing analysis are analyzed with TimeQuest Timing analyzer tool. AES32 [41], AES128 [41] and AES128U [41] consumes more resources and produces more frequency. Compared with [41], proposed method achieves 447.23 MhZ with reasonable hardware resources. When compared with [2], [29 – 31] algorithms our proposed method evident for more frequency. Proposed pipeline concept produces more maximum frequency when compared with other existing algorithms. Thus, pipeline-based design gives maximum speed or will run faster than non-pipeline design. Table 4: Comparison of Maximum Frequency (Fmax) Design Target Fmax (100 Mhz) AES-Pipeline [2] Cyclone IV EP4CE30F29C 241.6 AES-LUT [2] Cyclone IV EP4CE30F29C 215.84 AES-CFA [2] Cyclone IV EP4CE30F29C 136.54 AES-LFSR [2] Cyclone IV EP4CE30F29C 142.9 AES S-Box [29] Cyclone III EP3C5F256C6 380.66 AES S-Box [30] Cyclone III EP3C5F256C6 170.44 AES S-box [31] Cyclone III EP3C5F256C6 346.26 AES32 [41] Virtex-5 550 AES128 [ 41] Virtex-5 550 AES128U [41] Virtex-5 413 Proposed Method Cyclone IV EP4CE15F23C6 447.23 Proposed work also targets to observe the power consumption and compared with earlier methods which is provided in Table 5. LED [19] consumes more power when compared with other existing methods. Most of the existing methods consumes more dynamic power (mW) rather than static power. Total power is calculated by both dynamic and static power consumption. Proposed algorithm coding contains only static power consumption. As per the report no occurrence of dynamic power consumption.

ISSN 1943-023X 190 Received: 23 October 2018/Accepted: 21 November 2018 Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

Table 5: Comparison of Power Consumption Design Target Dynamic (mW) Static (mW) Granule [9] ASIC - UMCL180 27 -- PRESENT [ 37] ASIC - UMCL180 38 -- RECTANGLE [16] ASIC - UMCL180 31 -- LED [19] ASIC - UMCL180 89 -- AES S-Box [29] Cyclone III EP3C5F256C6 2.26 -- AES S-box [30] Cyclone III EP3C5F256C6 1.84 -- AES S-Box [31] Cyclone III EP3C5F256C6 0.15 -- Proposed Method Cyclone IV EP4CE15F23C6 -- 85.02 Experimental result evident that proposed pipeline based lightweight Feistel cipher can produce better throughput in terms of maximum frequency. Thus, this proposed algorithm gives more adoptable to secure communication for IoT based applications.

V. Conclusion

Internet of Things (IoT) based applications has more impact on various possibilities of threatens and attacks. Providing secure based communication network for heterogenous devices are major challenges to IoT. Conventional security protocols are not comfort with present need of secure IoT communication. Lightweight crypto algorithms are providing improved solutions to this issue. Our proposed algorithm emphasis on Feistel lightweight cipher combined with pipeline design. Experiment results are targeted to Cyclone IV EP4CE15F23C6 FPGA and observes hardware resource utilization, maximum frequency and power consumption. Our proposed algorithm consumes reasonable increase in hardware resource utilization due to pipeline design. It also provides improved maximum frequency and low power consumption when compared with other existing algorithms. Thus, it is evident to use this proposed algorithm for secure communication of IoT based applications.

References [1] Hatzivasilis, G., Fysarakis, K., Papaefstathiou, I. and Manifavas, C. A review of lightweight block ciphers. Journal of Cryptographic Engineering 8 (2) (2018) 141-184. [2] Wong, M. M., Wong, D. M., Zhang, C. and Hijazin, I. Circuit and system design for optimal lightweight AES encryption on FPGA. International Journal of Computer Science 45 (1) (2018). [3] Yaqoob, I., Ahmed, E., Ur Rehman, M. H., Ahmed, A. I. A., Al-garadi, M. A., Imran, M. and Guizani, M. The rise of and emerging security challenges in the Internet of Things. Computer Networks 129 (2017) 444-458. [4] Mohd, B. J., Hayajneh, T., Yousef, K. M. A., Khalaf, Z. A. and Bhuiyan, M. Z. A. Hardware design and modeling of lightweight block ciphers for secure communications. Future Generation Computer Systems 83 (2018) 510-521. [5] Singh, S., Sharma, P. K., Moon, S. Y. and Park, J. H. Advanced lightweight encryption algorithms for IoT devices: survey, challenges and solutions. Journal of Ambient Intelligence and Humanized Computing, 2017, 1-18. [6] Shamir, A., Biryukov, A. and Perrin, L. P. Summary of an Open Discussion on IoT and Lightweight Cryptography. Proceedings of Early Symmetric Crypto workshop. University of Luxembourg, 2017. [7] Biryukov, A. and Perrin, L. P. State of the art in lightweight symmetric cryptography. International Association for Cryptologic Research, 2017. [8] Ali, M. P. and George, G. T. Optimised Design of Light Weight Block Cipher Lilliput with Extended Generalised Feistal Network (EGFN). International Journal of Innovative Research in Science, Engineering and Technology 6 (4) (2017). [9] Bansod, G., Patil, A. and Pisharoty, N. GRANULE: An Ultra lightweight cipher design for embedded security. IACR Cryptology ePrint Archive, 2018. [10] Banik, S., Pandey, S. K., Peyrin, T., Sasaki, Y., Sim, S. M. and Todo, Y. GIFT: a small PRESENT. International Conference on Cryptographic Hardware and Embedded Systems, 2017, 321-345. [11] AlDabbagh, S. S. M. Design 32-bit Lightweight Block Cipher Algorithm (DLBCA). International Journal of Computer Applications 166 (8) (2017). [12] Patil, J., Bansod, G. and Kant, K. S. LiCi: A new ultra-lightweight block cipher. International Conference on Emerging Trends & Innovation in ICT (ICEI), 2017, 40-45.

ISSN 1943-023X 191 Received: 23 October 2018/Accepted: 21 November 2018 Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

[13] Mohd, B. J., Hayajneh, T., Khalaf, Z. A. and Ahmad Yousef, K. M. Modeling and optimization of the lightweight HIGHT block cipher design with FPGA implementation. Security and Communication Networks 9 (13) (2016) 2200-2216. [14] Mohd, B. J., Hayajneh, T. and Vasilakos, A. V. A survey on lightweight block ciphers for low-resource devices: Comparative study and open issues. Journal of Network and Computer Applications 58 (2015) 73-93. [15] Andrea, I., Chrysostomou, C. and Hadjichristofi, G. Internet of Things: Security vulnerabilities and challenges. IEEE Symposium on Computers and Communication (ISCC), 2015, 180-187. [16] Zhang, W., Bao, Z., Lin, D., Rijmen, V., Yang, B. and Verbauwhede, I. RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms. Science China Information Sciences 58 (12) (2015) 1-15. [17] Beaulieu, R., Treatman-Clark, S., Shors, D., Weeks, B., Smith, J. and Wingers, L. The SIMON and SPECK lightweight block ciphers. 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, 1-6. [18] Bansod, G., Raval, N. and Pisharoty, N. Implementation of a new lightweight encryption design for embedded security. IEEE Transactions on information forensics and security 10 (1) (2015) 142-151. [19] Hong, D., Lee, J. K., Kim, D. C., Kwon, D., Ryu, K. H. and Lee, D. G. LEA: A 128-bit block cipher for fast encryption on common processors. International Workshop on Information Security Applications, 2013, 3-27. [20] Boemo, E., Oliver, J. P. and Caffarena, G. Tracking the pipelining-power rule along the FPGA technical literature. Proceedings of the 10th FPGA world Conference, 2013, 1–9. [21] Batina, L., Das, A., Ege, B., Kavun, E. B., Mentens, N., Paar, C. and Yalçın, T. Dietary recommendations for lightweight block ciphers: power, energy and area analysis of recently developed architectures. International Workshop on Radio Frequency Identification: Security and Privacy Issues, 2013, 103-112. [22] Ho, G., Leung, D., Mishra, P., Hosseini, A., Song, D. and Wagner, D. Smart locks: Lessons for securing commodity internet of things devices. Proceedings of the 11th ACM on Asia conference on computer and communications security, 2016, 461-472. [23] Li, S., Tryfonas, T. and Li, H. The Internet of Things: a security point of view. Internet Research 26 (2) (2016) 337-359. [24] Kumar, S. A., Vealey, T. and Srivastava, H.. Security in internet of things: Challenges, solutions and future directions. 49th Hawaii International Conference on System Sciences (HICSS), 2016, 5772-5781. [25] Khan, S., Ibrahim, M. S., Amjad, H., Khan, K. A. and Ebrahim, M. FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture. IEEE International Conference on Control System, Computing and Engineering (ICCSCE), 2015, 1-6. [26] Ebrahim, M., Khan, S. and Khalid, U. B. Symmetric algorithm survey: a comparative analysis. International Journal of Computer Applications 61 (20) (2014). [27] Gubbi, J., Buyya, R., Marusic, S. and Palaniswami, M. Internet of Things (IoT): A vision, architectural elements, and future directions. Future generation computer systems 29 (7) (2013) 1645-1660. [28] Biryukov, F.C. Encyclopedia of cryptography and security. Springer, 2011. [29] Wong, M. M. and Wong, M. L. D. A high throughput low power compact AES S-box implementation using composite field arithmetic and Algebraic Normal Form representation. 2nd Asia Symposium on Quality Electronic Design (ASQED), 2010, 318-323. [30] Wong, M. M. and Wong, M. L. D. A new lightweight and high performance aes s-box using modular design. IEEE International Conference on Circuits and Systems (ICCAS), 2013, 65-70. [31] Morioka, S., and Satoh, A. An optimized S-Box circuit architecture for low power AES design. International Workshop on Cryptographic Hardware and Embedded Systems, 2002, 172-186. [32] Tay, J. J., Wong, M. M. and Hijazin, I. Compact and low power aes block cipher using lightweight key expansion mechanism and optimal number of s-boxes. International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2014, 108-114. [33] Beierle, C., Jean, J., Kölbl, S., Leander, G., Moradi, A., Peyrin, T. and Sim, S. M. The SKINNY family of block ciphers and its low-latency variant MANTIS. Annual Cryptology Conference, 2016, 123-153. [34] Chodowiec, P. and Gaj, K. Very compact FPGA implementation of the AES algorithm. International Workshop on Cryptographic Hardware and Embedded Systems, 2003, 319-333. [35] Chodowiec, P., Gaj, K., Bellows, P. and Schott, B. Experimental testing of the gigabit IPSec-Compliant implementations of Rijndael and triple DES using SLAAC-1V FPGA accelerator board. International Conference on Information Security, 2001, 220-234.

ISSN 1943-023X 192 Received: 23 October 2018/Accepted: 21 November 2018 Jour of Adv Research in Dynamical & Control Systems, Vol. 10, No.12, 2018

[36] Fischer, V. and Drutarovský, M. Two methods of Rijndael implementation in reconfigurable hardware. International Workshop on Cryptographic Hardware and Embedded Systems, 2001, 77-92. [37] Bogdanov, A., Knudsen, L. R., Leander, G., Paar, C., Poschmann, A., Robshaw, M. J. and Vikkelsoe, C. PRESENT: An ultra-lightweight block cipher. International Workshop on Cryptographic Hardware and Embedded Systems, 2007, 450-466. [38] Guo, J., Peyrin, T., Poschmann, A. and Robshaw, M. The LED Block Cipher, Cryptographic Hardware and Embedded Systems CHES. LNCS, 2011, 326-341. [39] Patil, A., Bansod, G. and Pisharoty, N. Hybrid lightweight and robust encryption design for security in IoT. International Journal of Security and Its Applications 9 (12) (2015) 85-98. [40] Borghoff, J., Canteaut, A., Güneysu, T., Kavun, E. B., Knezevic, M., Knudsen, L. R. and Rombouts, P. Prince–a low-latency block cipher for pervasive computing applications. In International Conference on the Theory and Application of Cryptology and Information Security, 2012, 208-225. [41] Drimer, S., Güneysu, T. and Paar, C. DSPs, BRAMs, and a pinch of logic: Extended recipes for AES on FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 3 (1) (2010). [42] Usman, M., Ahmed, I., Aslam, M. I., Khan, S. and Shah, U. A. Sit: A lightweight encryption algorithm for secure internet of things. arXiv preprint arXiv:1704.08688., 2017. [43] AlDabbagh, S. S. M., Shaikhli, A., Taha, I. F. and Alahmad, M. A. Hisec: A new lightweight block cipher algorithm. Proceedings of the 7th International Conference on Security of Information and Networks, 2014.

ISSN 1943-023X 193 Received: 23 October 2018/Accepted: 21 November 2018