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International Journal of Soft Computing and Engineering International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-8S2, June 2019 Analysis of Various Computer Architectures Kulvinder Singh, Pushpendra Kumar Pateriya, Devinder Kaur, Mritunjay Rai Abstract: With the tremendous acceptance of computers globally in the different fields, there comes the challenge of managing II. ISA instructions, processing, and improving the efficiency of computer systems. Ever since the inception of computers from Instruction Set Architecture (ISA) is a mechanism which earliest ENIAC (developed at the University of Pennsylvania) to governs the interaction of hardware and software. ISA modern supercomputer Sunway TaihuLight (developed at comprises of hardware implemented instructions, defined National Supercomputing Center, China) a broad research along addressing modes, types, and sizes of different operands used with great ideas in the field of computer architecture has laid its as well as registers and input-output control [10]. Broadly way. It has lead to the advances which has made the computers capable to perform computations at lightning speeds. For an speaking, an ISA is a set of operations which defines example, the computing speed of TaihuLight exceeds 93 everything a machine language programmer must be familiar petaflops. It uses 40,960 individual RISC processors to reach such with to be able to program a computer [2]. Every ISA has its high speeds. In this, the architecture plays an indispensable role own set of supported operations and valid instructions format right from accessing memory, allocating instruction to processors which are decoded by the control unit of the processor while for execution, and exploiting the architecture to increase the execution is performed by ALU. The first ISA appears on the efficiency [12]. Moreover, reducing energy consumption and cost IBM System 360 in 1964. computer architecture needs to be highly specific and fast in making decisions. With the passage of time, various ideas have come up to enhance this performance index. In this paper, we III. CLASSIFICATION OF ISA describe most frequently used computer architectures with a Amongst the different possible characteristics, the type of general review and working process which can help the readers to instruction set architecture supported can be the most understand the underlying principles of various computer significant feature. It fundamentally defines how the architectures. computer will be executing the instructions. Although, there Index Terms: Instruction Set Architecture, Load/store exist different approaches for comparing instruction set Architecture, Stack Architecture, Pipelining, NOP architectures, a popular approach is based on the architectural complexity. The restriction of fixed instruction length adds I. INTRODUCTION simplicity, also the number of operations supported by that Before the criticism of David Patterson and John L. particular instruction set get reduced. The architecture Hennessy, computer architecture was entirely referred to the designs which follow similar approach are called Reduced instruction set architecture. While, other features of the Instruction Set Computers (RISC)[4]. architecture were called as the implementation. But, the While, an opposite approach also exists alternative to the criticism shifted the view of the community to accept RISC which makes use of complex instructions. In this, size implementation aspect also in the formal definition of of instructions may vary adding capability of specifying computer architecture. Hence, most general approach defines sophisticated and multi step operations. These architecture computer architecture as the architecture which comprises of designs are called Complex Instruction Set Computers the organization of different components, physical design of (CISC) and were widely used before advent of the RISC in the individual hardware elements, and instruction set architecture 1970s. On the other hand, Very Long Instruction Word [1]. Although, hardware and organization paradigms have got (VLIW) architecture relies on the compiler for rearranging advanced, but still general principles have not changed much the program in advance for exploiting instruction-level in their case. On the other hand, ISA (Instruction Set parallelism. It is contrary to other types discussed above Architecture) has introduced new ways of implementing ideas which uses additional hardware to maximize parallel related to the interface between the hardware and software. execution of instructions [5]. Based on complexity, Through past years various attempts have been made in this instruction sets like Minimal Instruction Set Computer direction. In this paper, we have discussed various standard (MISC) have also been studied which have lesser complexity architectures, ideas, their working, historical perspective, than RISC. challenges, and their significance in present scenario as well Some others are One instruction Set Computer (OISC) as the future scope. and Zero Instruction Set Computer (ZISC) which along with many others are theoretically important for research perspective. But, they have insignificant performance and hence not been commercialized [10]. Several other architectures also exist like Transport Triggered Architecture Revised Manuscript Received on May 22, 2019. (TTA) which deals with data transfer buses to enhance the Kulvinder Singh, Lovely Professional University, Punjab, India. Email: performance with the help of direct buses. [email protected] Pushpendra Kumar Pateriya, Lovely Professional University, Punjab, India. E-mail: [email protected] Devinder Kaur, Lovely Professional University, Punjab, India. E-mail: [email protected] Mritunjay Rai, Lovely Professional University, Punjab, India. E-mail: [email protected] Published By: Blue Eyes Intelligence Engineering Retrieval Number: H11890688S219/19©BEIESP 1113 & Sciences Publication Analysis of Various Computer Architectures A. RISC execution of instruction whereas reducing the efforts in A primary set of operations, a compatible, and scalable programming the problem [11]. design can be used to build a computer which can give The CISC architecture consists of a large number of bits in instruction formats, which specifies the type of operation, the effectively faster results with lower latency. The decoding of number, type and position of the operands etc. Unlike RISC, it the instruction is faster due to the fixed set of addressing doesn’t follow load/store architecture and fetches instruction from modes, while the simplicity of instruction set enhances the memory every time it needs to perform some operation with it, refer execution of most instructions in a single machine cycle. In to Table 1 [6]. Code density, addition, such a machine should have a much shorter design i.e. the memory program takes in memory, is more than in CISC than time [6]. As the name suggests it’s architecture enables usage in RISC [12]. of lesser instruction as compared to CISC, the instructions are TABLE I: RISC VS. CISC [13] precise, simple, and general. Table no. I [7] can be referred to compare these two. RISC strictly follows Load/store Sr no. CISC RISC architecture which means that only load and store instructions have the privilege to access memory. No other instruction can 1. Complex instructions Simple instructions with individually access memory by itself [6]. Since RISC design with variable length fixed length is based on load/store design, it is important to provide a compatible and fast memory methodology to work in sync 2. Dont follow Load/Store Strongly follow design Load/Store design with processor [5]. In a RISC system, the memory methodology comprises of effective use management of 3. Pipelining not efficient Highly efficient with registers and caches to increase performance, and write pipelining buffers. Usually, there is also an on-chip memory management unit [8]. 4. Complex addressing Simple and limited ad- In a RISC design, the capability to predict the approximate modes dressing modes time for processing of the instructions enable pipelines to 5. Focuses on embedding Focuses on execution of work efficiently and faster [9]. The term RISC first appeared large number of one instruction per cycle in a paper by David Patterson of the University of operation on a single California, Berkeley, though similar concepts had appeared processor before [1]. A Similar paradigm of designing microprocessor 6. high number of opcode fixed number of opcodes architecture was discussed by John L. Hennessy of Stanford with variable size with fixed sizes University in 1981, with the name of MIPS project where the emphasis was on a simplified instruction set to get high 7. fetches data or every makes use of principle of performance, which became functioning in 1983, and was time locality for lesser interaction with able to run simple programs by 1984 [10]. Henessey an instruction needs it memory explained that, The RISC architecture is simple both in the 8. limited number of large number of registers instruction set and the hardware needed to implement that registers instruction set. Although the MIPS instruction set has a simple hardware implementation (i.e. it requires a minimal 9. Minimum program Increased program length amount of hardware control), the user level instruction set is length and minimum work on instruction and maximum work on not as straightforward, and the simplicity of the user level instruction instruction
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