Implementation of a Fast Mpeg-2 Compliant Huffman Decoder
Total Page：16
File Type：pdf, Size：1020Kb
IMPLEMENTATION OF A FAST MPEG-2 COMPLIANT HUFFMAN DECODER Mikael Karlsson Rudberg ([email protected]) and Lars Wanhammar ([email protected]) Department of Electrical Engineering, Linköping University, S-581 83 Linköping, Sweden Tel: +46 13 284059; fax: +46 13 139282 ABSTRACT 2. HUFFMAN DECODER In this paper a 100 Mbit/s Huffman decoder Huffman decoding can be performed in a numerous implementation is presented. A novel approach ways. One common principle is to decode the where a parallel decoding of data mixed with a incoming bit stream in parallel [3, 4]. The serial input has been used. The critical path has simplified decoding process is described below: been reduced and a significant increase in throughput is achieved. The decoder is aimed at 1. Feed a symbol decoder and a length the MPEG-2 Video decoding standard and has decoder with M bits, where M is the length therefore been designed to meet the required of the longest code word. performance. 2. The symbol decoder maps the input vector to the corresponding symbol. A length 1. INTRODUCTION decoder will at the same time find the length of the input vector. Huffman coding is a lossless compression 3. The information from the length decoder is technique often used in combination with other used in the input buffer to fill up the buffer lossy compression methods, in for instance digital again (with between one and M bits, figure video and audio applications. The Huffman coding 1). method uses codes with different lengths, where symbols with high probability are assigned shorter The problem with this solution is the long critical codes than symbols with lower probability. The path through the length decoder to the buffer that problem is that since the coded symbols have shifts in new data (figure 1). unequal lengths it is impossible to know the boundaries of the symbols without first decoding them. Therefore it is difficult to parallelize the symbol output symbol decoding process. When dealing with compressed decoder buffer video data this will become a problem since high data rates are necessary. M The architecture of the Huffman decoder presented input shifting bit/cycle in this paper is based on a novel hardware buffer structure [1] that allows high speed decoding. The decoder can handle all Huffman tables critical length length required for decoding MPEG-2 Video at the Main path decoder Stream, Main Level resolutions [2]. The design is completely MPEG-2 adapted with automatic handling of the MPEG-2 specific escape and end of block codes. In total our decoder supports 11 code Figure 1. A constant output rate Huffman tables with more than 600 different code words. decoder. Since the code books are static in the MPEG-2 standard the Huffman decoder has been optimized In our decoder the shifting buffer is realized with a for these specific MPEG-2 codes. A decoding rate of shift register that continuously shifts new data 100 Mbit/s is required and also achieved in our into the decoder (figure 2). The length decoder and implementation. symbol decoder are supplied from registers that are loaded every time a new code word is present at the input. The decoding process is described below: 1. Load the input registers of the length and The new structure require higher clock rate to symbol decoder. perform the same amount of work. But, if the average code length is short enough the new 2. If the coded data has a length of one go structure will have a higher speed due to the back to point 1. significantly higher clock rates that can be achieved. Normally the shorter code words will 3. If the coded data has a length of two go dominate in Huffman coded data and therefore the back to point 1. new decoder is faster during normal circumstances. and so on with codes of length three and four up to M. 2.1 Handling of special markers input shift register D Special markers are placed in the data stream to indicate for example end of block (eob) at the end of load a coded block of data. After this marker other M bits registers types of data like uncompressed stream load register M-1 bits symbol information will follow (figure 3). In the Huffman length decoder decoder decoder it is essential to detect the presence of this logic length=2? logic marker to be able to stop the decoding process and let other units process the data that will follow. length=M? length=1? This decoder detects the eob marker in the length select output buffer decoder and halts the decoding process until a new force load start signal is applied. length >1 symbol Huffman codes eob header data Huffman codes length decoder symbol decoder Huffman codes mb_escape fix length data Huffman codes Figure 2. Huffman decoder with relaxed length evaluation time. t Figure 3. Markers in the MPEG-2 stream This structure allows longer evaluation times for requiring special decoding. longer code words. The delay in the critical path is reduced to the time it takes for evaluating the The mb_escape marker is also important. After length of code words with a length of one or two this symbol the following data is of fix length. Also bits. Codes with other lengths are allowed to be this marker is detected in the length decoder and evaluated in several cycles, i.e. code words with results in that the following data is passed lengths of three must be evaluated in two cycles through the symbol decoder unchanged (figure 3). and so on. Comparing this algorithm with the previous one we note the following: 3. IMPLEMENTATION • The input rate of our new structure is The MPEG-2 standard requires that the input constant while the original has a variable data must be decoded at a rate of about 100 input rate. Mbit/s. During the implementation special care had to be taken during the partitioning of the • The new structure evaluates short code symbol decoder and a few critical paths had to be words in a few cycles but requires more optimized manually. A few modifications of the cycles for longer words. The original new decoding algorithm had to be made to make it structure has a constant evaluation time possible to achieve the targeted performance. for all code words. 3.1 Improvements of the length • The new structure allow higher clock rate decoder since the critical path is reduced. But this also means that the symbol decoder must The length decoder turned out to be to slow when be faster since it in the worst case will evaluating codes with lengths of one or two bits receive new data every clock cycle. ('length = 1?' and 'length = 2?' in figure 2). These paths had to be broken up. How this was done is • The new structure has a variable output rate while the original one has a constant shown in figure 4 below. The evaluation of the output rate. 'length = 1?' signal is done by taking data one step earlier (i.e. from position i—1 instead of i) from the applied. The decoded data is delivered with a shift register and add a flip flop after the maximum of 50 Msymbol/s. The 'symbol present' evaluation. For the 'length = 2?' signal the register signal (figure 5) indicates when data is valid at was moved to after the evaluation logic. the output. i-2 i-1 i i-2 i-1 i The shift register at the input of the decoder D D D D D D (figure 2) can be read and controlled externally. This is necessary since the Huffman coded data is load load D D interleaved with other information. logic logic logic logic load D D register register register register register load length=2? length=1? length=2? length=1? decoder decoder decoder decoder decoder D Before optimization After optimization unit 1 unit 2 unit 3 unit 4 unit 5 D Figure 4. Optimization of critical paths in the length decoder. register register register register register Note that this way of breaking up the critical loops can be generalized to removing all critical loops in current table D this structure, see [1]. D 3.2 Symbol Decoder post processing D The symbol decoding task is more complicated register D than the length decoding. The symbol decoder could not be designed to receive data in 100 >1 Mbit/s. Code words with a length of one bit are symbol symbol present rare in MPEG coded data. The most frequent used code tables do only contain codes with more than Figure 5. Realization of symbol decoder. two bits. Therefore the symbol decoder is fed with data no more often than every second clock cycle. 3.4 Synthesis The input shift register is halted one clock period every time a one bit code is found, and hence, the The decoder has been described in VHDL and then symbol decoder only need to process 50 Mbit/s transformed to a circuit using synthesis tools without a significance loss in performance. mapping to an 0.8 µm CMOS standard cell However, this modification causes the input rate to library. Some post processing had to be done after vary. the synthesis step to achieve the necessary performance. The main problem was to get the The symbol decoder were split into five separate symbol decoder to work fast enough. Therefore the units that takes care of their own part of the code symbol decoding has been split into five separate tables (figure 5). Every unit consists of an input units.