DOCSLIB.ORG

Rethinking Code Generation in Compilers

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Rethinking Code Generation in Compilers Rethinking Code Generation in Compilers Christian Schulte SCALE KTH Royal Institute of Technology & SICS (Swedish Institute of Computer Science) joint work with: Mats Carlsson SICS Roberto Castañeda Lozano SICS + KTH Frej Drejhammar SICS Gabriel Hjort Blindell KTH funded by: Ericsson, Vetenskapsrådet Compilation source front-end optimizer back-end assembly program (code generator) program Oct Oct 1, 2014 • Front-end: depends on source programming language • changes infrequently SCALE Schulte, • Optimizer: independent optimizations • changes infrequently CodeGeneration Rethinking • Back-end: depends on processor architecture 2 • changes often: new architectures, new features, … Building a Compiler source front-end optimizer back-end assembly program (code generator) program Oct Oct 1, 2014 LLVM Schulte, SCALE Schulte, Infrequent changes: front-end & optimizer • CodeGeneration Rethinking • reuse state-of-the-art: LLVM, for example 3 Building a Compiler source front-end optimizer back-end assembly program (code generator) program Oct Oct 1, 2014 Unison Schulte, SCALE Schulte, Infrequent changes: front-end & optimizer • CodeGeneration Rethinking • reuse state-of-the-art: LLVM, for example • Frequent changes: back-end • use flexible approach: Unison (project this talk is based on) 4 State-of-the-art instruction selection Oct Oct 1, 2014 add r0 r1 r2 x = y + z; mv $a6f0 r0 Schulte, SCALE Schulte, • Code generation organized into stages • instruction selection, CodeGeneration Rethinking 5 State-of-the-art register allocation Oct Oct 1, 2014 x register r0 x = y + z; y memory (spill to stack) … Schulte, SCALE Schulte, • Code generation organized into stages • instruction selection, register allocation, CodeGeneration Rethinking 6 State-of-the-art instruction scheduling Oct Oct 1, 2014 x = y + z; u = v – w; … … u = v – w; x = y + z; Schulte, SCALE Schulte, • Code generation organized into stages • instruction selection, register allocation, instruction scheduling CodeGeneration Rethinking 7 State-of-the-art instruction register instruction selection allocation scheduling Oct Oct 1, 2014 • Code generation organized into stages • stages are interdependent: no optimal order possible Schulte, SCALE Schulte, Rethinking Code Generation CodeGeneration Rethinking 8 State-of-the-art instruction instruction register selection scheduling allocation Oct Oct 1, 2014 • Code generation organized into stages • stages are interdependent: no optimal order possible SCALE Schulte, • Example: instruction scheduling register allocation • increased delay between instructions can increase throughput Rethinking Code Generation CodeGeneration Rethinking registers used over longer time-spans more registers needed 9 State-of-the-art instruction register instruction selection allocation scheduling Oct Oct 1, 2014 • Code generation organized into stages • stages are interdependent: no optimal order possible SCALE Schulte, • Example: instruction scheduling register allocation • put variables into fewer registers Rethinking Code Generation CodeGeneration Rethinking more dependencies among instructions less opportunity for reordering instructions 10 State-of-the-art instruction instruction register selection scheduling allocation Oct Oct 1, 2014 • Code generation organized into stages • stages are interdependent: no optimal order possible SCALE Schulte, • Stages use heuristic algorithms • for hard combinatorial problems (NP hard) Rethinking Code Generation CodeGeneration Rethinking • assumption: optimal solutions not possible anyway • difficult to take advantage of processor features • error-prone when adapting to change 11 State-of-the-art instruction instruction register selection scheduling allocation Oct Oct 1, 2014 • Code generation organized into stages • stages are interdependent: no optimal order possible SCALE Schulte, • Stages use heuristic algorithms • for hard combinatorial problemspreclude (NP hard) optimal code, Rethinking Code Generation CodeGeneration Rethinking • assumption: optimal solutions makenot possible development anyway • difficult to take advantage of processorcomplex features • error-prone when adapting to change 12 Rethinking: Unison Idea • No more staging and heuristic algorithms! • many assumptions are decades old... • Use state-of-the-art technology for solving combinatorial Oct 1, 2014 optimization problems: constraint programming • tremendous progress in last two decades... SCALE Schulte, • Generate and solve single model • captures all code generation tasks in unison Rethinking Code Generation CodeGeneration Rethinking • high-level of abstraction: based on processor description • flexible: ideally, just change processor description • potentially optimal: tradeoff between decisions accurately reflected 13 Unison Approach instruction selection constraint model constraints input instruction constraints program scheduling constraints Oct 1, 2014 register allocation Schulte, SCALE Schulte, processor description • Generate constraint model CodeGeneration Rethinking • based on input program and processor description • constraints for all code generation tasks • generate but not solve: simpler and more expressive 14 Unison Approach instruction selection constraint model constraints off-the-shelf input instruction constraint constraints program scheduling solver constraints Oct 1, 2014 register allocation assembly program Schulte, SCALE Schulte, processor description • Off-the-shelf constraint solver solves constraint model CodeGeneration Rethinking • solution is assembly program • optimization takes inter-dependencies into account 15 Overview • Constraint programming in a nutshell • Approach Oct 1, 2014 • Results Schulte, SCALE Schulte, • Discussion Rethinking Code Generation CodeGeneration Rethinking 16 Oct Oct 1, 2014 Schulte, SCALE Schulte, Rethinking Code Generation CodeGeneration Rethinking CONSTRAINT PROGRAMMING 17 IN A NUTSHELL Constraint Programming • Model and solve combinatorial (optimization) problems • Modeling • variables Oct 1, 2014 • constraints • branching heuristics • (cost function) SCALE Schulte, • Solving • constraint propagation Rethinking Code Generation CodeGeneration Rethinking • heuristic search • Of course simplified… 18 • array of modeling techniques Problem: Send More Money • Find distinct digits for letters such that SEND Oct 1, 2014 + MORE Schulte, SCALE Schulte, = MONEY Rethinking Code Generation CodeGeneration Rethinking 19 Constraint Model • Variables: S,E,N,D,M,O,R,Y {0,…,9} • Constraints: Oct 1, 2014 distinct(S,E,N,D,M,O,R,Y) 1000×S+100×E+10×N+D SCALE Schulte, + 1000×M+100×O+10×R+E = 10000×M+1000×O+100×N+10×E+Y CodeGeneration Rethinking S0 M0 20 Constraints • State relations between variables • legal combinations of values for variables • Examples Oct 1, 2014 • all variables pair wise distinct: distinct(x1, …, xn) • arithmetic constraints: x + 2×y = z • domain-specific: cumulative(t , …, t ) 1 n SCALE Schulte, nooverlap(r1, …, rn) Rethinking Code Generation CodeGeneration Rethinking • Success story: global constraints • modeling: capture recurring problem structures • solving: enable strong reasoning 21 constraint-specific methods Solving: Variables and Values Oct Oct 1, 2014 x{1,2,3,4} y{1,2,3,4} z{1,2,3,4} Schulte, SCALE Schulte, Rethinking Code Generation CodeGeneration Rethinking • Record possible values for variables • solution: single value left • failure: no values left 22 Constraint Propagation distinct(x, y, z) x + y = 3 Oct 1, 2014 x{1,2,3,4} y{1,2,3,4} z{1,2,3,4} Schulte, SCALE Schulte, Rethinking Code Generation CodeGeneration Rethinking • Prune values that are in conflict with constraint 23 Constraint Propagation distinct(x, y, z) x + y = 3 Oct 1, 2014 x{1,2} y{1,2} z{1,2,3,4} Schulte, SCALE Schulte, Rethinking Code Generation CodeGeneration Rethinking • Prune values that are in conflict with constraint 24 Constraint Propagation distinct(x, y, z) x + y = 3 Oct 1, 2014 x{1,2} y{1,2} z{3,4} Schulte, SCALE Schulte, Rethinking Code Generation CodeGeneration Rethinking • Prune values that are in conflict with constraint • propagation is often smart if not perfect! • captured by so-called global constraints 25 Heuristic Search distinct(x, y, z) x + y = 3 x=1 x{1,2} y{1,2} z{3,4} x≠1 distinct(x, y, z) x + y = 3 distinct(x, y, z) x + y = 3 Oct 1, 2014 x{1} y{2} z{3,4} x{2} y{1} z{3,4} Schulte, SCALE Schulte, • Propagation alone not sufficient decompose into simpler sub-problems • CodeGeneration Rethinking • search needed • Create subproblems with additional constraints • enables further propagation • defines search tree 26 • uses problem specific heuristic What Makes It Work? • Essential: avoid search... ...as it always suffers from combinatorial explosion • Constraint propagation drastically reduces search space Oct 1, 2014 • Efficient and powerful methods for propagation available SCALE Schulte, • When using search, use a clever heuristic Rethinking Code Generation CodeGeneration Rethinking • Array of modeling techniques available that reduce search • adding redundant constraints for more propagation, symmetry breaking, ... 27 • Hybrid methods (together with LP, SAT, stochastic, ...) Approach Source Material • Survey on Combinatorial Register Allocation and Instruction Scheduling • Roberto Castañeda Lozano, Christian Schulte. CoRR entry, 2014. • Combinatorial Spill Code Optimization and Ultimate Oct 1, 2014 Coalescing • Roberto Castañeda Lozano, Mats Carlsson, Gabriel Hjort Blindell, Christian Schulte. Languages, Compilers, Tools and Theory for Embedded Systems, 2014. SCALE Schulte, •
Load more

Recommended publications
  • Resourceable, Retargetable, Modular Instruction Selection Using a Machine-Independent, Type-Based Tiling of Low-Level Intermediate Code
    Reprinted from Proceedings of the 2011 ACM Symposium on Principles of Programming Languages (POPL’11) Resourceable, Retargetable, Modular Instruction Selection Using a Machine-Independent, Type-Based Tiling of Low-Level Intermediate Code Norman Ramsey Joao˜ Dias Department of Computer Science, Tufts University Department of Computer Science, Tufts University [email protected] [email protected] Abstract Our compiler infrastructure is built on C--, an abstraction that encapsulates an optimizing code generator so it can be reused We present a novel variation on the standard technique of selecting with multiple source languages and multiple target machines (Pey- instructions by tiling an intermediate-code tree. Typical compilers ton Jones, Ramsey, and Reig 1999; Ramsey and Peyton Jones use a different set of tiles for every target machine. By analyzing a 2000). C-- accommodates multiple source languages by providing formal model of machine-level computation, we have developed a two main interfaces: the C-- language is a machine-independent, single set of tiles that is machine-independent while retaining the language-independent target language for front ends; the C-- run- expressive power of machine code. Using this tileset, we reduce the time interface is an API which gives the run-time system access to number of tilers required from one per machine to one per archi- the states of suspended computations. tectural family (e.g., register architecture or stack architecture). Be- cause the tiler is the part of the instruction selector that is most dif- C-- is not a universal intermediate language (Conway 1958) or ficult to reason about, our technique makes it possible to retarget an a “write-once, run-anywhere” intermediate language encapsulating instruction selector with significantly less effort than standard tech- a rigidly defined compiler and run-time system (Lindholm and niques.
    [Show full text]
  • CS415 Compilers Register Allocation and Introduction to Instruction Scheduling
    CS415 Compilers Register Allocation and Introduction to Instruction Scheduling These slides are based on slides copyrighted by Keith Cooper, Ken Kennedy & Linda Torczon at Rice University Announcement • First homework out → Due tomorrow 11:59pm EST. → Sakai submission window open. → pdf format only. • Late policy → 20% penalty for first 24 hours late. → Not accepted 24 hours after deadline. If you have personal overriding reasons that prevents you from submitting homework online, please let me know in advance. cs415, spring 16 2 Lecture 3 Review: ILOC Register allocation on basic blocks in “ILOC” (local register allocation) • Pseudo-code for a simple, abstracted RISC machine → generated by the instruction selection process • Simple, compact data structures • Here: we only use a small subset of ILOC → ILOC simulator at ~zhang/cs415_2016/ILOC_Simulator on ilab cluster Naïve Representation: Quadruples: loadI 2 r1 • table of k x 4 small integers loadAI r0 @y r2 • simple record structure add r1 r2 r3 • easy to reorder loadAI r0 @x r4 • all names are explicit sub r4 r3 r5 ILOC is described in Appendix A of EAC cs415, spring 16 3 Lecture 3 Review: F – Set of Feasible Registers Allocator may need to reserve registers to ensure feasibility • Must be able to compute addresses Notation: • Requires some minimal set of registers, F k is the number of → F depends on target architecture registers on the • F contains registers to make spilling work target machine (set F registers “aside”, i.e., not available for register assignment) cs415, spring 16 4 Lecture 3 Live Range of a Value (Virtual Register) A value is live between its definition and its uses • Find definitions (x ← …) and uses (y ← … x ...) • From definition to last use is its live range → How does a second definition affect this? • Can represent live range as an interval [i,j] (in block) → live on exit Let MAXLIVE be the maximum, over each instruction i in the block, of the number of values (pseudo-registers) live at i.
    [Show full text]
  • MAO - an Extensible Micro-Architectural Optimizer
    MAO - an Extensible Micro-Architectural Optimizer Robert Hundt, Easwaran Raman, Martin Thuresson, Neil Vachharajani Google 1600 Amphitheatre Parkway Mountain View, CA, 94043 frhundt, eraman, [email protected], [email protected] .L3 movsbl 1(%rdi,%r8,4),%edx Abstract—Performance matters, and so does repeatability and movsbl (%rdi,%r8,4),%eax predictability. Today’s processors’ micro-architectures have be- # ... 6 instructions come so complex as to now contain many undocumented, not movl %edx, (%rsi,%r8,4) understood, and even puzzling performance cliffs. Small changes addq $1, %r8 in the instruction stream, such as the insertion of a single NOP instruction, can lead to significant performance deltas, with the nop # this instruction speeds up effect of exposing compiler and performance optimization efforts # the loop by 5% to perceived unwanted randomness. .L5: movsbl 1(%rdi,%r8,4),%edx This paper presents MAO, an extensible micro-architectural movsbl (%rdi,%r8,4),%eax assembly to assembly optimizer, which seeks to address this # ... identical code sequence problem for x86/64 processors. In essence, MAO is a thin wrapper movl %edx, (%rsi,%r8,4) around a common open source assembler infrastructure. It offers addq $1, %r8 basic operations, such as creation or modification of instructions, cmpl %r8d, %r9d simple data-flow analysis, and advanced infra-structure, such jg .L3 as loop recognition, and a repeated relaxation algorithm to compute instruction addresses and lengths. This infrastructure Fig. 1. Code snippet with high impact NOP instruction enables a plethora of passes for pattern matching, alignment specific optimizations, peep-holes, experiments (such as random insertion of NOPs), and fast prototyping of more sophisticated optimizations.
    [Show full text]
  • Lecture Notes on Instruction Selection
    Lecture Notes on Instruction Selection 15-411: Compiler Design Frank Pfenning Lecture 2 August 28, 2014 1 Introduction In this lecture we discuss the process of instruction selection, which typcially turns some form of intermediate code into a pseudo-assembly language in which we assume to have infinitely many registers called “temps”. We next apply register allocation to the result to assign machine registers and stack slots to the temps be- fore emitting the actual assembly code. Additional material regarding instruction selection can be found in the textbook [App98, Chapter 9]. 2 A Simple Source Language We use a very simple source language where a program is just a sequence of assign- ments terminated by a return statement. The right-hand side of each assignment is a simple arithmetic expression. Later in the course we describe how the input text is parsed and translated into some intermediate form. Here we assume we have arrived at an intermediate representation where expressions are still in the form of trees and we have to generate instructions in pseudo-assembly. We call this form IR Trees (for “Intermediate Representation Trees”). We describe the possible IR trees in a kind of pseudo-grammar, which should not be read as a description of the concrete syntax, but the recursive structure of the data. LECTURE NOTES AUGUST 28, 2014 Instruction Selection L2.2 Programs ~s ::= s1; : : : ; sn sequence of statements Statements s ::= x = e assignment j return e return, always last Expressions e ::= c integer constant j x variable j e1 ⊕ e2 binary operation Binops ⊕ ::= + j − j ∗ j = j ::: 3 Abstract Assembly Target Code For our very simple source, we use an equally simple target.
    [Show full text]
  • Synthesizing an Instruction Selection Rule Library from Semantic Specifications
    Synthesizing an Instruction Selection Rule Library from Semantic Specifications Sebastian Buchwald Andreas Fried Sebastian Hack Karlsruhe Institute of Technology Karlsruhe Institute of Technology Saarland University Germany Germany Germany [email protected] [email protected] [email protected] Abstract 1 Introduction Instruction selection is the part of a compiler that transforms Modern instruction set architectures (ISAs), even those of intermediate representation (IR) code into machine code. RISC processors, are complex and comprise several hundred Instruction selectors build on a library of hundreds if not instructions. In recent years, ISAs have been more frequently thousands of rules. Creating and maintaining these rules is extended to accelerate computations of various domains (e.g., a tedious and error-prone manual process. signal processing, graphics, string processing, etc.). In this paper, we present a fully automatic approach to Instruction selectors typically use a library of rules to create provably correct rule libraries from formal specifica- transform the program: Each rule associates a pattern of IR tions of the instruction set architecture and the compiler operations to a semantically equivalent, small program of IR. We use a hybrid approach that combines enumerative machine instructions. First, the selector matches the pattern techniques with template-based counterexample-guided in- of each rule in the library to the IR of the program to be ductive synthesis (CEGIS). Thereby, we overcome several compiled. Then, the selector computes a pattern cover of the shortcomings of existing approaches, which were not able program and rewrites it according to the rules associated to handle complex instructions in a reasonable amount of with the patterns.
    [Show full text]
  • Machine Independent Code Optimizations
    Machine Independent Code Optimizations Useless Code and Redundant Expression Elimination cs5363 1 Code Optimization Source IR IR Target Front end optimizer Back end program (Mid end) program compiler The goal of code optimization is to Discover program run-time behavior at compile time Use the information to improve generated code Speed up runtime execution of compiled code Reduce the size of compiled code Correctness (safety) Optimizations must preserve the meaning of the input code Profitability Optimizations must improve code quality cs5363 2 Applying Optimizations Most optimizations are separated into two phases Program analysis: discover opportunity and prove safety Program transformation: rewrite code to improve quality The input code may benefit from many optimizations Every optimization acts as a filtering pass that translate one IR into another IR for further optimization Compilers Select a set of optimizations to implement Decide orders of applying implemented optimizations The safety of optimizations depends on results of program analysis Optimizations often interact with each other and need to be combined in specific ways Some optimizations may need to applied multiple times . E.g., dead code elimination, redundancy elimination, copy folding Implement predetermined passes of optimizations cs5363 3 Scalar Compiler Optimizations Machine independent optimizations Enable other transformations Procedure inlining, cloning, loop unrolling Eliminate redundancy Redundant expression elimination Eliminate useless
    [Show full text]
  • Optimizations for Intel's 32-Bit Processors Version 2.2
    Optimizations for Intel's 32-Bit Processors Version 2.2 Optimizations for Intel's 32-Bit Processors Version 2.2 April 11, 1995 The following are trademarks of Intel Corporation and may only be used to identify Intel products: Intel, Intel386, Intel486, i486, and Pentium ©1995, Intel Corporation Page 1 Intel Confidential Optimizations for Intel's 32-Bit Processors Version 2.2 Table of Contents 1. INTRODUCTION ............................................................................................................................................4 2. OVERVIEW OF INTEL386, INTEL486, PENTIUM AND P6 PROCESSORS ...........................................4 2.1 THE INTEL386 PROCESSOR ................................................................................................................................4 2.1.1. INSTRUCTION PREFETCHER ................................................................................................................4 2.1.2. INSTRUCTION DECODER ......................................................................................................................4 2.1.3. EXECUTION CORE .................................................................................................................................4 2.2 THE INTEL486 PROCESSOR ................................................................................................................................5 2.2.1. INTEGER PIPELINE................................................................................................................................5
    [Show full text]
  • Instruction Selection
    Instruction selection Simple approach: • Macro-expand each IR tuple/subtree into machine instructions • Expanding tuples/subtrees independently ⇒ poor quality code • Sometimes mapping is many-to-one • “Maximal munch”: works reasonably well with RISC Other approaches: • Model target machine state as IR is expanded (interpretive code generation) Copyright c 2010 by Antony L. Hosking. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and full citation on the first page. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or fee. Request permission to publish from [email protected]. 1 Register and temporary management Temporaries hold data values relevant to current computation: • Usually registers • May be in-memory storage temporaries in local stack frame Register allocation: assign registers to temporaries • Limited number of hard registers ⇒ some temporaries may need to be allocated to storage – assume a pseudo-register for each temporary – register allocator chooses temporaries to spill – allocator generates corresponding mapping – allocator inserts code to spill/restore pseudo-registers to/from storage as necessary We will deal with register allocation after instruction selection 2 Tree patterns • Express each machine instruction as fragment of IR tree: a tree pattern • Instruction
    [Show full text]
  • Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
    IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, VOL. 28, NO. 9, SEPTEMBER 2002 847 Reconfigurable Instruction Set Processors from a Hardware/Software Perspective Francisco Barat, Student Member, IEEE, Rudy Lauwereins, Senior Member, IEEE, and Geert Deconinck, Senior Member, IEEE Abstract—This paper presents the design alternatives for reconfigurable instruction set processors (RISP) from a hardware/software point of view. Reconfigurable instruction set processors are programmable processors that contain reconfigurable logic in one or more of its functional units. Hardware design of such a type of processors can be split in two main tasks: the design of the reconfigurable logic and the design of the interfacing mechanisms of this logic to the rest of the processor. Among the most important design parameters are: the granularity of the reconfigurable logic, the structure of the configuration memory, the instruction encoding format, and the type of instructions supported. On the software side, code generation tools require new techniques to cope with the reconfigurability of the processor. Aside from traditional techniques, code generation requires the creation and evaluation of new reconfigurable instructions and the selection of instructions to minimize reconfiguration time. The most important design alternative on the software side is the degree of automatization present in the code generation tools. Index Terms—Reconfigurable instruction set processor overview, reconfigurable logic, microprocessor, compiler. æ 1INTRODUCTION MBEDDED systems today are composed of many hard- components interacting very closely. Traditional program- Eware and software components interacting with each mable processors do not have this type of interaction due to other. The balance between these components will deter- the generic nature of the processors.
    [Show full text]
  • Efficient Selection of Vector Instructions Using Dynamic Programming
    Efficient Selection of Vector Instructions using Dynamic Programming Rajkishore Barik, Jisheng Zhao, Vivek Sarkar Rice University, Houston, Texas E-mail: {rajbarik, jz10, vsarkar}@rice.edu Abstract: Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scientific, and embedded applications. To take full advantage of the vector capabilities, a compiler needs to generate efficient vector code automatically. However, most commercial and open-source compilers fall short of using the full potential of vector units, and only generate vector code for simple innermost loops. In this paper, we present the design and implementation of an auto-vectorization framework in the back- end of a dynamic compiler that not only generates optimized vector code but is also well integrated with the instruction scheduler and register allocator. The framework includes a novel compile-time efficient dynamic programming-based vector instruction selection algorithm for straight-line code that expands opportunities for vectorization in the following ways: (1) scalar packing explores opportunities of packing multiple scalar variables into short vectors; (2) judicious use of shuffle and horizontal vector operations, when possible; and (3) algebraic reassociation expands opportunities for vectorization by algebraic simplification. We report performance results on the impact of auto-vectorization on a set of standard numerical benchmarks using the Jikes RVM dynamic compilation environment. Our results show performance improvement of up to 57.71% on an Intel Xeon processor, compared to non-vectorized execution, with a modest increase in compile- time in the range from 0.87% to 9.992%.
    [Show full text]
  • Instruction Selection for the CACAO VM
    Die approbierte Originalversion dieser Diplom-/ Masterarbeit ist in der Hauptbibliothek der Tech- nischen Universität Wien aufgestellt und zugänglich. http://www.ub.tuwien.ac.at The approved original version of this diploma or master thesis is available at the main library of the Vienna University of Technology. http://www.ub.tuwien.ac.at/eng Instruction Selection for the CACAO VM MASTERARBEIT zur Erlangung des akademischen Grades Master of Science im Rahmen des Studiums Software Engineering & Internet Computing eingereicht von Christian Kühmayer BSc Matrikelnummer 0828301 an der Fakultät für Informatik der Technischen Universität Wien Betreuung: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Andreas Krall Wien, 14. April 2015 Christian Kühmayer Andreas Krall Technische Universität Wien A-1040 Wien Karlsplatz 13 Tel. +43-1-58801-0 www.tuwien.ac.at Instruction Selection for the CACAO VM MASTER’S THESIS submitted in partial fulfillment of the requirements for the degree of Master of Science in Software Engineering & Internet Computing by Christian Kühmayer BSc Registration Number 0828301 to the Faculty of Informatics at the Vienna University of Technology Advisor: Ao.Univ.Prof. Dipl.-Ing. Dr.techn. Andreas Krall Vienna, 14th April, 2015 Christian Kühmayer Andreas Krall Technische Universität Wien A-1040 Wien Karlsplatz 13 Tel. +43-1-58801-0 www.tuwien.ac.at Erklärung zur Verfassung der Arbeit Christian Kühmayer BSc Steinackergasse 20/5, 1120 Wien Hiermit erkläre ich, dass ich diese Arbeit selbständig verfasst habe, dass ich die verwen- deten Quellen und Hilfsmittel vollständig angegeben habe und dass ich die Stellen der Arbeit – einschließlich Tabellen, Karten und Abbildungen –, die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe.
    [Show full text]
  • Survey on Combinatorial Register Allocation and Instruction Scheduling ACM Computing Surveys
    http://www.diva-portal.org Postprint This is the accepted version of a paper published in ACM Computing Surveys. This paper has been peer-reviewed but does not include the final publisher proof-corrections or journal pagination. Citation for the original published paper (version of record): Castañeda Lozano, R., Schulte, C. (2018) Survey on Combinatorial Register Allocation and Instruction Scheduling ACM Computing Surveys Access to the published version may require subscription. N.B. When citing this work, cite the original published paper. Permanent link to this version: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-232189 Survey on Combinatorial Register Allocation and Instruction Scheduling ROBERTO CASTAÑEDA LOZANO, RISE SICS, Sweden and KTH Royal Institute of Technology, Sweden CHRISTIAN SCHULTE, KTH Royal Institute of Technology, Sweden and RISE SICS, Sweden Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the last three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This paper provides an exhaustive literature review and a classification of combinatorial optimization ap- proaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization.
    [Show full text]