DOCSLIB.ORG

Parallex: a Study of a New Parallel Computation Model

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Parallex: a Study of a New Parallel Computation Model ParalleX: A Study of A New Parallel Computation Model Guang R. Gao1, Thomas Sterling2,3,RickStevens4, Mark Hereld4, and Weirong Zhu1 1 2 Department of Electrical and Computer Engineering Center for Advanced Computing Research University of Delaware California Institute of Technology {ggao,weirong}@capsl.udel.edu [email protected] 3 4 Department of Computer Science Mathematics and Computer Science Division Louisiana State University Argonne National Laboratory [email protected] {stevens,hereld}@mcs.anl.gov Abstract more commonly the “message passing model” represented by various implementations of MPI (e.g. MPICH-2, Open- This paper proposes the study of a new computation MPI) adopted because of its applicability to microprocessor model that attempts to address the underlying sources of based MPPs and commodity clusters. Other models used performance degradation (e.g. latency, overhead, and star- are multiple threads (e.g. OpenMP), vector, and SIMD, but vation) and the difficulties of programmer productivity (e.g. message passing is dominant. However, as semiconductor explicit locality management and scheduling, performance technology has continued to evolve, both new opportunities tuning, fragmented memory, and synchronous global barri- and new challenges have emerged demanding correspond- ers) to dramatically enhance the broad effectiveness of par- ing improvements to architecture. Most pronounced is the allel processing for high end computing. In this paper, we move to multicore components and the re-emergence of het- present the progress of our research on a parallel program- erogeneous computing elements such as GPUs and Clear- ming and execution model - mainly, ParalleX. We describe speed SIMD [2] attached processors. The IBM Cell ar- the functional elements of ParalleX, one such model being chitecture embodies both heterogeneous and multicore el- explored as part of this project. We also report our progress ements [6]. These exemplify but do not fully reflect the on the development and study of a subset of ParalleX - the increasing need for new programming methods and archi- LITL-X at University of Delaware. We then present a novel tecture structures to continue to fully benefit from Moore’s architecture model - Gilgamesh II - as a ParalleX process- Law. An important objective of this research project has ing architecture. A design point study of Gilgamesh II and been the exploration and development of a possible new ex- the architecture concept strategy are presented. ecution model that will more readily employ the potential capabilities of near term semiconductor technologies while easing the programmer burden. Such an execution model 1 Introduction could lead to new programming models and languages, new parallel computer architecture, and new supporting system software. Historically as technology has advanced, computer ar- chitecture has changed to exploit the new opportunities In this paper, we present the progress of our research offered and to compensate for the exposed weaknesses. on a parallel programming and execution model - mainly, Alternative strategies for organizing the computation as ParalleX. We describes the functional elements of ParalleX, well as the architectural structures and system software one such model being explored as part of this project. Par- have been devised to provide governing semantic principles alleX principal elements are discussed, including locality, upon which such architecture and programming models are global name space, multithreading, parcels, local control based. For more than a decade, the dominant model of com- objects, percolation, echo, and parallel processes. We also putation has been the communication sequential process or report our progress on the development and study of a sub- set of ParalleX - the LITL-X at University of Delaware. We 1-4244-0910-1/07/$20.00 c 2007 IEEE. then present a novel architecture model - Gilgamesh II - as a ParalleX processing architecture. A design point study the size of the large scale machines. While these would ap- of Gilgamesh II is presented and the architecture concept pear to be properties of the bulk hardware, the manner of strategy is presented. its use is dictated by the execution model and therefore for a given sustained performance can be significantly affected 2 Parallel Programming Execution Model: by it. A new computational model is also needed to move towards a new balance of resources. To devise structures ParalleX and LITL-X and coordinate computing around the realistic precepts de- mands a model of computing quite distinct from those con- This section discusses the specific requirements for a ventionally employed by the mainstream today. This will new execution model and describes the functional elements enable the exploitation of the true performance opportu- of ParalleX, one such model being explored by Sterling’s nities yielded by technology and support architecture ad- group at LSU as part of this project. We also describe LITL- vances. X a subset of ParalleX that is being developed and studied The following are considered essential characteristics of at Gao’s group at Delaware. a future model of computation: • System wide global name spaces both for data and ac- 2.1 Requirements for a New Model of tive tasks with efficient address translation and com- Computation munication routing in the presence of dynamic object distribution, A new model of computation is required to meet the • Rich parallelism semantics and granularity to exploit challenges of emerging technologies. Such a model must a diversity of forms to make available the million to serve as a discipline to govern future scalable system archi- billion way parallelism that will be required of near tectures, programming methods, and runtime and operating nanoscale systems by the end of the next decade, system software. Among its most important requirements is to address the dominant factors impeding significant im- • Direct support for lightweight processing of irregular provements to efficiency. Among these are latency, over- time-varying sparse data structure parallelism such as head, starvation, resource contention, and programmability. that for trees (N-body codes), directed graphs (adaptive Latency is the time delay, measured in processor clock cy- mesh refinement, semantic nets), and particle in cell cles required to access remote data or services such as local (magneto hydro dynamics), main memory or remote nodes. Overhead is the critical path • Intrinsic mechanisms for automatic latency hiding, to work required to manage parallel physical resources and mitigate this major source of performance degradation concurrent abstract tasks. Overhead can determine the scal- duetoblockingoncompletionofremoteactionsand ability of a system and the minimum granularity of program the ensuing idle times experienced, tasks that can be effectively exploited. Starvation is the lack of work and therefore the idle cycles experienced by an ex- • Incorporation of low overhead mechanisms for manag- ecution site (e.g. processor core) caused either due to inad- ing global system parallelism including synchroniza- equate program parallelism or due to poor load balancing. tion, scheduling, data movement, and load balancing, Contention for shared resources causes delays while one re- and questing execution site is blocked by another accessing the • Affinity semantics to establish relationships that would same needed resource. These can include shared communi- lead to locality opportunities through both compile cation channels, common memory banks, or other mutually time and runtime techniques. accessible resource. Programmability relates to program- mer productivity. Systems that require direct and explicit Addressing these challenges through new strategies and resource management by the programmer to achieve opti- structures of computation would remove the reliance on mized performance can be much more difficult to use than manual, pains taking, and error prone direct user interven- those machines with mechanisms more naturally suited to tion including direct control of hardware mechanisms, di- effectively exploit the function elements thus reducing pro- rect management and allocation of hardware resources, and grammer intervention. All of these efficiency factors can direct choreographing of physical data and task locality. As benefit from improved programming models and parallel a consequence, efficiency and performance scaling could be architecture requiring a model of computation that incorpo- dramatically higher, systems smaller and lower power, and rates the means and facilitates the methods to make effective programming dramatically easier. Towards this end, Par- use of the critical resources. alleX is being devised to provide an alternative framework Other demands on the execution model include such from conventional methods and currently addresses many practical concerns as power consumption, reliability, and (but not all) of these requirements. 2 2.2 Principal Elements of ParalleX puting, ParalleX recognizes a local physical domain. In the case of ParalleX, it is the locus of resources An execution model is neither a programming model (al- that can be guaranteed to operate synchronously and though it influences it) nor a virtual machine (although it is for which hardware can guarantee compound atomic often treated as such) but rather a set of guiding principles operations on local data elements. While a typical ex- that organize the computation and govern the relationships
Load more

Recommended publications
  • CS 2210: Theory of Computation
    CS 2210: Theory of Computation Spring, 2019 Administrative Information • Background survey • Textbook: E. Rich, Automata, Computability, and Complexity: Theory and Applications, Prentice-Hall, 2008. • Book website: http://www.cs.utexas.edu/~ear/cs341/automatabook/ • My Office Hours: – Monday, 6:00-8:00pm, Searles 224 – Tuesday, 1:00-2:30pm, Searles 222 • TAs – Anjulee Bhalla: Hours TBA, Searles 224 – Ryan St. Pierre, Hours TBA, Searles 224 What you can expect from the course • How to do proofs • Models of computation • What’s the difference between computability and complexity? • What’s the Halting Problem? • What are P and NP? • Why do we care whether P = NP? • What are NP-complete problems? • Where does this make a difference outside of this class? • How to work the answers to these questions into the conversation at a cocktail party… What I will expect from you • Problem Sets (25%): – Goal: Problems given on Mondays and Wednesdays – Due the next Monday – Graded by following Monday – A learning tool, not a testing tool – Collaboration encouraged; more on this in next slide • Quizzes (15%) • Exams (2 non-cumulative, 30% each): – Closed book, closed notes, but… – Can bring in 8.5 x 11 page with notes on both sides • Class participation: Tiebreaker Other Important Things • Go to the TA hours • Study and work on problem sets in groups • Collaboration Issues: – Level 0 (In-Class Problems) • No restrictions – Level 1 (Homework Problems) • Verbal collaboration • But, individual write-ups – Level 2 (not used in this course) • Discussion with TAs only – Level 3 (Exams) • Professor clarifications only Right now… • What does it mean to study the “theory” of something? • Experience with theory in other disciplines? • Relationship to practice? – “In theory, theory and practice are the same.
    [Show full text]
  • The Problem with Threads
    The Problem with Threads Edward A. Lee Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-1.html January 10, 2006 Copyright © 2006, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science Foundation (NSF award No. CCR-0225610), the State of California Micro Program, and the following companies: Agilent, DGIST, General Motors, Hewlett Packard, Infineon, Microsoft, and Toyota. The Problem with Threads Edward A. Lee Professor, Chair of EE, Associate Chair of EECS EECS Department University of California at Berkeley Berkeley, CA 94720, U.S.A. [email protected] January 10, 2006 Abstract Threads are a seemingly straightforward adaptation of the dominant sequential model of computation to concurrent systems. Languages require little or no syntactic changes to sup- port threads, and operating systems and architectures have evolved to efficiently support them. Many technologists are pushing for increased use of multithreading in software in order to take advantage of the predicted increases in parallelism in computer architectures.
    [Show full text]
  • Computer Architecture: Dataflow (Part I)
    Computer Architecture: Dataflow (Part I) Prof. Onur Mutlu Carnegie Mellon University A Note on This Lecture n These slides are from 18-742 Fall 2012, Parallel Computer Architecture, Lecture 22: Dataflow I n Video: n http://www.youtube.com/watch? v=D2uue7izU2c&list=PL5PHm2jkkXmh4cDkC3s1VBB7- njlgiG5d&index=19 2 Some Required Dataflow Readings n Dataflow at the ISA level q Dennis and Misunas, “A Preliminary Architecture for a Basic Data Flow Processor,” ISCA 1974. q Arvind and Nikhil, “Executing a Program on the MIT Tagged- Token Dataflow Architecture,” IEEE TC 1990. n Restricted Dataflow q Patt et al., “HPS, a new microarchitecture: rationale and introduction,” MICRO 1985. q Patt et al., “Critical issues regarding HPS, a high performance microarchitecture,” MICRO 1985. 3 Other Related Recommended Readings n Dataflow n Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985. n Lee and Hurson, “Dataflow Architectures and Multithreading,” IEEE Computer 1994. n Restricted Dataflow q Sankaralingam et al., “Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture,” ISCA 2003. q Burger et al., “Scaling to the End of Silicon with EDGE Architectures,” IEEE Computer 2004. 4 Today n Start Dataflow 5 Data Flow Readings: Data Flow (I) n Dennis and Misunas, “A Preliminary Architecture for a Basic Data Flow Processor,” ISCA 1974. n Treleaven et al., “Data-Driven and Demand-Driven Computer Architecture,” ACM Computing Surveys 1982. n Veen, “Dataflow Machine Architecture,” ACM Computing Surveys 1986. n Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985. n Arvind and Nikhil, “Executing a Program on the MIT Tagged-Token Dataflow Architecture,” IEEE TC 1990.
    [Show full text]
  • Ece585 Lec2.Pdf
    ECE 485/585 Microprocessor System Design Lecture 2: Memory Addressing 8086 Basics and Bus Timing Asynchronous I/O Signaling Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F. Basic I/O – Part I ECE 485/585 Outline for next few lectures Simple model of computation Memory Addressing (Alignment, Byte Order) 8088/8086 Bus Asynchronous I/O Signaling Review of Basic I/O How is I/O performed Dedicated/Isolated /Direct I/O Ports Memory Mapped I/O How do we tell when I/O device is ready or command complete? Polling Interrupts How do we transfer data? Programmed I/O DMA ECE 485/585 Simplified Model of a Computer Control Control Data, Address, Memory Data Path Microprocessor Keyboard Mouse [Fetch] Video display [Decode] Printer [Execute] I/O Device Hard disk drive Audio card Ethernet WiFi CD R/W DVD ECE 485/585 Memory Addressing Size of operands Bytes, words, long/double words, quadwords 16-bit half word (Intel: word) 32-bit word (Intel: doubleword, dword) 0x107 64-bit double word (Intel: quadword, qword) 0x106 Note: names are non-standard 0x105 SUN Sparc word is 32-bits, double is 64-bits 0x104 0x103 Alignment 0x102 Can multi-byte operands begin at any byte address? 0x101 Yes: non-aligned 0x100 No: aligned. Low order address bit(s) will be zero ECE 485/585 Memory Operand Alignment …Intel IA speak (i.e. word = 16-bits = 2 bytes) 0x107 0x106 0x105 0x104 0x103 0x102 0x101 0x100 Aligned Unaligned Aligned Unaligned Aligned Unaligned word word Double Double Quad Quad address address word word word word -----0 address address address address -----00 ----000 ECE 485/585 Memory Operand Alignment Why do we care? Unaligned memory references Can cause multiple memory bus cycles for a single operand May also span cache lines Requiring multiple evictions, multiple cache line fills Complicates memory system and cache controller design Some architectures restrict addresses to be aligned Even in architectures without alignment restrictions (e.g.
    [Show full text]
  • 10. Assembly Language, Models of Computation
    10. Assembly Language, Models of Computation 6.004x Computation Structures Part 2 – Computer Architecture Copyright © 2015 MIT EECS 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #1 Beta ISA Summary • Storage: – Processor: 32 registers (r31 hardwired to 0) and PC – Main memory: Up to 4 GB, 32-bit words, 32-bit byte addresses, 4-byte-aligned accesses OPCODE rc ra rb unused • Instruction formats: OPCODE rc ra 16-bit signed constant 32 bits • Instruction classes: – ALU: Two input registers, or register and constant – Loads and stores: access memory – Branches, Jumps: change program counter 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #2 Programming Languages 32-bit (4-byte) ADD instruction: 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 opcode rc ra rb (unused) Means, to the BETA, Reg[4] ß Reg[2] + Reg[3] We’d rather write in assembly language: Today ADD(R2, R3, R4) or better yet a high-level language: Coming up a = b + c; 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #3 Assembly Language Symbolic 01101101 11000110 Array of bytes representation Assembler 00101111 to be loaded of stream of bytes 10110001 into memory ..... Source Binary text file machine language • Abstracts bit-level representation of instructions and addresses • We’ll learn UASM (“microassembler”), built into BSim • Main elements: – Values – Symbols – Labels (symbols for addresses) – Macros 6.004 Computation Structures L10: Assembly Language, Models
    [Show full text]
  • Actor Model of Computation
    Published in ArXiv http://arxiv.org/abs/1008.1459 Actor Model of Computation Carl Hewitt http://carlhewitt.info This paper is dedicated to Alonzo Church and Dana Scott. The Actor model is a mathematical theory that treats “Actors” as the universal primitives of concurrent digital computation. The model has been used both as a framework for a theoretical understanding of concurrency, and as the theoretical basis for several practical implementations of concurrent systems. Unlike previous models of computation, the Actor model was inspired by physical laws. It was also influenced by the programming languages Lisp, Simula 67 and Smalltalk-72, as well as ideas for Petri Nets, capability-based systems and packet switching. The advent of massive concurrency through client- cloud computing and many-core computer architectures has galvanized interest in the Actor model. An Actor is a computational entity that, in response to a message it receives, can concurrently: send a finite number of messages to other Actors; create a finite number of new Actors; designate the behavior to be used for the next message it receives. There is no assumed order to the above actions and they could be carried out concurrently. In addition two messages sent concurrently can arrive in either order. Decoupling the sender from communications sent was a fundamental advance of the Actor model enabling asynchronous communication and control structures as patterns of passing messages. November 7, 2010 Page 1 of 25 Contents Introduction ............................................................ 3 Fundamental concepts ............................................ 3 Illustrations ............................................................ 3 Modularity thru Direct communication and asynchrony ............................................................. 3 Indeterminacy and Quasi-commutativity ............... 4 Locality and Security ............................................
    [Show full text]
  • Computer Architecture Lecture 1: Introduction and Basics Where We Are
    Computer Architecture Lecture 1: Introduction and Basics Where we are “C” as a model of computation Programming Programmer’s view of a computer system works How does an assembly program end up executing as Architect/microarchitect’s view: digital logic? How to design a computer that meets system design goals. What happens in-between? Choices critically affect both How is a computer designed the SW programmer and using logic gates and wires the HW designer to satisfy specific goals? HW designer’s view of a computer system works CO Digital logic as a model of computation 2 Levels of Transformation “The purpose of computing is insight” (Richard Hamming) We gain and generate insight by solving problems How do we ensure problems are solved by electrons? Problem Algorithm Program/Language Runtime System (VM, OS, MM) ISA (Architecture) Microarchitecture Logic Circuits Electrons 3 The Power of Abstraction Levels of transformation create abstractions Abstraction: A higher level only needs to know about the interface to the lower level, not how the lower level is implemented E.g., high-level language programmer does not really need to know what the ISA is and how a computer executes instructions Abstraction improves productivity No need to worry about decisions made in underlying levels E.g., programming in Java vs. C vs. assembly vs. binary vs. by specifying control signals of each transistor every cycle Then, why would you want to know what goes on underneath or above? 4 Crossing the Abstraction Layers As long as everything goes well, not knowing what happens in the underlying level (or above) is not a problem.
    [Show full text]
  • A Model of Computation for VLSI with Related Complexity Results
    A Model of Computation for VLSI with Related Complexity Results BERNARD CHAZELLE AND LOUIS MONIER Carnegie-Mellon University, Pittsburgh, Pennsylvania Abstract. A new model of computation for VLSI, based on the assumption that time for propagating information is at least linear in the distance, is proposed. While accommodating for basic laws of physics, the model is designed to be general and technology independent. Thus, from a complexity viewpoint, it is especially suited for deriving lower bounds and trade-offs. New results for a number of problems, including fan-in, transitive functions, matrix multiplication, and sorting are presented. As regards upper bounds, it must be noted that, because of communication costs, the model clearly favors regular and pipelined architectures (e.g., systolic arrays). Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles-%91 (very- large-scale integration) General Terms: Algorithms, Theory Additional Key Words and Phrases: Chip complexity, lower bounds 1. Introduction The importance of having general models of computation for very-large-scale integration (VLSI) is apparent for various reasons, chief of which are the need for evaluating and comparing circuit performance, establishing lower bounds and trade-offs on area, time, and energy, and, more generally, building a complexity theory of VLSI computation. Although models must be simple and general enough to allow for mathematical analysis, they must also reflect reality regardless of the size of the circuit. We justify the latter claim by observing that if today’s circuits are still relatively small, the use of high-level design languages combined with larger integration, bigger chips, and improved yield may make asymptotic analysis quite relevant in the near future.
    [Show full text]
  • Neuromorphic Computing Is Turing-Complete and Therefore Capable of General-Purpose Computing
    NEUROMORPHIC COMPUTING IS TURING-COMPLETE Prasanna Date Catherine Schuman Bill Kay Computer Science & Mathematics Computer Science & Mathematics Computer Science & Mathematics Oak Ridge National Laboratory Oak Ridge National Laboratory Oak Ridge National Laboratory Oak Ridge, TN 37932 Oak Ridge, TN 37932 Oak Ridge, TN 37932 [email protected] [email protected] [email protected] Thomas Potok Computer Science & Mathematics Oak Ridge National Laboratory Oak Ridge, TN 37932 [email protected] April 30, 2021 ABSTRACT Neuromorphic computing is a non-von Neumann computing paradigm that performs computation by emulating the human brain. Neuromorphic systems are extremely energy-efficient and known to consume thousands of times less power than CPUs and GPUs. They have the potential to drive critical use cases such as autonomous vehicles, edge computing and internet of things in the future. For this reason, they are sought to be an indispensable part of the future computing landscape. Neuromorphic systems are mainly used for spike-based machine learning applications, although there are some non-machine learning applications in graph theory, differential equations, and spike-based simulations. These applications suggest that neuromorphic computing might be capable of general- purpose computing. However, general-purpose computability of neuromorphic computing has not been established yet. In this work, we prove that neuromorphic computing is Turing-complete and therefore capable of general-purpose computing. Specifically, we present a model of neuromorphic computing, with just two neuron parameters (threshold and leak), and two synaptic parameters (weight and delay). We devise neuromorphic circuits for computing all the µ-recursive functions (i.e., constant, successor and projection functions) and all the µ-recursive operators (i.e., composition, primitive recursion and minimization operators).
    [Show full text]
  • Introduction to Theory of Computation
    Introduction to Theory of Computation Anil Maheshwari Michiel Smid School of Computer Science Carleton University Ottawa Canada anil,michiel @scs.carleton.ca { } April 17, 2019 ii Contents Contents Preface vi 1 Introduction 1 1.1 Purposeandmotivation ..................... 1 1.1.1 Complexitytheory .................... 2 1.1.2 Computability theory . 2 1.1.3 Automatatheory ..................... 3 1.1.4 Thiscourse ........................ 3 1.2 Mathematical preliminaries . 4 1.3 Prooftechniques ......................... 7 1.3.1 Directproofs ....................... 8 1.3.2 Constructiveproofs. 9 1.3.3 Nonconstructiveproofs . 10 1.3.4 Proofsbycontradiction. 11 1.3.5 The pigeon hole principle . 12 1.3.6 Proofsbyinduction. 13 1.3.7 Moreexamplesofproofs . 15 Exercises................................. 18 2 Finite Automata and Regular Languages 21 2.1 An example: Controling a toll gate . 21 2.2 Deterministic finite automata . 23 2.2.1 Afirstexampleofafiniteautomaton . 26 2.2.2 Asecondexampleofafiniteautomaton . 28 2.2.3 A third example of a finite automaton . 29 2.3 Regularoperations ........................ 31 2.4 Nondeterministic finite automata . 35 2.4.1 Afirstexample ...................... 35 iv Contents 2.4.2 Asecondexample..................... 37 2.4.3 Athirdexample...................... 38 2.4.4 Definition of nondeterministic finite automaton . 39 2.5 EquivalenceofDFAsandNFAs . 41 2.5.1 Anexample ........................ 44 2.6 Closureundertheregularoperations . 48 2.7 Regularexpressions. .. .. 52 2.8 Equivalence of regular expressions and regular languages . 56 2.8.1 Every regular expression describes a regular language . 57 2.8.2 Converting a DFA to a regular expression . 60 2.9 The pumping lemma and nonregular languages . 67 2.9.1 Applications of the pumping lemma . 69 2.10Higman’sTheorem ........................ 76 2.10.1 Dickson’sTheorem .
    [Show full text]
  • Instruction Set Completeness Theorem: Concept Relevance Proof
    Instruction Set Completeness Theorem: Concept, Relevance, Proof, and Example for Processor Architecture William F. Gilreath ([email protected]) March 2017 Abstract The Instruction Set Completeness Theorem is first formally defined and discussed in the seminal work on one-instruction set computing—the book Computer Architecture: A Minimalist Perspective. Yet the original formalism of the Instruction Set Completeness Theorem did not provide a definitive, explicit mathematical proof of completeness, analyze both singular and plural instruction sets that were either complete or incomplete, nor examine the significance of the theorem to computer architecture instruction sets. A mathematical proof of correctness shows the equivalence of the Instruction Set Completeness Theorem to a Turing machine, a hypothetical model of computation, and thereby establishes the mathematical truth of the Instruction Set Completeness Theorem. With a more detailed examination of the Instruction Set Completeness Theorem develops several surprising conclusions for both the instruction set completeness theorem, and the instruction sets for a computer architecture. Keywords: Church-Turing Thesis, computation model, computer architecture, computer organization, instruction set, instruction set completeness theorem, plural instruction set, processor architecture, one-instruction computer, one-instruction set computer, singular instruction set, Turing machine, von Neumann architecture Instruction Set Completeness Theorem: Concept, Relevance, Proof, and Example for Processor Architecture 1. Introduction The Instruction Set Completeness Theorem is formally stated by Gilreath and Laplante [Gilr 2003c] by: “Any processor with a complete instruction set must be stateful of computation. That is, a means to alter the state or next state transition by explicit operation or by implicit computation is needed to deterministically affect processor state.” The five principles of the Instruction Set Completeness Theorem are stated by Gilreath and Laplante.
    [Show full text]
  • Arxiv:1707.06202V1 [Cs.ET] 19 Jul 2017
    Instruction Set Architectures for Quantum Processing Units Keith A. Britt? and Travis S. Humble Quantum Computing Institute Oak Ridge National Laboratory Oak Ridge, Tennessee USA 37830 {brittka,humblets}@ornl.gov http://quantum.ornl.gov Abstract. Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows. We briefly describe several promi- nent quantum computational models, their associated quantum process- ing units (QPUs), and the adoption of these devices as accelerators within high-performance computing systems. Emphasizing the interface to the QPU, we analyze instruction set architectures based on reduced and com- plex instruction sets, i.e., RISC and CISC architectures. We clarify the role of conventional constraints on memory addressing and instruction widths within the quantum computing context. Finally, we examine ex- isting quantum computing platforms, including the D-Wave 2000Q and IBM Quantum Experience, within the context of future ISA development and HPC needs. Keywords: quantum, accelerator, instruction set architecture, qubit 1 Quantum Processing Units The realization of quantum processing units (QPUs) represents a milestone in computing. For decades theoretical computational complexity gains using QPUs have served as a lure to solving conventionally intractable problems. As an exam- ple, using two different models of quantum computing Grover's quantum searchp algorithm finds a marked item in an unordered database of size N in O( N) whereas the best classical approach, a sequential search, requires O(N) [1,2]. ? This contribution has been authored by UT-Battelle, LLC, under Contract No. DE- AC0500OR22725 with the U.S. Department of Energy.
    [Show full text]