Options by IBM: IBM 512MB PC800 16D ECC RDRAM RIMM Memory Upgrade

Total Page:16

File Type:pdf, Size:1020Kb

Options by IBM: IBM 512MB PC800 16D ECC RDRAM RIMM Memory Upgrade Hardware Announcement April 24, 2001 Options by IBM: IBM 512MB PC800 16D ECC RDRAM RIMM Memory Upgrade Overview Key Prerequisites At a Glance Improve the performance capability The 512MB PC800 16D ECC RDRAM of your selected NetVista A60, RIMM memory upgrade is supported The IBM 512MB PC800 16D ECC NetVista A60i, IntelliStation M Pro on selected models of NetVista A60, RDRAM RIMM memory upgrade and Z Pro systems with the new IBM NetVista A60i, IntelliStation M Pro features: 512MB PC800 Rambus DRAM and Z Pro, as shown in the Hardware • Fast access time — synchronous (RDRAM) RIMM memory upgrade. Requirements section. ′ The Rambus function enables faster to the Rambus channel s clock IBM List Price*: $1,249 performance than either fast page • 184-pin RIMM with gold-plated mode (FPM), hyper-page mode * IBM price; does not include tax or leads (EDO), or the more recent shipping and is subject to change • Synchronous DRAM (SDRAM) mode without notice. Reseller prices may Guaranteed compatibility on memory. vary. IBM systems listed in the Hardware Requirements section This offering lets you upgrade Part Number: 33L3254 1 standard system memory and take • Warranted by IBM advantage of the latest operating Planned Availability Date In order to get the genuine product, systems and applications. Adding be sure to specify “IBM” Product. additional memory is a cost-effective Second Quarter 2001 Similar products are offered under way to help optimize your system′s identical part numbers that are performance. Trademarks neither supported, nor warranted, To optimize the performance of the NetVista is a trademark of by IBM. International Business Machines Rambus technology, there is a Corporation in the United States or 1 For information on and copies of limitation of 32 devices on a other countries or both. IBM′s statement of limited particular channel. IBM products IntelliStation is a registered warranty, go to state the number of devices in each trademark of International Business http://www.pc.ibm.com/support RIMM with a number followed by the Machines Corporation in the United or contact your local reseller. character “D.” The Rambus signal States or other countries or both. channel is a high-quality terminated Other company, product, and service For technical support: transmission line as contrasted with names may be trademarks or service marks of others. • Request technical information memory buses used in previous via the IBM Personal Systems technologies. Memory sockets that Group (PSG) Web site at are not occupied with RIMMs must http://www.ibm.com/pc/support be populated with “jumper” cards in or IBM Faxback (800-426-3395) order for the signals in the channel to be properly terminated. The 512MB PC800 16D ECC RDRAM RIMM memory upgrade meets or exceeds IBM reliability standards for memory products. This announcement is provided for your information only. For additional information, contact your IBM representative, call 800-IBM-4YOU, or visit the IBM home page at: http://www.ibm.com. IBM United States IBM is a registered trademark of International Business Machines Corporation. 101-123 IBM US Announcement Supplemental Information April 24, 2001 Indicated IntelliStation M Pro and Z Pro models must be IBM 512MB PC800 16D ECC RDRAM RIMM upgraded with pairs (two at a time, same speed, capacity Memory Upgrade (33L3254) and technology) of RIMMs. System board memory sockets must be populated with Technical Information jumper boards, if a RIMM is not present, in order for the signals on the memory channel to be properly terminated. Performance Specifications Caution • 256 Mb Technology • 800 MHz Rambus operation • ECC function organized as 64M x 72 IBM Rambus memory upgrade product names contain a • Serial presence detect/decode number followed by “D.” The number represents the • 184-pin, 1-mm pin spacing number of RDRAM devices used to construct that • 2.5-volt supply particular RIMM. Exceeding a total of 32 devices, more • Gold-plated contacts likely on systems with 3 RIMM sockets, may not operate • RIMM built with 16 RDRAMs using Chip Scale Package or may produce unpredictable results. (CSP) with metal covers to protect the RDRAM devices and act as a heat sink Planning Information Physical Specifications Cable Orders Required: No • Approximate height: 31.75 mm (1.25 in) Installation Time: Approximately five minutes (30 • Approximate width: 133.35 mm (5.25 in) minutes if BIOS needs to be updated) • Approximate depth: 7.4 mm (0.29 in) Packaging: One kraft box with IBM logo and Operating Environment tamper-evident security seal. • ° ° ° ° Temperature: 10 to 35 C (50 to 95 F) Shipment Group • Relative humidity: 80% • IBM 512MB PC800 16D ECC RDRAM RIMM memory ENERGY STAR-Compliant: No upgrade • Publication Hardware Requirements — IBM Systems: The IBM 512MB • Minimum BIOS level flyer PC800 16D ECC RDRAM RIMM memory upgrade is supported on the following IBM systems: Note: The Hardware Maintenance Manual has been discontinued. System Name Machine Type Models Security, Auditability, and Control NetVista A60 68332, 6838 All, in pairs 2 NetVista A60i 6832 , 6848 All, in pairs This product uses the security and auditability features IntelliStation M Pro 6849, 6868 All, in pairs of the system in which it is installed. It also includes: IntelliStation Z Pro 68663 All, in pairs 2 • Tamper-evident packaging bearing the IBM logo 1.5 GB maximum. • 3 The amount of system memory available with 4 GB installed Product serial number on product carton will depend on what adapters are installed in the system. • Bar code serialized DIMM The 840 chipset supports up to 4 GB of memory, however, • Authenticity seal applied to the DIMM the X86 architecture has various memory mapped I/O and • IBM logo on the memory module to indicate genuine non-system memory required by PCI adapters at the high product end of this address range. This will truncate the system memory by the amount of memory required by system flash and PCI adapters installed. Terms and Conditions Hardware Requirements — Non-IBM Systems: The IBM Field-Installable Yes 512MB PC800 16D ECC RDRAM RIMM memory upgrade Customer Setup Yes is supported on non-IBM systems that support industry Limited Warranty Period4 3 Years standard RAMBUS to the PC800 specification. Service Type CCE Maintenance Agreement No Limitations: Older systems will require a BIOS update to Optional Upgrade No recognize this product. Refer to the flyer included with Central Facility Maintenance No the product for the minimum BIOS level required for your Service (CFMS) Option specific system. Licensed Programs No This announcement is provided for your information only. For additional information, contact your IBM representative, call 800-IBM-4YOU, or visit the IBM home page at: http://www.ibm.com. IBM United States IBM is a registered trademark of International Business Machines Corporation. 101-123 All other terms and conditions are the same as those applicable to the IBM machine type in which the feature is installed. 4 Information on and copies of IBM′s statement of limited warranty can be obtained by calling the HelpCenter at 800-772-2227, by contacting your reseller, or by accessing the online services listed in the Help and Service Information section. Help and Service Information During the warranty period, technical support can be obtained by accessing IBM′s online services or calling the HelpCenter (800-772-2227), to answer questions regarding your new IBM option. Response time will vary depending on the number and nature of calls received. If you need warranty service, return or exchange is available. In addition, if your IBM option is installed in an IBM computer, you may be entitled to service at your location. Your technical support representative can help you determine the best alternative. Accessing IBM Online Services • IBM Web site at http://www.ibm.com/pc/support • IBM Fax system at 800-426-3395 Prices IBM Part List Description Number Price5 IBM 512MB PC800 16D 33L3254 $1,249 ECC RDRAM RIMM Memory Upgrade 5 IBM price; does not include tax or shipping and is subject to change without notice. Reseller prices may vary. Trademarks NetVista is a trademark of International Business Machines Corporation in the United States or other countries or both. IntelliStation and HelpCenter are registered trademarks of International Business Machines Corporation in the United States or other countries or both. Other company, product, and service names may be trademarks or service marks of others. 101-123 -2-.
Recommended publications
  • 2GB DDR3 SDRAM 72Bit SO-DIMM
    Apacer Memory Product Specification 2GB DDR3 SDRAM 72bit SO-DIMM Speed Max CAS Component Number of Part Number Bandwidth Density Organization Grade Frequency Latency Composition Rank 0C 78.A2GCB.AF10C 8.5GB/sec 1066Mbps 533MHz CL7 2GB 256Mx72 256Mx8 * 9 1 Specifications z Support ECC error detection and correction z On DIMM Thermal Sensor: YES z Density:2GB z Organization – 256 word x 72 bits, 1rank z Mounting 9 pieces of 2G bits DDR3 SDRAM sealed FBGA z Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) --- PCB height: 30.0mm --- Lead pitch: 0.6mm (pin) --- Lead-free (RoHS compliant) z Power supply: VDD = 1.5V + 0.075V z Eight internal banks for concurrent operation ( components) z Interface: SSTL_15 z Burst lengths (BL): 8 and 4 with Burst Chop (BC) z /CAS Latency (CL): 6,7,8,9 z /CAS Write latency (CWL): 5,6,7 z Precharge: Auto precharge option for each burst access z Refresh: Auto-refresh, self-refresh z Refresh cycles --- Average refresh period 7.8㎲ at 0℃ < TC < +85℃ 3.9㎲ at +85℃ < TC < +95℃ z Operating case temperature range --- TC = 0℃ to +95℃ z Serial presence detect (SPD) z VDDSPD = 3.0V to 3.6V Apacer Memory Product Specification Features z Double-data-rate architecture; two data transfers per clock cycle. z The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. z Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. z DQS is edge-aligned with data for READs; center aligned with data for WRITEs.
    [Show full text]
  • Different Types of RAM RAM RAM Stands for Random Access Memory. It Is Place Where Computer Stores Its Operating System. Applicat
    Different types of RAM RAM RAM stands for Random Access Memory. It is place where computer stores its Operating System. Application Program and current data. when you refer to computer memory they mostly it mean RAM. The two main forms of modern RAM are Static RAM (SRAM) and Dynamic RAM (DRAM). DRAM memories (Dynamic Random Access Module), which are inexpensive . They are used essentially for the computer's main memory SRAM memories(Static Random Access Module), which are fast and costly. SRAM memories are used in particular for the processer's cache memory. Early memories existed in the form of chips called DIP (Dual Inline Package). Nowaday's memories generally exist in the form of modules, which are cards that can be plugged into connectors for this purpose. They are generally three types of RAM module they are 1. DIP 2. SIMM 3. DIMM 4. SDRAM 1. DIP(Dual In Line Package) Older computer systems used DIP memory directely, either soldering it to the motherboard or placing it in sockets that had been soldered to the motherboard. Most memory chips are packaged into small plastic or ceramic packages called dual inline packages or DIPs . A DIP is a rectangular package with rows of pins running along its two longer edges. These are the small black boxes you see on SIMMs, DIMMs or other larger packaging styles. However , this arrangment caused many problems. Chips inserted into sockets suffered reliability problems as the chips would (over time) tend to work their way out of the sockets. 2. SIMM A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s .
    [Show full text]
  • Product Guide SAMSUNG ELECTRONICS RESERVES the RIGHT to CHANGE PRODUCTS, INFORMATION and SPECIFICATIONS WITHOUT NOTICE
    May. 2018 DDR4 SDRAM Memory Product Guide SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd. All rights reserved. - 1 - May. 2018 Product Guide DDR4 SDRAM Memory 1. DDR4 SDRAM MEMORY ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 K 4 A X X X X X X X - X X X X SAMSUNG Memory Speed DRAM Temp & Power DRAM Type Package Type Density Revision Bit Organization Interface (VDD, VDDQ) # of Internal Banks 1. SAMSUNG Memory : K 8. Revision M: 1st Gen. A: 2nd Gen. 2. DRAM : 4 B: 3rd Gen. C: 4th Gen. D: 5th Gen.
    [Show full text]
  • PATENT PLEDGES Jorge L. Contreras*
    PATENT PLEDGES Jorge L. Contreras* ABSTRACT An increasing number of firms are making public pledges to limit the enforcement of their patents. In doing so, they are entering a little- understood middle ground between the public domain and exclusive property rights. The best-known of these patent pledges are FRAND commitments, in which patent holders commit to license their patents to manufacturers of standardized products on terms that are “fair, reasonable and non-discriminatory.” But patent pledges have been appearing in settings well beyond standard-setting, including open source software, green technology and the life sciences. As a result, this increasingly prevalent private ordering mechanism is beginning to reshape the role and function of patents in the economy. Despite their proliferation, little scholarship has explored the phenomenon of patent pledges beyond FRAND commitments and standard- setting. This article fills this gap by providing the first comprehensive descriptive account of patent pledges across the board. It offers a four-part taxonomy of patent pledges based on the factors that motivate patent holders to make them and the effect they are intended to have on other market actors. Using this classification system, it argues that pledges likely to induce reliance in other market actors should be treated as “actionable” * Associate Professor, S.J. Quinney College of Law, University of Utah and Senior Policy Fellow, American University Washington College of Law. The author thanks Jonas Anderson, Clark Asay, Marc Sandy Block, Mark Bohannon, Matthew Bye, Michael Carrier, Michael Carroll, Colleen Chien, Thomas Cotter, Carter Eltzroth, Carissa Hessick, Meredith Jacob, Jay Kesan, Anne Layne-Farrar, Irina Manta, Sean Pager, Gideon Parchomovsky, Arti Rai, Amelia Rinehart, Cliff Rosky, Daniel Sokol and Duane Valz for their helpful comments, suggestions and discussion of this article and contributions of data to the Patent Pledge Database at American University.
    [Show full text]
  • Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines, External
    5. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines June 2012 EMI_DG_005-4.1 EMI_DG_005-4.1 This chapter describes guidelines for implementing dual unbuffered DIMM (UDIMM) DDR2 and DDR3 SDRAM interfaces. This chapter discusses the impact on signal integrity of the data signal with the following conditions in a dual-DIMM configuration: ■ Populating just one slot versus populating both slots ■ Populating slot 1 versus slot 2 when only one DIMM is used ■ On-die termination (ODT) setting of 75 Ω versus an ODT setting of 150 Ω f For detailed information about a single-DIMM DDR2 SDRAM interface, refer to the DDR2 and DDR3 SDRAM Board Design Guidelines chapter. DDR2 SDRAM This section describes guidelines for implementing a dual slot unbuffered DDR2 SDRAM interface, operating at up to 400-MHz and 800-Mbps data rates. Figure 5–1 shows a typical DQS, DQ, and DM signal topology for a dual-DIMM interface configuration using the ODT feature of the DDR2 SDRAM components. Figure 5–1. Dual-DIMM DDR2 SDRAM Interface Configuration (1) VTT Ω RT = 54 DDR2 SDRAM DIMMs (Receiver) Board Trace FPGA Slot 1 Slot 2 (Driver) Board Trace Board Trace Note to Figure 5–1: (1) The parallel termination resistor RT = 54 Ω to VTT at the FPGA end of the line is optional for devices that support dynamic on-chip termination (OCT). © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries.
    [Show full text]
  • Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory Sung I
    Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory Sung I. Hong, Sally A. McKee†, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, Wm. A. Wulf Dept. of Electrical and Computer Engineering †Dept. of Computer Science University of Virginia University of Utah Charlottesville, VA 22903 Salt Lake City, Utah 84112 Abstract current DRAM page forces a new page to be accessed. The Processor speeds are increasing rapidly, and memory speeds are overhead time required to do this makes servicing such a request not keeping up. Streaming computations (such as multi-media or significantly slower than one that hits the current page. The order of scientific applications) are among those whose performance is requests affects the performance of all such components. Access most limited by the memory bottleneck. Rambus hopes to bridge the order also affects bus utilization and how well the available processor/memory performance gap with a recently introduced parallelism can be exploited in memories with multiple banks. DRAM that can deliver up to 1.6Gbytes/sec. We analyze the These three observations — the inefficiency of traditional, performance of these interesting new memory devices on the inner dynamic caching for streaming computations; the high advertised loops of streaming computations, both for traditional memory bandwidth of Direct Rambus DRAMs; and the order-sensitive controllers that treat all DRAM transactions as random cacheline performance of modern DRAMs — motivated our investigation of accesses, and for controllers augmented with streaming hardware. a hardware streaming mechanism that dynamically reorders For our benchmarks, we find that accessing unit-stride streams in memory accesses in a Rambus-based memory system.
    [Show full text]
  • Big Data, AI, and the Future of Memory
    Big Data, AI, and the Future of Memory Steven Woo Fellow and Distinguished Inventor, Rambus Inc. May 15, 2019 Memory Advancements Through Time 1990’s 2000’s 2010’s 2020’s Synchronous Memory Graphics Memory Low Power Memory Ultra High Bandwidth for PCs for Gaming for Mobile Memory for AI Faster Compute + Big Data Enabling Explosive Growth in AI 1980s Annual Size of the Global Datasphere – 1990s Now 175 ZB More 180 Accuracy Compute Neural Networks 160 140 120 Other Approaches 100 Zettabytes 80 60 40 20 Scale (Data Size, Model Size) 2010 2015 2020 2025 Source: Adapted from Jeff Dean, “Recent Advances in Artificial Intelligence and the Source: Adapted from Data Age 2025, sponsored by Seagate Implications for Computer System Design,” HotChips 29 Keynote, August 2017 with data from IDC Global DataSphere, Nov 2018 Key challenges: Moore’s Law ending, energy efficiency growing in importance ©2019 Rambus Inc. 3 AI Accelerators Need Memory Bandwidth Google TPU v1 1000 TPU Roofline Inference on newer silicon (Google TPU K80 Roofline HSW Roofline v1) built for AI processing largely limited LSTM0 by memory bandwidth LSTM1 10 MLP1 MLP0 v nVidia K80 CNN0 Inference on older, general purpose Intel Haswell CNN1 hardware (Haswell, K80) limited by LSTM0 1 LSTM1 compute and memory bandwidth TeraOps/sec (log scale) (log TeraOps/sec MLP1 MLP0 CNN0 0.1 CNN1 LSTM0 1 10 100 1000 Memory bandwidth is a critical LSTM1 Ops/weight byte (log scale) resource for AI applications = Google TPU v1 = nVidia K80 = Intel Haswell N. Jouppi, et.al., “In-Datacenter Performance Analysis of a Tensor Processing Unit™,” https://arxiv.org/ftp/arxiv/papers/1704/1704.04760.pdf ©2019 Rambus Inc.
    [Show full text]
  • DDR SDRAM SO-DIMM MODULE, 2.5V 128Mbyte - 16MX64 AVK6416U35C5266K0-AP
    DDR SDRAM SO-DIMM MODULE, 2.5V 128MByte - 16MX64 AVK6416U35C5266K0-AP FEATURES JEDEC Standard DDR 266MHz PC2100 Version 1.0, Lead Free, RoHS compliant Clock frequency: 133MHz with CAS latency 2.5 256 byte serial EEPROM Data input and output masking Programmable burst length: 2, 4, 8 Programmable burst type: sequential and interleave Programmable CAS latency: 2.5 Auto refresh and self refresh capability Gold card edge fingers 8K refresh per 64ms Low active and standby current consumption SSTL-2 compatible inputs and outputs Decoupling capacitors at each memory device Double-sided module 30.75mm (1.25 inch) height DESCRIPTION The AVK6416U35C5266K0-AP is an Unbuffered DDR SDRAM SODIMM memory module. This module is JEDEC- standard 200-pin, small-outline, dual in-line memory module. A 256 byte serial EEPROM on board can be used to store module information such as timing, configuration, density, etc. The AVK6416U35C5266K0-AP memory module is 128MByte and organized as a 16MX64 array using (8) 8MX16 DDR SDRAMs in lead free TSSOP II packages. All memory modules are fabricated using the latest technology design, six-layer printed circuit board substrate construction with low ESR decoupling capacitors on-board for high reliability and low noise. PHYSICAL DIMENSIONS 67.60 (2.66) 3.50 (0.14) SPD 128Mbit 128Mbit 128Mbit 128Mbit ) 5 8MbX16 8MbX16 8MbX16 8MbX16 2 . 1 ( DDR DDR DDR DDR 5 7 SDRAM SDRAM SDRAM SDRAM . 1 ) 3 7 8 7 . 0 ( 0 2 FRONT SIDE 1.00 (0.04) Pin 1 Pin 199 NOTES: 1- All dimensions are in milimeters (inches) 2- All blue ICs are on the front, and all red ICs are on the back side of the module.
    [Show full text]
  • Download Attachment
    NON-CONFIDENTIAL 2010-1556 UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT ASUSTEK COMPUTER INC., ASUS COMPUTER INTERNATIONAL, INC., BFG TECHNOLOGIES, INC., BIOSTAR MICROTECH (U.S.A.) CORP., BIOSTAR MICROTECH INTERNATIONAL CORP., DIABLOTEK, INC., EVGA CORP., G.B.T., INC., GIGA-BYTE TECHNOLOGY CO., LTD., HEWLETT-PACKARD COMPANY, MSI COMPUTER CORP., MICRO-STAR INTERNATIONAL COMPANY, LTD., GRACOM TECHNOLOGIES LLC (FORMERLY KNOWN AS PALIT MULTIMEDIA, INC.), PALIT MICROSYSTEMS LTD., PINE TECHNOLOGY (MACAO COMMERCIAL OFFSHORE) LTD., AND SPARKLE COMPUTER COMPANY, LTD. Appellants, — v. — INTERNATIONAL TRADE COMMISSION, Appellee, and RAMBUS, INC., Intervenor, and NVIDIA CORPORATION, Intervenor. ______________ 2010-1557 ______________ NVIDIA CORPORATION, Appellant, — v. — INTERNATIONAL TRADE COMMISSION, Appellee, and RAMBUS, INC., Intervenor. ______________ ON APPEAL FROM THE UNITED STATES INTERNATIONAL TRADE COMMISSION IN INVESTIGATION NO. 337-TA-661 ______________ NON-CONFIDENTIAL REPLY BRIEF OF APPELLANTS NVIDIA CORPORATION ET AL. _______________ *Caption Continued on Next Page COMPANION CASES TO: 2010-1483 RAMBUS, INC., Appellant, — v. — INTERNATIONAL TRADE COMMISSION, Appellee, and NVIDIA CORPORATION ET AL., Intervenors. ______________ RUFFIN B. CORDELL I. NEEL CHATTERJEE MARK S. DAVIES ANDREW R. KOPSIDAS RICHARD S. SWOPE RACHEL M. MCKENZIE FISH & RICHARDSON P.C. NITIN GAMBHIR LAUREN J. PARKER 1425 K Street, NW, 11th Floor ORRICK, HERRINGTON ORRICK, HERRINGTON Washington, DC 20005 & SUTCLIFFE LLP & SUTCLIFFE LLP Tel. No. 202-626-6449
    [Show full text]
  • Appendix to Brief of Appellee and Cross-Appellant Rambus Inc
    PUBLIC UNITED STATES OF AMERICA BEFORE FEDERAL TRADE COMMISSION COMMISSIONERS: Deborah Platt Majoras, Chairman Orson Swindle Thomas B. Leary Pamela Jones Harbour Jon Leibowitz ) In the Matter of ) RAMBUS INCORPORATED, ) ) a corporation. ) Docket No. 9302 ) ) ) APPENDIX TO BRIEF OF APPELLEE AND CROSS-APPELLANT RAMBUS INC. Pursuant to the Commission’s October 4, 2004 Order granting Rambus leave to file an appendix, Rambus submits this appendix to its appeal brief containing a glossary of terms. -1- US1DOCS 4782131v1 Glossary of Terms Auto precharge: DRAMs store information as minute quantities of electrical charge in memory cells – no charge is interpreted as “0" and positive charge as a “1.” Sense amplifiers are circuits on the DRAM that sense the charge in a memory cell and amplify it when information is to be read from the DRAM. Before the sense amplifiers can perform this function, they must be “precharged” to an intermediate charged state. “Auto precharge” is a feature that was originally found in RDRAMs and later adopted by SDRAMs and DDR SDRAMs that allows the controller to determine whether the sense amplifiers are to be automatically precharged – that is, precharged without the need for a separate precharge command – at the end of a read or write operation. Bit/Byte: A bit or “binary digit” is the unit of information used by digital computers that takes on only two values – “0" or “1." Each memory cell in a DRAM stores a single bit. A “byte” usually refers to eight bits. Since each bit in a byte can take on two values, a byte can take on 28, or 256, possible values.
    [Show full text]
  • The Intel Random Number Generator
    ® THE INTEL RANDOM NUMBER GENERATOR CRYPTOGRAPHY RESEARCH, INC. WHITE PAPER PREPARED FOR INTEL CORPORATION Benjamin Jun and Paul Kocher April 22, 1999 Information in this white paper is provided without guarantee or warranty of any kind. This review represents the opinions of Cryptography Research and may or may not reflect opinions of Intel Corporation. Characteristics of the Intel RNG may vary with design or process changes. © 1999 by Cryptography Research, Inc. and Intel Corporation. 1. Introduction n = − H K∑ pi log pi , Good cryptography requires good random i=1 numbers. This paper evaluates the hardware- where pi is the probability of state i out of n based Intel Random Number Generator (RNG) possible states and K is an optional constant to for use in cryptographic applications. 1 provide units (e.g., log(2) bit). In the case of a Almost all cryptographic protocols require random number generator that produces a k-bit the generation and use of secret values that must binary result, pi is the probability that an output be unknown to attackers. For example, random will equal i, where 0 ≤ i < 2k . Thus, for a number generators are required to generate -k perfect random number generator, pi = 2 and public/private keypairs for asymmetric (public the entropy of the output is equal to k bits. This key) algorithms including RSA, DSA, and means that all possible outcomes are equally Diffie-Hellman. Keys for symmetric and hybrid (un)likely, and on average the information cryptosystems are also generated randomly. present in the output cannot be represented in a RNGs are also used to create challenges, nonces sequence shorter than k bits.
    [Show full text]
  • DDR3 SODIMM Product Datasheet
    DDR3 SODIMM Product Datasheet 廣 穎 電 通 股 份 有 限 公 司 Silicon Power Computer & Communications Inc. TEL: 886-2 8797-8833 FAX: 886-2 8751-6595 台北市114內湖區洲子街106號7樓 7F, No.106, ZHO-Z ST. NEIHU DIST, 114, TAIPEI, TAIWAN, R.O.C This document is a general product description and is subject to change without notice DDR3 SODIMM Product Datasheet Index Index...................................................................................................................................................................... 2 Revision History ................................................................................................................................................ 3 Description .......................................................................................................................................................... 4 Features ............................................................................................................................................................... 5 Pin Assignments................................................................................................................................................ 7 Pin Description................................................................................................................................................... 8 Environmental Requirements......................................................................................................................... 9 Absolute Maximum DC Ratings....................................................................................................................
    [Show full text]