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Intel® 64 and IA32 Architectures Performance Monitoring Events Intel® 64 and IA32 Architectures Performance Monitoring Events 2017 December Revision 1.0 Document Number:335279-001 Performance Monitoring Events No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice.Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at http://intel.com/. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1.800.548.4725 or by visiting www.intel.com/design/literature.htm. Intel, the Intel logo, and Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2017, Intel Corporation. All Rights Reserved. 1 Document Number:335279-001 Revision 1.0 Performance Monitoring Events Revision History Document Number Revision Number Description Date 334525-001 1.0 Initial release of the document 2017 December 2 Document Number:335279-001 Revision 1.0 Performance Monitoring Events Performance Monitoring Events Glossary......................................................................................................................................................................... 4 Architectural Performance Monitoring Events.....................................................................................................7 Performance Monitoring Events based on Skylake Microarchitecture - 6th Generation Intel® Core™ Processor and 7th Generation Intel® Core™ Processor.....................................................................................10 Performance Monitoring Events based on Broadwell Microarchitecture - Intel® Core™ M and 5th Generation Intel® Core™ Processors......................................................................................................................42 Performance Monitoring Events based on Haswell Microarchitecture - Intel Xeon® Processor E5 v3 Family.......................................................................................................................................................................... 80 Performance Monitoring Events based on Haswell-E Microarchitecture- Intel Xeon Processor E5 v3 Family........................................................................................................................................................................111 Performance Monitoring Events based on Ivy Bridge Microarchitecture - 3rd Generation Intel® Core™ Processors................................................................................................................................................................112 Performance Monitoring Events based on Ivy Bridge-E Microarchitecture - 3rd Generation Intel® Core™ Processors.................................................................................................................................................... 137 Performance Monitoring Events based on Sandy Bridge Microarchitecture - 2nd Generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx Processor Series............................................ 138 Performance Monitoring Events based on Westmere-EP-SP Microarchitecture.....................................166 Performance Monitoring Events based on Westmere-EP-DP Microarchitecture.................................... 191 Performance Monitoring Events based on Nehalem Microarchitecture - Intel® Core™ i7 Processor Family and Intel® Xeon®® Processor Family...................................................................................................... 216 Performance Monitoring Events based on Knights Landing Microarchitecture - Intel® Xeon® Phi™ Processor 3200, 5200, 7200 Series................................................................................................................. 241 Performance Monitoring Events based on Knights Corner Microarchitecture........................................ 250 Performance Monitoring Events based on Goldmont Plus Microarchitecture.........................................258 Performance Monitoring Events based on Goldmont Microarchitecture..................................................272 Performance Monitoring Events based on Airmont Microarchitecture.....................................................284 Performance Monitoring Events based on Silvermont Microarchitecture................................................298 Performance Monitoring Events based on Bonnell Microarchitecture......................................................312 3 Document Number:335279-001 Revision 1.0 Performance Monitoring Events Glossary Glossary Items as listed below: Name Description EventSelect Set the EventSelect bits to the value specified. These bits are defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. UMask Set the UMask bits to the value specified. These bits are defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. USR Set the USR bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set the bit according to the desired scope. When set, the counter will count events when the logical processor is operating at privilege level 0. This flag can be used with the USR flag. OS Set the OS bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set the bit according to the desired scope. When set, the counter will count events when the logical processor is operating at privilege levels 1, 2 or 3. This flag can be used with the OS flag. EdgeDetect Set the EdgeDetect bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set this bit to 0. AnyThread Set the AnyThread bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set this bit to 0. Invert Set the Invert bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set this bit to 0. CMask Set the CMask bits to the value specified. These bits are defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. MSR_PEBS_FRONTEND Set the MSR_PEBS_FRONTEND bits to the value specified. These bits are defined in Chapter 18.13.1.4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. MSR_PEBS_LD_LAT_THRESHOLD Set the MSR_PEBS_LD_LAT_THRESHOLD bits to the value specified. These bits are defined in Chapter 18.8.1.2 and the relevant PEBS sub-sections across the core PMU sections in Chapter 18, Performance Monitoring. 4 Document Number:335279-001 Revision 1.0 Performance Monitoring Events Architectural This event is architecturally defined as described in Chapter 18.2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Fixed This event uses a Fixed-function Performance Counter Register, as defined in Chapter 18.2.2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Precise The Processor Event Based Sampling (PEBS) facility is capable of capturing the exact machine state after the instruction that experienced this event retires, including R/EIP of the next instruction. In some generations, information about the instruction that experienced the event is also available. See Section 18.4.4, “Processor Event Based Sampling (PEBS),” and the relevant PEBS sub-sections across the core PMU sections in Chapter 18, “Performance Monitoring.” Deprecated In future generations, this event has its name changed or is no longer supported. It remains supported in this generation. 5 Document Number:335279-001 Revision 1.0 Performance Monitoring Events Architectural Performance Monitoring Events 6 Document Number:335279-001 Revision 1.0 Performance Monitoring Events Architectural Performance Monitoring Events Architectural performance events are introduced in Intel Core Solo and Intel Core Duo processors. They are also supported on processors based on Intel Core microarchitecture. Table below lists pre-defined architectural performance events that can be configured using general-purpose performance counters and associated event-select
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