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Measuring Jitter in Digital Systems

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Measuring Jitter in Digital Systems Measuring Jitter in Digital Systems Application Note 1448-1 Table of Contents Measuring jitter in digital systems Measuring jitter in digital systems: . 1 The topic of jitter is becoming increasingly critical to the Why measure jitter?: . 2 proper design of digital subsystems. In the past, digital designers were largely concerned with functional issues. Eye diagrams portray jitter intuitively: . 2 Now, in addition to debugging the functionality of a Jitter reduction requires a multifaceted view: . 3 design, digital designers are also called upon to investigate Jitter characteristics depend on its sources: . 4 parametric issues. These parametric issues have Bounded/deterministic vs unbounded/random jitter: . 4 a signifi cant impact on the design, operation, and proof of operation of a digital product. Calculating total jitter: . 5 A case study: jitter evaluation on an eye diagram: . 6 At bit transfer rates exceeding a gigabit per second, Jitter measurement viewpoints: . 7 the analog nature of signals can become frustratingly Eye diagrams revisited: . 8 apparent. Designers can no longer remain in the ideal binary realm of 1s and 0s, verifying that their logic Histograms: . 8 performs its functions. They must also move into the The bathtub plot: . 9 parametric realm, dealing with ambiguity and Frequency-domain jitter views: . .10 measuring how well their designs work. Separating random and deterministic jitter: . .11 As new data transfer standards (Infi niBand, PCI Jitter tolerance and jitter transfer: . .12 Express, 10-Gigabit Ethernet, FibreChannel, DDR, Tools for measuring & viewing jitter: . .13 HyperTransport, and RapidIO, to name just a few) with Pulse/pattern generator: . .13 ever faster bit transfer rates are proposed and implemented, Low-level phase-noise/spectrum analyzer: . .13 designers must concern themselves with the ultimate analog nature of electronic signals: There may Real-time sampling oscilloscopes: . .14 be digital circuits that transfer binary data, but there Digital communications analyzers (DCAs): . .14 really is no such thing as a digital waveform. Bit error ratio testers (BERTs): . .15 Logic analyzers with EyeScan: . .15 This application note is for engineers who design data transfer systems and components operating at over a References: . .15 gigabit per second, and so must be concerned with the effects of jitter on their system's bit error ratio (BER). Why measure jitter? Figure 2a Ideal Clock Jitter isn’t measured just to create statistics. It is measured because jitter can cause transmission errors. If jitter results in a signal being on the “wrong side” Figure 2b Jittered Clock of the transition threshold at the sampling point, the receiving circuit will interpret that bit differently than the transmitter intended, causing a bit error (Figure 1). Figure 2c Phase vs. Time Plot Transmitted Figure 2: Jitter can cause phase advance or delay in a signal: (a) Waveform a regular clock signal with a 50% duty cycle, (b) the same clock Received signal with a sinusoidal phase perturbation at 1/10 the original Waveform signal, and with an amplitude of 4/3π, and (c) a phase versus Interpreted time plot of the phase-perturbation sinusoid. Waveform Figure 2a shows a clock signal, and Figure 2b shows Figure 1: Jitter can cause a receiver to misinterpret the same pulse train with a phase perturbation (in this transmitted digital data case, extra phase in the form of a sinusoid at 1/10 the rate of the original signal with an amplitude of 4/3 π). Jitter can be defi ned as “the deviation of the signifi cant This causes the original, very regular 50-percent-duty-cycle instances of a signal from their ideal location in time,” pulse train to become compressed and stretched over time. or more simply, how early or late a signal transitions with reference to when it should transition. In a digital Comparing the two signals shows the phase advance signal the signifi cant instances are the transition and delay. The vertical line between the two signals is (crossover) points and the time reference is generated at a point where the phase-perturbed signal has advanced from the sampled data or is externally provided. more than a half cycle, about a 240-degree phase shift or change of 4/3 π radians, with a rising edge where the This defi nition allows for many interpretations of original signal has a falling edge. Figure 2c is a plot of phase jitter. Absolute jitter is the rms (root means squared) versus time. In the real world it would be extremely unlikely evaluation of many edge measurements from an to encounter such a nice regular sine wave for phase jitter. expected location or absolute time reference. Cycle-to-cycle jitter measures the time differences between successive edges of a signal, and period jitter is an rms Eye diagrams portray jitter intuitively calculation of the difference of each period from a The most fundamental, intuitive view of jitter is provided waveform average. Of most interest in current standards by the “eye diagram.”An eye diagram is a composite view is the Time Interval Error (TIE) representation of jitter. This of all the bit periods of a captured waveform superimposed expresses the deviation in time using either the actual upon each other. In other words, the waveform transmitter clock or a reconstruction of it from the sampled trajectory from the start of period 2 to the start of data set, and takes the form of instantaneous phase varia- period 3 is overlaid on the trajectory from the start of tions for each bit period of the waveform captured. 2 Amplitude Noise Am Noise Left Left Crossing X Crossing Detector Point Sanpling Point Point Phase CDR Clock Noise One Unit Interval Noise One Bit Period Your Design Figure 3: An idealized eye diagram Figure 5: The sources of jitter can be internal or external to a circuit period 1 to the start of period 2, and so on for all bit or falling edges where data errors are most likely to periods. Figure 3 shows an idealized eye diagram, very occur. Imperfect clock recovery is shown in Figure 5 straight and symmetrical with smooth transitions (left with a t block representing phase advance or delay in and right crossing points), and a large, wide-open eye to the clock data recovery (CDR) block due to amplitude-to- provide an ideal location to sample a bit. At this point phase conversion mechanisms, phase noise of VCOs the waveform should have settled to its high or low value or oscillators, and phase locked loop design fl aws. and is least likely to result in a bit error. An obvious solution to eliminate the amplitude noise Jitter, or timing error, is caused by amplitude-to-phase contribution is to make the transition times as instanta- conversion mechanisms and phase noise. Figure 4 neous as possible. While plausible in theory, this would portrays a detailed view of a rising edge, and clearly require a high bandwidth that either doesn’t exist illustrates the mechanism for jitter caused by amplitude because the channel won’t allow it, or shouldn’t exist noise. Phase noise is portrayed as an edge variation that because it implies ineffi cient use of available bandwidth. results from a timing-circuit error as might be caused by Another solution is to move the sampling point farther noise in a crystal oscillator. In modern serial buses, the from the edge, but this implies slowing the data rate, and amplitude noise is a bigger problem in the clock-recovery data rate is usually not an alterable parameter. function than in the actual data transition, as imperfect clock recovery will cause the data to be strobed on rising Jitter reduction requires a multifaceted view Jitter can arise from sources internal and external to your circuit, as illustrated in Figure 5. You need to NOISE eliminate or reduce those sources of jitter arising internally as much as possible. Aside from logic-family noise, Logic High you have the ability to model, anticipate, and mitigate Edge Advance internal jitter performance. However, you might have no control over external sources of jitter, so you need THRESHOLD Transition to determine their net effect on your design. SAMPLING Zone POINT Logic Low IDEAL Figure 4: Amplitude and phase noise can combine to cause jitter 3 By representing jitter in terms of phase perturbation Jitter characteristics depend on its sources only, it is possible to consider different domains for Jitter on a signal will have different characteristics analysis. In mathematical terms, the phase error depending on its causes, so categorizing the sources of (advance or delay) is generalized with the function jitter becomes important for measuring and analyzing ϕj (t), so the equation for a pulsed signal affected by jitter. The fi rst category is random noise mechanisms, jitter becomes: processes that randomly introduce noise to a system. S(t) = P [2πƒdt + ϕj (t)], These sources include: where P is used to denote a sequence of periodic pulses. • thermal noise (KTB noise, which is associated with electron fl ow in conductors and increases with This leads to mathematically equivalent expressions for bandwidth, temperature, and noise resistance) jitter. Since the argument of the function is in radians, • shot noise (electron and hole noise in a semiconductor, dividing ∆ϕ(peak or rms phase) by 2π expresses jitter in which rises depending on bias current terms of the unit interval (UI), or bit period (for the pulses): and measurement bandwidth) • fl icker (pink) noise (noise that is spectrally ∆ϕ 1 J(UI) = ( 2 π ) related to /ƒ) These exist in all semiconductors and components, and Unit interval expression is useful because it allows play the most signifi cant roles in phase locked loop immediate comparison with the bit period and a designs, oscillator topologies and designs, and crystal consistent comparison of jitter between one data rate performance.
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